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Line 57... |
input i_write,
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input i_write,
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input [127:0] i_wdata,
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input [127:0] i_wdata,
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input [15:0] i_be,
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input [15:0] i_be,
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input [31:0] i_addr,
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input [31:0] i_addr,
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output [127:0] o_rdata,
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output [127:0] o_rdata,
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output o_ready,
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output o_ack,
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// Wishbone side
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// Wishbone side
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output o_valid,
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output o_valid,
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input i_accepted,
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input i_accepted,
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output o_write,
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output o_write,
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| Line 74... |
Line 74... |
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// ----------------------------------------------------
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// ----------------------------------------------------
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// Signals
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// Signals
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// ----------------------------------------------------
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// ----------------------------------------------------
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reg wbuf_used_r = 'd0;
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reg [1:0] wbuf_used_r = 'd0;
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reg [127:0] wbuf_wdata_r;
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reg [127:0] wbuf_wdata_r [1:0];
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reg [31:0] wbuf_addr_r;
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reg [31:0] wbuf_addr_r [1:0];
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reg [15:0] wbuf_be_r;
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reg [15:0] wbuf_be_r [1:0];
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reg wbuf_write_r = 'd0;
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reg [1:0] wbuf_write_r = 'd0;
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wire in_wreq = i_req && i_write;
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reg wbuf_wp_r = 'd0; // write buf write pointer
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reg wbuf_rp_r = 'd0; // write buf read pointer
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reg busy_reading_r = 'd0;
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reg busy_reading_r = 'd0;
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reg wait_rdata_valid_r = 'd0;
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wire in_wreq;
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reg ack_owed_r = 'd0;
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// ----------------------------------------------------
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// ----------------------------------------------------
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// Access Buffer
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// Access Buffer
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// ----------------------------------------------------
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// ----------------------------------------------------
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assign in_wreq = i_req && i_write;
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assign push = i_req && !busy_reading_r && (wbuf_used_r == 2'd1 || (wbuf_used_r == 2'd0 && !i_accepted));
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assign pop = o_valid && i_accepted && wbuf_used_r != 2'd0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_req && !wbuf_used_r)
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if (push && pop)
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begin
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wbuf_used_r <= wbuf_used_r;
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wbuf_used_r <= !i_accepted;
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else if (push)
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wbuf_wdata_r <= i_wdata;
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wbuf_used_r <= wbuf_used_r + 1'd1;
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wbuf_addr_r <= i_addr;
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else if (pop)
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wbuf_be_r <= i_write ? i_be : 16'hffff;
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wbuf_used_r <= wbuf_used_r - 1'd1;
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wbuf_write_r <= i_write;
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end
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always @(posedge i_clk)
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else if ( i_req && wbuf_used_r && o_valid && i_accepted)
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if (push && in_wreq && !o_ack)
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ack_owed_r = 1'd1;
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else if (!i_req && o_ack)
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ack_owed_r = 1'd0;
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always @(posedge i_clk)
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if (push)
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begin
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begin
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wbuf_used_r <= 1'd1;
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wbuf_wdata_r [wbuf_wp_r] <= i_wdata;
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wbuf_wdata_r <= i_wdata;
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wbuf_addr_r [wbuf_wp_r] <= i_addr;
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wbuf_addr_r <= i_addr;
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wbuf_be_r [wbuf_wp_r] <= i_write ? i_be : 16'hffff;
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wbuf_be_r <= i_write ? i_be : 16'hffff;
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wbuf_write_r [wbuf_wp_r] <= i_write;
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wbuf_write_r <= i_write;
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wbuf_wp_r <= !wbuf_wp_r;
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end
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end
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else if (o_valid && i_accepted && wbuf_write_r)
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wbuf_used_r <= 1'd0;
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always @(posedge i_clk)
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else if (i_rdata_valid && !wbuf_write_r)
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if (pop)
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wbuf_used_r <= 1'd0;
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wbuf_rp_r <= !wbuf_rp_r;
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// ----------------------------------------------------
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// ----------------------------------------------------
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// Output logic
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// Output logic
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// ----------------------------------------------------
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// ----------------------------------------------------
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assign o_wdata = wbuf_used_r ? wbuf_wdata_r : i_wdata;
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assign o_wdata = wbuf_used_r != 2'd0 ? wbuf_wdata_r[wbuf_rp_r] : i_wdata;
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assign o_write = wbuf_used_r ? wbuf_write_r : i_write;
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assign o_write = wbuf_used_r != 2'd0 ? wbuf_write_r[wbuf_rp_r] : i_write;
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assign o_addr = wbuf_used_r ? wbuf_addr_r : i_addr;
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assign o_addr = wbuf_used_r != 2'd0 ? wbuf_addr_r [wbuf_rp_r] : i_addr;
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assign o_be = wbuf_used_r ? wbuf_be_r : i_write ? i_be : 16'hffff;
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assign o_be = wbuf_used_r != 2'd0 ? wbuf_be_r [wbuf_rp_r] : i_write ? i_be : 16'hffff;
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assign o_valid = (wbuf_used_r || i_req) && !busy_reading_r;
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assign o_ack = (in_wreq ? (wbuf_used_r == 2'd0) : i_rdata_valid) || (ack_owed_r && pop);
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assign o_valid = (wbuf_used_r != 2'd0 || i_req) && !wait_rdata_valid_r;
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assign o_rdata = i_rdata;
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assign o_rdata = i_rdata;
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assign o_ready = in_wreq ? (!wbuf_used_r || i_accepted) : i_rdata_valid;
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always@(posedge i_clk)
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always@(posedge i_clk)
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if (o_valid && !o_write && i_accepted)
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if (o_valid && !o_write)
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busy_reading_r <= 1'd1;
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busy_reading_r <= 1'd1;
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else if (i_rdata_valid)
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else if (i_rdata_valid)
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busy_reading_r <= 1'd0;
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busy_reading_r <= 1'd0;
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always@(posedge i_clk)
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if (o_valid && !o_write && i_accepted)
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wait_rdata_valid_r <= 1'd1;
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else if (i_rdata_valid)
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wait_rdata_valid_r <= 1'd0;
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endmodule
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endmodule
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