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Line 44... |
input i_clk,
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input i_clk,
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input i_mem_stall, // Mem stage asserting stall
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input i_mem_stall, // Mem stage asserting stall
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input [31:0] i_mem_read_data, // data reads
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input [31:0] i_mem_read_data, // data reads
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input i_mem_read_data_valid, // read data is valid
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input i_mem_read_data_valid, // read data is valid
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input [9:0] i_mem_load_rd, // Rd for data reads
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input [10:0] i_mem_load_rd, // Rd for data reads
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output [31:0] o_wb_read_data, // data reads
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output [31:0] o_wb_read_data, // data reads
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output o_wb_read_data_valid, // read data is valid
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output o_wb_read_data_valid, // read data is valid
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output [9:0] o_wb_load_rd, // Rd for data reads
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output [10:0] o_wb_load_rd, // Rd for data reads
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input [31:0] i_daddress,
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input [31:0] i_daddress,
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input i_daddress_valid
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input i_daddress_valid
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);
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);
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reg [31:0] mem_read_data_r = 'd0; // Register read data from Data Cache
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reg [31:0] mem_read_data_r = 'd0; // Register read data from Data Cache
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reg mem_read_data_valid_r = 'd0; // Register read data from Data Cache
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reg mem_read_data_valid_r = 'd0; // Register read data from Data Cache
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reg [9:0] mem_load_rd_r = 'd0; // Register the Rd value for loads
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reg [10:0] mem_load_rd_r = 'd0; // Register the Rd value for loads
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reg [31:0] daddress_r = 'd0; // Register read data from Data Cache
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reg [31:0] daddress_r = 'd0; // Register read data from Data Cache
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assign o_wb_read_data = mem_read_data_r;
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assign o_wb_read_data = mem_read_data_r;
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assign o_wb_read_data_valid = mem_read_data_valid_r;
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assign o_wb_read_data_valid = mem_read_data_valid_r;
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assign o_wb_load_rd = mem_load_rd_r;
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assign o_wb_load_rd = mem_load_rd_r;
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