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https://opencores.org/ocsvn/amber/amber/trunk
[/] [amber/] [trunk/] [hw/] [vlog/] [amber25/] [a25_write_back.v] - Diff between revs 35 and 53
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| Rev 35 |
Rev 53 |
| Line 57... |
Line 57... |
);
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);
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reg [31:0] mem_read_data_r = 'd0; // Register read data from Data Cache
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reg [31:0] mem_read_data_r = 'd0; // Register read data from Data Cache
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reg mem_read_data_valid_r = 'd0; // Register read data from Data Cache
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reg mem_read_data_valid_r = 'd0; // Register read data from Data Cache
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reg [10:0] mem_load_rd_r = 'd0; // Register the Rd value for loads
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reg [10:0] mem_load_rd_r = 'd0; // Register the Rd value for loads
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reg [31:0] daddress_r = 'd0; // Register read data from Data Cache
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assign o_wb_read_data = mem_read_data_r;
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assign o_wb_read_data = mem_read_data_r;
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assign o_wb_read_data_valid = mem_read_data_valid_r;
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assign o_wb_read_data_valid = mem_read_data_valid_r;
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assign o_wb_load_rd = mem_load_rd_r;
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assign o_wb_load_rd = mem_load_rd_r;
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Line 69... |
if ( !i_mem_stall )
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if ( !i_mem_stall )
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begin
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begin
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mem_read_data_r <= i_mem_read_data;
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mem_read_data_r <= i_mem_read_data;
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mem_read_data_valid_r <= i_mem_read_data_valid;
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mem_read_data_valid_r <= i_mem_read_data_valid;
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mem_load_rd_r <= i_mem_load_rd;
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mem_load_rd_r <= i_mem_load_rd;
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daddress_r <= i_daddress;
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end
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end
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// Used by a25_decompile.v, so simulation only
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//synopsys translate_off
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reg [31:0] daddress_r = 'd0; // Register read data from Data Cache
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always @( posedge i_clk )
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if ( !i_mem_stall )
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daddress_r <= i_daddress;
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//synopsys translate_on
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endmodule
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endmodule
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