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[/] [amber/] [trunk/] [hw/] [vlog/] [amber25/] [a25_write_back.v] - Diff between revs 35 and 53

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Rev 35 Rev 53
Line 57... Line 57...
);
);
 
 
reg  [31:0]         mem_read_data_r = 'd0;          // Register read data from Data Cache
reg  [31:0]         mem_read_data_r = 'd0;          // Register read data from Data Cache
reg                 mem_read_data_valid_r = 'd0;    // Register read data from Data Cache
reg                 mem_read_data_valid_r = 'd0;    // Register read data from Data Cache
reg  [10:0]         mem_load_rd_r = 'd0;            // Register the Rd value for loads
reg  [10:0]         mem_load_rd_r = 'd0;            // Register the Rd value for loads
reg  [31:0]         daddress_r = 'd0;               // Register read data from Data Cache
 
 
 
assign o_wb_read_data       = mem_read_data_r;
assign o_wb_read_data       = mem_read_data_r;
assign o_wb_read_data_valid = mem_read_data_valid_r;
assign o_wb_read_data_valid = mem_read_data_valid_r;
assign o_wb_load_rd         = mem_load_rd_r;
assign o_wb_load_rd         = mem_load_rd_r;
 
 
Line 70... Line 69...
    if ( !i_mem_stall )
    if ( !i_mem_stall )
    begin
    begin
    mem_read_data_r         <= i_mem_read_data;
    mem_read_data_r         <= i_mem_read_data;
    mem_read_data_valid_r   <= i_mem_read_data_valid;
    mem_read_data_valid_r   <= i_mem_read_data_valid;
    mem_load_rd_r           <= i_mem_load_rd;
    mem_load_rd_r           <= i_mem_load_rd;
    daddress_r              <= i_daddress;
 
    end
    end
 
 
 
 
 
// Used by a25_decompile.v, so simulation only
 
//synopsys translate_off    
 
reg  [31:0]         daddress_r = 'd0;               // Register read data from Data Cache
 
always @( posedge i_clk )
 
    if ( !i_mem_stall )
 
        daddress_r              <= i_daddress;
 
//synopsys translate_on    
 
 
endmodule
endmodule
 
 
 
 
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