| Line 426... |
Line 426... |
reg [15:0] TxLength;
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reg [15:0] TxLength;
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reg [15:0] LatchedTxLength;
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reg [15:0] LatchedTxLength;
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reg [14:11] TxStatus;
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reg [14:11] TxStatus;
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reg [14:13] RxStatus;
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reg [14:13] RxStatus;
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wire [14:13] RxStatus_s;
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reg TxStartFrm_wb;
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reg TxStartFrm_wb;
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reg TxRetry_wb;
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reg TxRetry_wb;
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reg TxAbort_wb;
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reg TxAbort_wb;
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reg TxDone_wb;
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reg TxDone_wb;
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| Line 1350... |
Line 1351... |
assign WrapTxStatusBit = TxStatus[13];
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assign WrapTxStatusBit = TxStatus[13];
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assign PerPacketPad = TxStatus[12];
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assign PerPacketPad = TxStatus[12];
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assign PerPacketCrcEn = TxStatus[11];
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assign PerPacketCrcEn = TxStatus[11];
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assign RxIRQEn = RxStatus[14];
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assign RxIRQEn = RxStatus_s[14];
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assign WrapRxStatusBit = RxStatus[13];
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assign WrapRxStatusBit = RxStatus_s[13];
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// Temporary Tx and Rx buffer descriptor address
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// Temporary Tx and Rx buffer descriptor address
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assign TempTxBDAddress[7:1] = {7{ TxStatusWrite & ~WrapTxStatusBit}} & (TxBDAddress + 1'b1) ; // Tx BD increment or wrap (last BD)
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assign TempTxBDAddress[7:1] = {7{ TxStatusWrite & ~WrapTxStatusBit}} & (TxBDAddress + 1'b1) ; // Tx BD increment or wrap (last BD)
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assign TempRxBDAddress[7:1] = {7{ WrapRxStatusBit}} & (r_TxBDNum[6:0]) | // Using first Rx BD
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assign TempRxBDAddress[7:1] = {7{ WrapRxStatusBit}} & (r_TxBDNum[6:0]) | // Using first Rx BD
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| Line 1385... |
Line 1386... |
RxBDAddress <=#Tp TempRxBDAddress;
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RxBDAddress <=#Tp TempRxBDAddress;
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end
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end
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wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
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wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
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assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 4'h0, RxStatusInLatched};
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assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus_s, 4'h0, RxStatusInLatched};
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assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
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assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
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// Signals used for various purposes
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// Signals used for various purposes
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assign TxRetryPulse = TxRetry_wb & ~TxRetry_wb_q;
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assign TxRetryPulse = TxRetry_wb & ~TxRetry_wb_q;
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| Line 1872... |
Line 1873... |
else
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else
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if(RxEn & RxEn_q & RxBDRead)
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if(RxEn & RxEn_q & RxBDRead)
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RxStatus <=#Tp ram_do[14:13];
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RxStatus <=#Tp ram_do[14:13];
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end
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end
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// Need the RxStatus 1 cycle early when doing an RxStatusWrite immediately after a read
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assign RxStatus_s = (RxEn & RxEn_q & RxBDRead) ? ram_do[14:13] : RxStatus;
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// RxReady generation
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// RxReady generation
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always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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