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[/] [amber/] [trunk/] [hw/] [vlog/] [ethmac/] [eth_wishbone.v] - Diff between revs 2 and 61

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Rev 2 Rev 61
Line 426... Line 426...
reg    [15:0]   TxLength;
reg    [15:0]   TxLength;
reg    [15:0]   LatchedTxLength;
reg    [15:0]   LatchedTxLength;
reg   [14:11]   TxStatus;
reg   [14:11]   TxStatus;
 
 
reg   [14:13]   RxStatus;
reg   [14:13]   RxStatus;
 
wire  [14:13]   RxStatus_s;
 
 
reg             TxStartFrm_wb;
reg             TxStartFrm_wb;
reg             TxRetry_wb;
reg             TxRetry_wb;
reg             TxAbort_wb;
reg             TxAbort_wb;
reg             TxDone_wb;
reg             TxDone_wb;
Line 1350... Line 1351...
assign WrapTxStatusBit  = TxStatus[13];
assign WrapTxStatusBit  = TxStatus[13];
assign PerPacketPad     = TxStatus[12];
assign PerPacketPad     = TxStatus[12];
assign PerPacketCrcEn   = TxStatus[11];
assign PerPacketCrcEn   = TxStatus[11];
 
 
 
 
assign RxIRQEn         = RxStatus[14];
assign RxIRQEn         = RxStatus_s[14];
assign WrapRxStatusBit = RxStatus[13];
assign WrapRxStatusBit = RxStatus_s[13];
 
 
 
 
// Temporary Tx and Rx buffer descriptor address 
// Temporary Tx and Rx buffer descriptor address 
assign TempTxBDAddress[7:1] = {7{ TxStatusWrite     & ~WrapTxStatusBit}}   & (TxBDAddress + 1'b1) ; // Tx BD increment or wrap (last BD)
assign TempTxBDAddress[7:1] = {7{ TxStatusWrite     & ~WrapTxStatusBit}}   & (TxBDAddress + 1'b1) ; // Tx BD increment or wrap (last BD)
assign TempRxBDAddress[7:1] = {7{ WrapRxStatusBit}} & (r_TxBDNum[6:0])     | // Using first Rx BD
assign TempRxBDAddress[7:1] = {7{ WrapRxStatusBit}} & (r_TxBDNum[6:0])     | // Using first Rx BD
Line 1385... Line 1386...
    RxBDAddress <=#Tp TempRxBDAddress;
    RxBDAddress <=#Tp TempRxBDAddress;
end
end
 
 
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
 
 
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 4'h0, RxStatusInLatched};
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus_s, 4'h0, RxStatusInLatched};
assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
 
 
 
 
// Signals used for various purposes
// Signals used for various purposes
assign TxRetryPulse   = TxRetry_wb   & ~TxRetry_wb_q;
assign TxRetryPulse   = TxRetry_wb   & ~TxRetry_wb_q;
Line 1872... Line 1873...
  else
  else
  if(RxEn & RxEn_q & RxBDRead)
  if(RxEn & RxEn_q & RxBDRead)
    RxStatus <=#Tp ram_do[14:13];
    RxStatus <=#Tp ram_do[14:13];
end
end
 
 
 
// Need the RxStatus 1 cycle early when doing an RxStatusWrite immediately after a read
 
assign RxStatus_s = (RxEn & RxEn_q & RxBDRead) ? ram_do[14:13] : RxStatus;
 
 
 
 
// RxReady generation
// RxReady generation
always @ (posedge WB_CLK_I or posedge Reset)
always @ (posedge WB_CLK_I or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)

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