| Line 62... |
Line 62... |
);
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);
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wire start_write;
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wire start_write;
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wire start_read;
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wire start_read;
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reg start_read_r = 'd0;
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wire [WB_DWIDTH-1:0] read_data;
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wire [WB_DWIDTH-1:0] read_data;
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wire [WB_DWIDTH-1:0] write_data;
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wire [WB_DWIDTH-1:0] write_data;
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wire [WB_SWIDTH-1:0] byte_enable;
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wire [WB_SWIDTH-1:0] byte_enable;
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wire [MADDR_WIDTH-1:0] address;
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wire [MADDR_WIDTH-1:0] address;
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`ifdef AMBER_WISHBONE_DEBUG
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reg [7:0] jitter_r = 8'h0f;
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reg [1:0] start_read_r = 'd0;
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`else
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reg start_read_r = 'd0;
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`endif
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// Can't start a write while a read is completing. The ack for the read cycle
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// Can't start a write while a read is completing. The ack for the read cycle
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// needs to be sent first
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// needs to be sent first
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assign start_write = i_wb_stb && i_wb_we && !start_read_r;
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`ifdef AMBER_WISHBONE_DEBUG
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assign start_read = i_wb_stb && !i_wb_we && !start_read_r;
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assign start_write = i_wb_stb && i_wb_we && !(|start_read_r) && jitter_r[0];
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`else
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assign start_write = i_wb_stb && i_wb_we && !(|start_read_r);
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`endif
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assign start_read = i_wb_stb && !i_wb_we && !(|start_read_r);
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`ifdef AMBER_WISHBONE_DEBUG
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always @( posedge i_wb_clk )
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jitter_r <= {jitter_r[6:0], jitter_r[7] ^ jitter_r[4] ^ jitter_r[1]};
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always @( posedge i_wb_clk )
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always @( posedge i_wb_clk )
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if (start_read)
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start_read_r <= {3'd0, start_read};
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else if (o_wb_ack)
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start_read_r <= 'd0;
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else
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start_read_r <= {start_read_r[2:0], start_read};
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`else
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always @( posedge i_wb_clk )
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start_read_r <= start_read;
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start_read_r <= start_read;
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`endif
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assign o_wb_err = 1'd0;
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assign o_wb_err = 1'd0;
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assign write_data = i_wb_dat;
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assign write_data = i_wb_dat;
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assign byte_enable = i_wb_sel;
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assign byte_enable = i_wb_sel;
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assign o_wb_dat = read_data;
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assign o_wb_dat = read_data;
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assign address = i_wb_adr[MADDR_WIDTH+3:4];
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assign address = i_wb_adr[MADDR_WIDTH+3:4];
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`ifdef AMBER_WISHBONE_DEBUG
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assign o_wb_ack = i_wb_stb && ( start_write || start_read_r[jitter_r[1]] );
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`else
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assign o_wb_ack = i_wb_stb && ( start_write || start_read_r );
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assign o_wb_ack = i_wb_stb && ( start_write || start_read_r );
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`endif
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// ------------------------------------------------------
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// ------------------------------------------------------
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// Instantiate SRAMs
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// Instantiate SRAMs
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// ------------------------------------------------------
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// ------------------------------------------------------
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