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Line 43... |
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module boot_mem32 #(
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module boot_mem32 #(
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parameter WB_DWIDTH = 32,
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parameter WB_DWIDTH = 32,
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parameter WB_SWIDTH = 4,
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parameter WB_SWIDTH = 4,
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parameter MADDR_WIDTH = 11
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parameter MADDR_WIDTH = 12
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)(
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)(
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input i_wb_clk, // WISHBONE clock
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input i_wb_clk, // WISHBONE clock
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input [31:0] i_wb_adr,
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input [31:0] i_wb_adr,
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input [WB_SWIDTH-1:0] i_wb_sel,
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input [WB_SWIDTH-1:0] i_wb_sel,
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Line 117... |
// ------------------------------------------------------
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// ------------------------------------------------------
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// Instantiate SRAMs
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// Instantiate SRAMs
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// ------------------------------------------------------
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// ------------------------------------------------------
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//
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//
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`ifdef XILINX_FPGA
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`ifdef XILINX_FPGA
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xs6_sram_4096x32_byte_en
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`ifdef XILINX_SPARTAN6_FPGA
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xs6_sram_2048x32_byte_en
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`endif
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`ifdef XILINX_VIRTEX6_FPGA
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xv6_sram_2048x32_byte_en
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`endif
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#(
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#(
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// This file holds a software image used for FPGA simulations
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// This file holds a software image used for FPGA simulations
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// This pre-processor syntax works with both the simulator
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// This pre-processor syntax works with both the simulator
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// and ISE, which I couldn't get to work with giving it the
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// and ISE, which I couldn't get to work with giving it the
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// file name as a define.
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// file name as a define.
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`ifdef BOOT_MEM_PARAMS_FILE
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`ifdef BOOT_MEM_PARAMS_FILE
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`include `BOOT_MEM_PARAMS_FILE
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`include `BOOT_MEM_PARAMS_FILE
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`else
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`else
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`ifdef BOOT_LOADER_ETHMAC
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`include "boot-loader-ethmac_memparams32.v"
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`else
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// default file
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// default file
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`include "boot-loader_memparams32.v"
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`include "boot-loader_memparams32.v"
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`endif
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`endif
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`endif
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)
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)
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`endif
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`endif
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`ifndef XILINX_FPGA
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`ifndef XILINX_FPGA
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