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[/] [amber/] [trunk/] [hw/] [vlog/] [system/] [clocks_resets.v] - Diff between revs 2 and 14
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Line 237... |
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`ifndef XILINX_FPGA
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`ifndef XILINX_FPGA
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localparam [7:0] FULL_COUNT = `AMBER_CLK_DIVIDER / 4;
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real brd_clk_period = 6000; // use starting value of 6000pS
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localparam [7:0] HALF_COUNT = FULL_COUNT / 2;
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real pll_clk_period = 1000; // use starting value of 1000pS
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real brd_temp;
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// e.g. Divide clock by 6 to get 33MHz
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reg pll_clk_beh;
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reg [7:0] clk_div_count;
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reg sys_clk_beh;
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integer pll_div_count = 0;
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// measure input clock period
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initial
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initial
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begin
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begin
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clk_div_count <= FULL_COUNT - 1'd3;
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@ (posedge i_brd_clk_p)
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forever @ (posedge i_brd_clk_p)
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brd_temp = $time;
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if ( clk_div_count == ( FULL_COUNT - 1'd1 ) )
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@ (posedge i_brd_clk_p)
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clk_div_count <= 8'h0;
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brd_clk_period = $time - brd_temp;
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pll_clk_period = brd_clk_period / 4;
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end
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// Generate an 800MHz pll clock based off the input clock
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always @( posedge i_brd_clk_p )
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begin
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pll_clk_beh = 1'd1;
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# ( pll_clk_period / 2 )
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pll_clk_beh = 1'd0;
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# ( pll_clk_period / 2 )
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pll_clk_beh = 1'd1;
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# ( pll_clk_period / 2 )
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pll_clk_beh = 1'd0;
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# ( pll_clk_period / 2 )
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pll_clk_beh = 1'd1;
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# ( pll_clk_period / 2 )
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pll_clk_beh = 1'd0;
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# ( pll_clk_period / 2 )
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pll_clk_beh = 1'd1;
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# ( pll_clk_period / 2 )
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pll_clk_beh = 1'd0;
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end
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// Divide the pll clock down to get the system clock
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always @( pll_clk_beh )
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begin
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if ( pll_div_count == (
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`AMBER_CLK_DIVIDER
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* 2 ) - 1 )
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pll_div_count <= 'd0;
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else
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else
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clk_div_count <= clk_div_count + 1'd1;
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pll_div_count <= pll_div_count + 1'd1;
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if ( pll_div_count == 0 )
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sys_clk_beh = 1'd1;
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else if ( pll_div_count ==
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`AMBER_CLK_DIVIDER
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)
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sys_clk_beh = 1'd0;
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end
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end
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assign o_sys_clk = clk_div_count < HALF_COUNT;
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assign o_sys_clk = sys_clk_beh;
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assign rst0 = i_brd_rst;
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assign rst0 = i_brd_rst;
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assign calib_done_33mhz = 1'd1;
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assign calib_done_33mhz = 1'd1;
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assign o_clk_200 = i_brd_clk_p;
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assign o_clk_200 = i_brd_clk_p;
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`endif
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`endif
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