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// from http://www.opencores.org/lgpl.shtml //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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// //
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//////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////
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module interrupt_controller (
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module interrupt_controller #(
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parameter WB_DWIDTH = 32,
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parameter WB_SWIDTH = 4
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)(
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input i_clk,
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input i_clk,
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input [31:0] i_wb_adr,
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input [31:0] i_wb_adr,
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input [3:0] i_wb_sel,
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input [WB_SWIDTH-1:0] i_wb_sel,
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input i_wb_we,
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input i_wb_we,
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output [31:0] o_wb_dat,
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output [WB_DWIDTH-1:0] o_wb_dat,
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input [31:0] i_wb_dat,
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input [WB_DWIDTH-1:0] i_wb_dat,
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input i_wb_cyc,
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input i_wb_cyc,
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input i_wb_stb,
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input i_wb_stb,
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output o_wb_ack,
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output o_wb_ack,
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output o_wb_err,
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output o_wb_err,
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wire firq_0;
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wire firq_0;
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wire irq_1;
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wire irq_1;
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wire firq_1;
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wire firq_1;
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// Wishbone interface
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// Wishbone interface
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reg [31:0] wb_rdata = 'd0;
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reg [31:0] wb_rdata32 = 'd0;
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wire wb_start_write;
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wire wb_start_write;
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wire wb_start_read;
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wire wb_start_read;
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reg wb_start_read_d1 = 'd0;
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reg wb_start_read_d1 = 'd0;
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wire [31:0] wb_wdata32;
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// ======================================================
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// ======================================================
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// Wishbone Interface
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// Wishbone Interface
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// ======================================================
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// ======================================================
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assign wb_start_read = i_wb_stb && !i_wb_we && !o_wb_ack;
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assign wb_start_read = i_wb_stb && !i_wb_we && !o_wb_ack;
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always @( posedge i_clk )
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always @( posedge i_clk )
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wb_start_read_d1 <= wb_start_read;
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wb_start_read_d1 <= wb_start_read;
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assign o_wb_dat = wb_rdata;
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assign o_wb_err = 1'd0;
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assign o_wb_err = 1'd0;
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assign o_wb_ack = i_wb_stb && ( wb_start_write || wb_start_read_d1 );
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assign o_wb_ack = i_wb_stb && ( wb_start_write || wb_start_read_d1 );
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generate
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if (WB_DWIDTH == 128)
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begin : wb128
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assign wb_wdata32 = i_wb_adr[3:2] == 2'd3 ? i_wb_dat[127:96] :
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i_wb_adr[3:2] == 2'd2 ? i_wb_dat[ 95:64] :
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i_wb_adr[3:2] == 2'd1 ? i_wb_dat[ 63:32] :
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i_wb_dat[ 31: 0] ;
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assign o_wb_dat = {4{wb_rdata32}};
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end
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else
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begin : wb32
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assign wb_wdata32 = i_wb_dat;
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assign o_wb_dat = wb_rdata32;
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end
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endgenerate
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// ======================================
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// ======================================
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// Interrupts
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// Interrupts
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// ======================================
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// ======================================
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assign raw_interrupts = {23'd0,
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assign raw_interrupts = {23'd0,
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// ========================================================
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// ========================================================
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always @( posedge i_clk )
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always @( posedge i_clk )
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if ( wb_start_read )
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if ( wb_start_read )
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case ( i_wb_adr[15:0] )
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case ( i_wb_adr[15:0] )
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AMBER_IC_IRQ0_ENABLESET: wb_rdata <= irq0_enable_reg;
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AMBER_IC_IRQ0_ENABLESET: wb_rdata32 <= irq0_enable_reg;
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AMBER_IC_FIRQ0_ENABLESET: wb_rdata <= firq0_enable_reg;
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AMBER_IC_FIRQ0_ENABLESET: wb_rdata32 <= firq0_enable_reg;
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AMBER_IC_IRQ0_RAWSTAT: wb_rdata <= raw_interrupts;
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AMBER_IC_IRQ0_RAWSTAT: wb_rdata32 <= raw_interrupts;
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AMBER_IC_IRQ0_STATUS: wb_rdata <= irq0_interrupts;
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AMBER_IC_IRQ0_STATUS: wb_rdata32 <= irq0_interrupts;
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AMBER_IC_FIRQ0_RAWSTAT: wb_rdata <= raw_interrupts;
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AMBER_IC_FIRQ0_RAWSTAT: wb_rdata32 <= raw_interrupts;
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AMBER_IC_FIRQ0_STATUS: wb_rdata <= firq0_interrupts;
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AMBER_IC_FIRQ0_STATUS: wb_rdata32 <= firq0_interrupts;
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AMBER_IC_INT_SOFTSET_0: wb_rdata <= {31'd0, softint_0_reg};
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AMBER_IC_INT_SOFTSET_0: wb_rdata32 <= {31'd0, softint_0_reg};
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AMBER_IC_INT_SOFTCLEAR_0: wb_rdata <= {31'd0, softint_0_reg};
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AMBER_IC_INT_SOFTCLEAR_0: wb_rdata32 <= {31'd0, softint_0_reg};
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AMBER_IC_IRQ1_ENABLESET: wb_rdata <= irq1_enable_reg;
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AMBER_IC_IRQ1_ENABLESET: wb_rdata32 <= irq1_enable_reg;
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AMBER_IC_FIRQ1_ENABLESET: wb_rdata <= firq1_enable_reg;
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AMBER_IC_FIRQ1_ENABLESET: wb_rdata32 <= firq1_enable_reg;
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AMBER_IC_IRQ1_RAWSTAT: wb_rdata <= raw_interrupts;
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AMBER_IC_IRQ1_RAWSTAT: wb_rdata32 <= raw_interrupts;
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AMBER_IC_IRQ1_STATUS: wb_rdata <= irq1_interrupts;
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AMBER_IC_IRQ1_STATUS: wb_rdata32 <= irq1_interrupts;
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AMBER_IC_FIRQ1_RAWSTAT: wb_rdata <= raw_interrupts;
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AMBER_IC_FIRQ1_RAWSTAT: wb_rdata32 <= raw_interrupts;
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AMBER_IC_FIRQ1_STATUS: wb_rdata <= firq1_interrupts;
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AMBER_IC_FIRQ1_STATUS: wb_rdata32 <= firq1_interrupts;
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AMBER_IC_INT_SOFTSET_1: wb_rdata <= {31'd0, softint_1_reg};
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AMBER_IC_INT_SOFTSET_1: wb_rdata32 <= {31'd0, softint_1_reg};
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AMBER_IC_INT_SOFTCLEAR_1: wb_rdata <= {31'd0, softint_1_reg};
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AMBER_IC_INT_SOFTCLEAR_1: wb_rdata32 <= {31'd0, softint_1_reg};
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default: wb_rdata <= 32'h22334455;
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default: wb_rdata32 <= 32'h22334455;
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endcase
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endcase
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