URL
https://opencores.org/ocsvn/amber/amber/trunk
[/] [amber/] [trunk/] [hw/] [vlog/] [system/] [main_mem.v] - Diff between revs 2 and 11
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 2 |
Rev 11 |
| Line 44... |
Line 44... |
|
|
|
|
module main_mem
|
module main_mem
|
(
|
(
|
input i_clk,
|
input i_clk,
|
|
input i_mem_ctrl, // 0=128MB, 1=32MB
|
// Wishbone Bus
|
// Wishbone Bus
|
input [31:0] i_wb_adr,
|
input [31:0] i_wb_adr,
|
input [3:0] i_wb_sel,
|
input [3:0] i_wb_sel,
|
input i_wb_we,
|
input i_wb_we,
|
output reg [31:0] o_wb_dat = 'd0,
|
output reg [31:0] o_wb_dat = 'd0,
|
| Line 94... |
Line 94... |
wr_mask <= i_wb_adr[3:2] == 2'd0 ? { 12'hfff, ~i_wb_sel } :
|
wr_mask <= i_wb_adr[3:2] == 2'd0 ? { 12'hfff, ~i_wb_sel } :
|
i_wb_adr[3:2] == 2'd1 ? { 8'hff, ~i_wb_sel, 4'hf } :
|
i_wb_adr[3:2] == 2'd1 ? { 8'hff, ~i_wb_sel, 4'hf } :
|
i_wb_adr[3:2] == 2'd2 ? { 4'hf, ~i_wb_sel, 8'hff } :
|
i_wb_adr[3:2] == 2'd2 ? { 4'hf, ~i_wb_sel, 8'hff } :
|
{ ~i_wb_sel, 12'hfff } ;
|
{ ~i_wb_sel, 12'hfff } ;
|
wr_data <= {4{i_wb_dat}};
|
wr_data <= {4{i_wb_dat}};
|
addr_d1 <= i_wb_adr[29:2];
|
|
|
// Wrap the address at 32 MB, or full width
|
|
addr_d1 <= i_mem_ctrl ? {5'd0, i_wb_adr[24:2]} : i_wb_adr[29:2];
|
|
|
if ( wr_en )
|
if ( wr_en )
|
ram [addr_d1[27:2]] <= masked_wdata;
|
ram [addr_d1[27:2]] <= masked_wdata;
|
end
|
end
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.