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// from http://www.opencores.org/lgpl.shtml //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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// //
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//////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////
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module main_mem
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module main_mem#(
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(
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parameter WB_DWIDTH = 32,
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parameter WB_SWIDTH = 4
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)(
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input i_clk,
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input i_clk,
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input i_mem_ctrl, // 0=128MB, 1=32MB
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input i_mem_ctrl, // 0=128MB, 1=32MB
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// Wishbone Bus
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// Wishbone Bus
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input [31:0] i_wb_adr,
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input [31:0] i_wb_adr,
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input [3:0] i_wb_sel,
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input [WB_SWIDTH-1:0] i_wb_sel,
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input i_wb_we,
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input i_wb_we,
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output reg [31:0] o_wb_dat = 'd0,
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output [WB_DWIDTH-1:0] o_wb_dat,
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input [31:0] i_wb_dat,
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input [WB_DWIDTH-1:0] i_wb_dat,
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input i_wb_cyc,
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input i_wb_cyc,
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input i_wb_stb,
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input i_wb_stb,
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output o_wb_ack,
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output o_wb_ack,
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output o_wb_err
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output o_wb_err
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assign busy = start_read_d1 || start_read_d2;
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assign busy = start_read_d1 || start_read_d2;
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assign o_wb_err = 'd0;
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assign o_wb_err = 'd0;
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generate
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if (WB_DWIDTH == 128)
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begin : wb128
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reg [127:0] wb_rdata128 = 'd0;
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// ------------------------------------------------------
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// ------------------------------------------------------
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// Write
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// Write for 32-bit wishbone
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// ------------------------------------------------------
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always @( posedge i_clk )
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begin
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wr_en <= start_write;
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wr_mask <= ~ i_wb_sel;
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wr_data <= i_wb_dat;
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// Wrap the address at 32 MB, or full width
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addr_d1 <= i_mem_ctrl ? {5'd0, i_wb_adr[24:2]} : i_wb_adr[29:2];
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if ( wr_en )
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ram [addr_d1[27:2]] <= masked_wdata;
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end
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for (i=0;i<16;i=i+1) begin : masked
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assign masked_wdata[8*i+7:8*i] = wr_mask[i] ? rd_data[8*i+7:8*i] : wr_data[8*i+7:8*i];
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end
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// ------------------------------------------------------
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// Read for 32-bit wishbone
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// ------------------------------------------------------
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assign rd_data = ram [addr_d1[27:2]];
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always @( posedge i_clk )
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begin
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start_read_d1 <= start_read;
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start_read_d2 <= start_read_d1;
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if ( start_read_d1 )
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begin
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wb_rdata128 <= rd_data;
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end
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end
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assign o_wb_dat = wb_rdata128 ;
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assign o_wb_ack = i_wb_stb && ( start_write || start_read_d2 );
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end
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else
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begin : wb32
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reg [31:0] wb_rdata32 = 'd0;
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// ------------------------------------------------------
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// Write for 32-bit wishbone
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// ------------------------------------------------------
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// ------------------------------------------------------
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always @( posedge i_clk )
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always @( posedge i_clk )
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begin
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begin
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wr_en <= start_write;
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wr_en <= start_write;
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wr_mask <= i_wb_adr[3:2] == 2'd0 ? { 12'hfff, ~i_wb_sel } :
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wr_mask <= i_wb_adr[3:2] == 2'd0 ? { 12'hfff, ~i_wb_sel } :
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if ( wr_en )
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if ( wr_en )
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ram [addr_d1[27:2]] <= masked_wdata;
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ram [addr_d1[27:2]] <= masked_wdata;
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end
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end
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generate
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for (i=0;i<16;i=i+1) begin : masked
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for (i=0;i<16;i=i+1) begin : masked
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assign masked_wdata[8*i+7:8*i] = wr_mask[i] ? rd_data[8*i+7:8*i] : wr_data[8*i+7:8*i];
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assign masked_wdata[8*i+7:8*i] = wr_mask[i] ? rd_data[8*i+7:8*i] : wr_data[8*i+7:8*i];
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end
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end
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endgenerate
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// ------------------------------------------------------
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// ------------------------------------------------------
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// Read
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// Read for 32-bit wishbone
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// ------------------------------------------------------
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// ------------------------------------------------------
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assign rd_data = ram [addr_d1[27:2]];
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assign rd_data = ram [addr_d1[27:2]];
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always @( posedge i_clk )
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always @( posedge i_clk )
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begin
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begin
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start_read_d1 <= start_read;
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start_read_d1 <= start_read;
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start_read_d2 <= start_read_d1;
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start_read_d2 <= start_read_d1;
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if ( start_read_d1 )
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if ( start_read_d1 )
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begin
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begin
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o_wb_dat <= addr_d1[1:0] == 2'd0 ? rd_data[ 31: 0] :
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wb_rdata32 <= addr_d1[1:0] == 2'd0 ? rd_data[ 31: 0] :
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addr_d1[1:0] == 2'd1 ? rd_data[ 63:32] :
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addr_d1[1:0] == 2'd1 ? rd_data[ 63:32] :
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addr_d1[1:0] == 2'd2 ? rd_data[ 95:64] :
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addr_d1[1:0] == 2'd2 ? rd_data[ 95:64] :
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rd_data[127:96] ;
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rd_data[127:96] ;
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end
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end
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end
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end
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assign o_wb_dat = wb_rdata32 ;
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assign o_wb_ack = i_wb_stb && ( start_write || start_read_d2 );
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assign o_wb_ack = i_wb_stb && ( start_write || start_read_d2 );
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end
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endgenerate
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endmodule
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endmodule
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