| Line 119... |
Line 119... |
wire c3_p0_cmd_full;
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wire c3_p0_cmd_full;
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wire c3_p0_wr_full;
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wire c3_p0_wr_full;
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`endif
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`endif
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|
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wire phy_init_done;
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wire phy_init_done;
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wire test_mem_ctrl;
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|
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// ======================================
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// ======================================
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// Xilinx Virtex-6 DDR3 Controller connections
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// Xilinx Virtex-6 DDR3 Controller connections
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// ======================================
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// ======================================
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`ifdef XILINX_VIRTEX6_FPGA
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`ifdef XILINX_VIRTEX6_FPGA
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| Line 380... |
Line 381... |
test_module u_test_module (
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test_module u_test_module (
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.i_clk ( sys_clk ),
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.i_clk ( sys_clk ),
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|
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.o_irq ( test_reg_irq ),
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.o_irq ( test_reg_irq ),
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.o_firq ( test_reg_firq ),
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.o_firq ( test_reg_firq ),
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.o_mem_ctrl ( test_mem_ctrl ),
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.i_wb_adr ( s_wb_adr [5] ),
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.i_wb_adr ( s_wb_adr [5] ),
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.i_wb_sel ( s_wb_sel [5] ),
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.i_wb_sel ( s_wb_sel [5] ),
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.i_wb_we ( s_wb_we [5] ),
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.i_wb_we ( s_wb_we [5] ),
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.o_wb_dat ( s_wb_dat_r[5] ),
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.o_wb_dat ( s_wb_dat_r[5] ),
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.i_wb_dat ( s_wb_dat_w[5] ),
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.i_wb_dat ( s_wb_dat_w[5] ),
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| Line 456... |
Line 458... |
|
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assign phy_init_done = 1'd1;
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assign phy_init_done = 1'd1;
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|
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main_mem u_main_mem (
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main_mem u_main_mem (
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.i_clk ( sys_clk ),
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.i_clk ( sys_clk ),
|
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.i_mem_ctrl ( test_mem_ctrl ),
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.i_wb_adr ( s_wb_adr [2] ),
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.i_wb_adr ( s_wb_adr [2] ),
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.i_wb_sel ( s_wb_sel [2] ),
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.i_wb_sel ( s_wb_sel [2] ),
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.i_wb_we ( s_wb_we [2] ),
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.i_wb_we ( s_wb_we [2] ),
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.o_wb_dat ( s_wb_dat_r[2] ),
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.o_wb_dat ( s_wb_dat_r[2] ),
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.i_wb_dat ( s_wb_dat_w[2] ),
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.i_wb_dat ( s_wb_dat_w[2] ),
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| Line 489... |
Line 492... |
.o_wr_mask ( c3_p0_wr_mask ),
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.o_wr_mask ( c3_p0_wr_mask ),
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.o_wr_data ( c3_p0_wr_data ),
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.o_wr_data ( c3_p0_wr_data ),
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.i_rd_data ( c3_p0_rd_data ),
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.i_rd_data ( c3_p0_rd_data ),
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.i_rd_empty ( c3_p0_rd_empty ),
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.i_rd_empty ( c3_p0_rd_empty ),
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|
|
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.i_mem_ctrl ( test_mem_ctrl ),
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.i_wb_adr ( s_wb_adr [2] ),
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.i_wb_adr ( s_wb_adr [2] ),
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.i_wb_sel ( s_wb_sel [2] ),
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.i_wb_sel ( s_wb_sel [2] ),
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.i_wb_we ( s_wb_we [2] ),
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.i_wb_we ( s_wb_we [2] ),
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.o_wb_dat ( s_wb_dat_r[2] ),
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.o_wb_dat ( s_wb_dat_r[2] ),
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.i_wb_dat ( s_wb_dat_w[2] ),
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.i_wb_dat ( s_wb_dat_w[2] ),
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| Line 592... |
Line 596... |
.i_ddr_rd_valid ( xv6_rd_data_valid ),
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.i_ddr_rd_valid ( xv6_rd_data_valid ),
|
|
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.i_phy_init_done ( phy_init_done1 ),
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.i_phy_init_done ( phy_init_done1 ),
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.o_phy_init_done ( phy_init_done ), // delayed version
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.o_phy_init_done ( phy_init_done ), // delayed version
|
|
|
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.i_mem_ctrl ( test_mem_ctrl ),
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.i_wb_adr ( s_wb_adr [2] ),
|
.i_wb_adr ( s_wb_adr [2] ),
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.i_wb_sel ( s_wb_sel [2] ),
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.i_wb_sel ( s_wb_sel [2] ),
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.i_wb_we ( s_wb_we [2] ),
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.i_wb_we ( s_wb_we [2] ),
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.o_wb_dat ( s_wb_dat_r[2] ),
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.o_wb_dat ( s_wb_dat_r[2] ),
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.i_wb_dat ( s_wb_dat_w[2] ),
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.i_wb_dat ( s_wb_dat_w[2] ),
|
