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wire            c3_p0_wr_full;

wire            c3_p0_wr_full;

`endif

`endif

wire            phy_init_done;

wire            phy_init_done;

wire            test_mem_ctrl;

wire            test_mem_ctrl;

// ======================================

// ======================================

// Xilinx Virtex-6 DDR3 Controller connections

// Xilinx Virtex-6 DDR3 Controller connections

// ======================================

// ======================================

`ifdef XILINX_VIRTEX6_FPGA

`ifdef XILINX_VIRTEX6_FPGA

// -------------------------------------------------------------

// -------------------------------------------------------------

// Instantiate Amber Processor Core

// Instantiate Amber Processor Core

// -------------------------------------------------------------

// -------------------------------------------------------------

    .i_clk          ( sys_clk         ),

    .i_clk          ( sys_clk         ),

    .i_irq          ( amber_irq       ),

    .i_irq          ( amber_irq       ),

    .i_firq         ( amber_firq      ),

    .i_firq         ( amber_firq      ),

    .o_wb_adr       ( m_wb_adr  [1]   ),

    .o_wb_adr       ( m_wb_adr  [1]   ),

    .o_wb_sel       ( m_wb_sel  [1]   ),

    .o_wb_sel       ( m_wb_sel  [1]   ),

    .o_wb_we        ( m_wb_we   [1]   ),

    .o_wb_we        ( m_wb_we   [1]   ),

    .i_wb_dat       ( m_wb_dat_r[1]   ),

    .i_wb_dat       ( m_wb_dat_r[1]   ),

);

);

// Ethernet MII PHY reset

// Ethernet MII PHY reset

assign phy_reset_n = !sys_rst;

assign phy_reset_n = !sys_rst;

// -------------------------------------------------------------

// -------------------------------------------------------------

// Instantiate Boot Memory - 8KBytes of Embedded SRAM

// Instantiate Boot Memory - 8KBytes of Embedded SRAM

// -------------------------------------------------------------

// -------------------------------------------------------------

boot_mem u_boot_mem (

boot_mem u_boot_mem (