| Line 70... |
Line 70... |
output ddr3_ck_p,
|
output ddr3_ck_p,
|
output ddr3_ck_n,
|
output ddr3_ck_n,
|
|
|
`ifdef XILINX_SPARTAN6_FPGA
|
`ifdef XILINX_SPARTAN6_FPGA
|
inout mcb3_rzq,
|
inout mcb3_rzq,
|
//inout mcb3_zio,
|
|
`endif
|
`endif
|
|
|
|
|
// Ethmac B100 MAC to PHY Interface
|
// Ethmac B100 MAC to PHY Interface
|
input mtx_clk_pad_i,
|
input mtx_clk_pad_i,
|
| Line 94... |
Line 93... |
output [3:0] led
|
output [3:0] led
|
);
|
);
|
|
|
|
|
wire sys_clk; // System clock
|
wire sys_clk; // System clock
|
wire sys_rst; // Active low reset, synchronous to sys_clk
|
wire sys_rst; // Active high reset, synchronous to sys_clk
|
wire clk_200; // 200MHz from board
|
wire clk_200; // 200MHz from board
|
|
|
|
|
// ======================================
|
// ======================================
|
// Xilinx MCB DDR3 Controller connections
|
// Xilinx MCB DDR3 Controller connections
|
| Line 243... |
Line 242... |
|
|
|
|
// -------------------------------------------------------------
|
// -------------------------------------------------------------
|
// Instantiate B100 Ethernet MAC
|
// Instantiate B100 Ethernet MAC
|
// -------------------------------------------------------------
|
// -------------------------------------------------------------
|
|
|
eth_top u_eth_top (
|
eth_top u_eth_top (
|
.wb_clk_i ( sys_clk ),
|
.wb_clk_i ( sys_clk ),
|
.wb_rst_i ( sys_rst ),
|
.wb_rst_i ( sys_rst ),
|
|
|
// WISHBONE slave
|
// WISHBONE slave
|
| Line 307... |
Line 305... |
// T is high for tri-state output
|
// T is high for tri-state output
|
.T ( ~md_padoe_o )
|
.T ( ~md_padoe_o )
|
);
|
);
|
|
|
// Ethernet MII PHY reset
|
// Ethernet MII PHY reset
|
//assign phy_reset_n = !sys_rst;
|
|
|
|
// Halt core until system is ready
|
// Halt core until system is ready
|
assign system_rdy = phy_init_done && !sys_rst;
|
assign system_rdy = phy_init_done && !sys_rst;
|
|
|
// -------------------------------------------------------------
|
// -------------------------------------------------------------
|
// Instantiate Boot Memory - 8KBytes of Embedded SRAM
|
// Instantiate Boot Memory - 8KBytes of Embedded SRAM
|
| Line 581... |
Line 577... |
.mcb3_dram_reset_n ( ddr3_reset_n ),
|
.mcb3_dram_reset_n ( ddr3_reset_n ),
|
.mcb3_dram_cke ( ddr3_cke ),
|
.mcb3_dram_cke ( ddr3_cke ),
|
.mcb3_dram_udm ( ddr3_dm[1] ),
|
.mcb3_dram_udm ( ddr3_dm[1] ),
|
.mcb3_dram_dm ( ddr3_dm[0] ),
|
.mcb3_dram_dm ( ddr3_dm[0] ),
|
.mcb3_rzq ( mcb3_rzq ),
|
.mcb3_rzq ( mcb3_rzq ),
|
// .mcb3_zio ( mcb3_zio ),
|
|
.mcb3_dram_udqs ( ddr3_dqs_p[1] ),
|
.mcb3_dram_udqs ( ddr3_dqs_p[1] ),
|
.mcb3_dram_dqs ( ddr3_dqs_p[0] ),
|
.mcb3_dram_dqs ( ddr3_dqs_p[0] ),
|
.mcb3_dram_udqs_n ( ddr3_dqs_n[1] ),
|
.mcb3_dram_udqs_n ( ddr3_dqs_n[1] ),
|
.mcb3_dram_dqs_n ( ddr3_dqs_n[0] ),
|
.mcb3_dram_dqs_n ( ddr3_dqs_n[0] ),
|
.mcb3_dram_ck ( ddr3_ck_p ),
|
.mcb3_dram_ck ( ddr3_ck_p ),
|
