Subversion Repositories amber

reg [2:0]       sim_ctrl_reg        = 'd0; // 0 = fpga, other values for simulations

reg [2:0]       sim_ctrl_reg        = 'd0; // 0 = fpga, other values for simulations

reg             mem_ctrl_reg        = 'd0; // 0 = 128MB, 1 = 32MB main memory

reg             mem_ctrl_reg        = 'd0; // 0 = 128MB, 1 = 32MB main memory

reg [31:0]      test_status_reg     = 'd0;

reg [31:0]      test_status_reg     = 'd0;

reg             test_status_set     = 'd0; // used to terminate tests

reg             test_status_set     = 'd0; // used to terminate tests

wire            wb_start_write;

wire            wb_start_write;

wire            wb_start_read;

wire            wb_start_read;

reg             wb_start_read_d1    = 'd0;

reg             wb_start_read_d1    = 'd0;

reg  [31:0]     wb_rdata            = 'd0;

reg  [31:0]     wb_rdata            = 'd0;

            AMBER_TEST_UART_TXD:         wb_rdata <= {24'd0, tb_uart_txd_reg};

            AMBER_TEST_UART_TXD:         wb_rdata <= {24'd0, tb_uart_txd_reg};

            //synopsys translate_on

            //synopsys translate_on

            AMBER_TEST_SIM_CTRL:         wb_rdata <= {29'd0, sim_ctrl_reg};

            AMBER_TEST_SIM_CTRL:         wb_rdata <= {29'd0, sim_ctrl_reg};

            AMBER_TEST_MEM_CTRL:         wb_rdata <= {31'd0, mem_ctrl_reg};

            AMBER_TEST_MEM_CTRL:         wb_rdata <= {31'd0, mem_ctrl_reg};

            default:                     wb_rdata <= 32'haabbccdd;

            default:                     wb_rdata <= 32'haabbccdd;

        endcase

        endcase

    if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_STATUS )

    if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_STATUS )

        test_status_set <= 1'd1;

        test_status_set <= 1'd1;

// ======================================

// ======================================

// Memory Configuration Register Write

// Memory Configuration Register Write

// ======================================

// ======================================

always @( posedge i_clk )

always @( posedge i_clk )

    if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_MEM_CTRL )

    if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_MEM_CTRL )

        mem_ctrl_reg <= i_wb_dat[0];

        mem_ctrl_reg <= i_wb_dat[0];