| Line 56... |
Line 56... |
output [WB_DWIDTH-1:0] o_wb_dat,
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output [WB_DWIDTH-1:0] o_wb_dat,
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input [WB_DWIDTH-1:0] i_wb_dat,
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input [WB_DWIDTH-1:0] i_wb_dat,
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input i_wb_cyc,
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input i_wb_cyc,
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input i_wb_stb,
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input i_wb_stb,
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output o_wb_ack,
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output o_wb_ack,
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output o_wb_err
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output o_wb_err,
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output [3:0] o_led,
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output o_phy_rst_n
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);
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);
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`include "register_addresses.v"
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`include "register_addresses.v"
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| Line 87... |
Line 88... |
wire wb_start_read;
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wire wb_start_read;
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reg wb_start_read_d1 = 'd0;
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reg wb_start_read_d1 = 'd0;
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reg [31:0] wb_rdata32 = 'd0;
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reg [31:0] wb_rdata32 = 'd0;
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wire [31:0] wb_wdata32;
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wire [31:0] wb_wdata32;
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reg [3:0] led_reg = 'd0;
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reg phy_rst_reg = 'd0;
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// Can't start a write while a read is completing. The ack for the read cycle
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// Can't start a write while a read is completing. The ack for the read cycle
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// needs to be sent first
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// needs to be sent first
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assign wb_start_write = i_wb_stb && i_wb_we && !wb_start_read_d1;
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assign wb_start_write = i_wb_stb && i_wb_we && !wb_start_read_d1;
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assign wb_start_read = i_wb_stb && !i_wb_we && !o_wb_ack;
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assign wb_start_read = i_wb_stb && !i_wb_we && !o_wb_ack;
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| Line 98... |
Line 103... |
wb_start_read_d1 <= wb_start_read;
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wb_start_read_d1 <= wb_start_read;
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assign o_wb_ack = i_wb_stb && ( wb_start_write || wb_start_read_d1 );
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assign o_wb_ack = i_wb_stb && ( wb_start_write || wb_start_read_d1 );
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assign o_wb_err = 1'd0;
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assign o_wb_err = 1'd0;
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assign o_mem_ctrl = mem_ctrl_reg;
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assign o_mem_ctrl = mem_ctrl_reg;
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assign o_led = led_reg;
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assign o_phy_rst_n = phy_rst_reg;
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generate
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generate
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if (WB_DWIDTH == 128)
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if (WB_DWIDTH == 128)
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begin : wb128
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begin : wb128
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assign wb_wdata32 = i_wb_adr[3:2] == 2'd3 ? i_wb_dat[127:96] :
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assign wb_wdata32 = i_wb_adr[3:2] == 2'd3 ? i_wb_dat[127:96] :
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| Line 117... |
Line 123... |
assign wb_wdata32 = i_wb_dat;
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assign wb_wdata32 = i_wb_dat;
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assign o_wb_dat = wb_rdata32;
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assign o_wb_dat = wb_rdata32;
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end
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end
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endgenerate
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endgenerate
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// ========================================================
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// ========================================================
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// Register Reads
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// Register Reads
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// ========================================================
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// ========================================================
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always @( posedge i_clk )
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always @( posedge i_clk )
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if ( wb_start_read )
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if ( wb_start_read )
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| Line 158... |
Line 165... |
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AMBER_TEST_SIM_CTRL: wb_rdata32 <= {29'd0, sim_ctrl_reg};
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AMBER_TEST_SIM_CTRL: wb_rdata32 <= {29'd0, sim_ctrl_reg};
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AMBER_TEST_MEM_CTRL: wb_rdata32 <= {31'd0, mem_ctrl_reg};
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AMBER_TEST_MEM_CTRL: wb_rdata32 <= {31'd0, mem_ctrl_reg};
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AMBER_TEST_CYCLES: wb_rdata32 <= cycles_reg;
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AMBER_TEST_CYCLES: wb_rdata32 <= cycles_reg;
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AMBER_TEST_LED: wb_rdata32 <= {27'd0, led_reg};
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AMBER_TEST_PHY_RST: wb_rdata32 <= {31'd0, phy_rst_reg};
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default: wb_rdata32 <= 32'haabbccdd;
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default: wb_rdata32 <= 32'haabbccdd;
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endcase
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endcase
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| Line 253... |
Line 262... |
// ======================================
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// ======================================
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always @( posedge i_clk )
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always @( posedge i_clk )
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if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_STATUS )
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if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_STATUS )
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test_status_set <= 1'd1;
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test_status_set <= 1'd1;
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// ======================================
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// ======================================
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// Cycles counter
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// Cycles counter
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// ======================================
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// ======================================
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always @( posedge i_clk )
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always @( posedge i_clk )
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cycles_reg <= cycles_reg + 1'd1;
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cycles_reg <= cycles_reg + 1'd1;
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// ======================================
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// ======================================
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// Memory Configuration Register Write
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// Memory Configuration Register Write
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// ======================================
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// ======================================
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always @( posedge i_clk )
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always @( posedge i_clk )
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if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_MEM_CTRL )
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if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_MEM_CTRL )
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mem_ctrl_reg <= wb_wdata32[0];
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mem_ctrl_reg <= wb_wdata32[0];
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// ======================================
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// ======================================
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// Test LEDs
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// ======================================
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always @( posedge i_clk )
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if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_LED )
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led_reg <= wb_wdata32[3:0];
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// ======================================
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// PHY Reset Register
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// ======================================
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always @( posedge i_clk )
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if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_PHY_RST )
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phy_rst_reg <= wb_wdata32[0];
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// ======================================
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// Test UART registers
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// Test UART registers
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// ======================================
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// ======================================
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// These control the testbench UART, not the real
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// These control the testbench UART, not the real
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// UART in system
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// UART in system
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