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// from http://www.opencores.org/lgpl.shtml //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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// //
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//////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////
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module timer_module (
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module timer_module #(
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parameter WB_DWIDTH = 32,
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parameter WB_SWIDTH = 4
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)(
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input i_clk,
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input i_clk,
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input [31:0] i_wb_adr,
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input [31:0] i_wb_adr,
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input [3:0] i_wb_sel,
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input [WB_SWIDTH-1:0] i_wb_sel,
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input i_wb_we,
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input i_wb_we,
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output [31:0] o_wb_dat,
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output [WB_DWIDTH-1:0] o_wb_dat,
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input [31:0] i_wb_dat,
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input [WB_DWIDTH-1:0] i_wb_dat,
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input i_wb_cyc,
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input i_wb_cyc,
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input i_wb_stb,
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input i_wb_stb,
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output o_wb_ack,
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output o_wb_ack,
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output o_wb_err,
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output o_wb_err,
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reg timer0_int_reg = 'd0; // interrupt flag
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reg timer0_int_reg = 'd0; // interrupt flag
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reg timer1_int_reg = 'd0; // interrupt flag
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reg timer1_int_reg = 'd0; // interrupt flag
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reg timer2_int_reg = 'd0; // interrupt flag
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reg timer2_int_reg = 'd0; // interrupt flag
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// Wishbone interface
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// Wishbone interface
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reg [31:0] wb_rdata = 'd0;
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reg [31:0] wb_rdata32 = 'd0;
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wire wb_start_write;
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wire wb_start_write;
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wire wb_start_read;
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wire wb_start_read;
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reg wb_start_read_d1 = 'd0;
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reg wb_start_read_d1 = 'd0;
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wire [31:0] wb_wdata32;
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// ======================================================
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// ======================================================
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// Wishbone Interface
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// Wishbone Interface
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// ======================================================
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// ======================================================
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assign wb_start_read = i_wb_stb && !i_wb_we && !o_wb_ack;
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assign wb_start_read = i_wb_stb && !i_wb_we && !o_wb_ack;
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always @( posedge i_clk )
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always @( posedge i_clk )
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wb_start_read_d1 <= wb_start_read;
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wb_start_read_d1 <= wb_start_read;
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assign o_wb_dat = wb_rdata;
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assign o_wb_err = 1'd0;
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assign o_wb_err = 1'd0;
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assign o_wb_ack = i_wb_stb && ( wb_start_write || wb_start_read_d1 );
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assign o_wb_ack = i_wb_stb && ( wb_start_write || wb_start_read_d1 );
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generate
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if (WB_DWIDTH == 128)
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begin : wb128
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assign wb_wdata32 = i_wb_adr[3:2] == 2'd3 ? i_wb_dat[127:96] :
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i_wb_adr[3:2] == 2'd2 ? i_wb_dat[ 95:64] :
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i_wb_adr[3:2] == 2'd1 ? i_wb_dat[ 63:32] :
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i_wb_dat[ 31: 0] ;
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assign o_wb_dat = {4{wb_rdata32}};
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end
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else
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begin : wb32
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assign wb_wdata32 = i_wb_dat;
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assign o_wb_dat = wb_rdata32;
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end
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endgenerate
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// ========================================================
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// ========================================================
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// Timer Interrupt Outputs
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// Timer Interrupt Outputs
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// ========================================================
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// ========================================================
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assign o_timer_int = { timer2_int_reg,
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assign o_timer_int = { timer2_int_reg,
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// Register Reads
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// Register Reads
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// ========================================================
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// ========================================================
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always @( posedge i_clk )
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always @( posedge i_clk )
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if ( wb_start_read )
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if ( wb_start_read )
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case ( i_wb_adr[15:0] )
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case ( i_wb_adr[15:0] )
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AMBER_TM_TIMER0_LOAD: wb_rdata <= {16'd0, timer0_load_reg};
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AMBER_TM_TIMER0_LOAD: wb_rdata32 <= {16'd0, timer0_load_reg};
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AMBER_TM_TIMER1_LOAD: wb_rdata <= {16'd0, timer1_load_reg};
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AMBER_TM_TIMER1_LOAD: wb_rdata32 <= {16'd0, timer1_load_reg};
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AMBER_TM_TIMER2_LOAD: wb_rdata <= {16'd0, timer2_load_reg};
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AMBER_TM_TIMER2_LOAD: wb_rdata32 <= {16'd0, timer2_load_reg};
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AMBER_TM_TIMER0_CTRL: wb_rdata <= {24'd0,
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AMBER_TM_TIMER0_CTRL: wb_rdata32 <= {24'd0,
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timer0_ctrl_reg[7:6],
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timer0_ctrl_reg[7:6],
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2'd0,
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2'd0,
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timer0_ctrl_reg[3:2],
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timer0_ctrl_reg[3:2],
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2'd0
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2'd0
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};
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};
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AMBER_TM_TIMER1_CTRL: wb_rdata <= {24'd0,
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AMBER_TM_TIMER1_CTRL: wb_rdata32 <= {24'd0,
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timer1_ctrl_reg[7:6],
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timer1_ctrl_reg[7:6],
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2'd0,
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2'd0,
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timer1_ctrl_reg[3:2],
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timer1_ctrl_reg[3:2],
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2'd0
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2'd0
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};
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};
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AMBER_TM_TIMER2_CTRL: wb_rdata <= {24'd0,
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AMBER_TM_TIMER2_CTRL: wb_rdata32 <= {24'd0,
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timer2_ctrl_reg[7:6],
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timer2_ctrl_reg[7:6],
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2'd0,
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2'd0,
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timer2_ctrl_reg[3:2],
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timer2_ctrl_reg[3:2],
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2'd0
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2'd0
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};
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};
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AMBER_TM_TIMER0_VALUE: wb_rdata <= {16'd0, timer0_value_reg[23:8]};
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AMBER_TM_TIMER0_VALUE: wb_rdata32 <= {16'd0, timer0_value_reg[23:8]};
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AMBER_TM_TIMER1_VALUE: wb_rdata <= {16'd0, timer1_value_reg[23:8]};
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AMBER_TM_TIMER1_VALUE: wb_rdata32 <= {16'd0, timer1_value_reg[23:8]};
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AMBER_TM_TIMER2_VALUE: wb_rdata <= {16'd0, timer2_value_reg[23:8]};
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AMBER_TM_TIMER2_VALUE: wb_rdata32 <= {16'd0, timer2_value_reg[23:8]};
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default: wb_rdata <= 32'h66778899;
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default: wb_rdata32 <= 32'h66778899;
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endcase
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endcase
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