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Line 51... |
// //
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// //
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//////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////
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`include "system_config_defines.v"
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`include "system_config_defines.v"
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// Normally AMBER_UART_BAUD is defined in the system_config_defines.v file.
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`ifndef AMBER_UART_BAUD
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`define AMBER_UART_BAUD 230400
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`endif
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module uart (
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module uart (
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input i_clk,
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input i_clk,
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input [31:0] i_wb_adr,
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input [31:0] i_wb_adr,
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input [3:0] i_wb_sel,
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input [3:0] i_wb_sel,
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Line 99... |
TXD_STOP3 = 4'd12;
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TXD_STOP3 = 4'd12;
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localparam [3:0] RXD_IDLE = 4'd0,
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localparam [3:0] RXD_IDLE = 4'd0,
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RXD_START = 4'd1,
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RXD_START = 4'd1,
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RXD_START_MID = 4'd2,
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RXD_START_MID = 4'd2,
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RXD_DATA0 = 4'd3,
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RXD_START_MID1 = 4'd3,
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RXD_DATA1 = 4'd4,
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RXD_DATA0 = 4'd4,
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RXD_DATA2 = 4'd5,
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RXD_DATA1 = 4'd5,
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RXD_DATA3 = 4'd6,
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RXD_DATA2 = 4'd6,
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RXD_DATA4 = 4'd7,
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RXD_DATA3 = 4'd7,
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RXD_DATA5 = 4'd8,
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RXD_DATA4 = 4'd8,
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RXD_DATA6 = 4'd9,
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RXD_DATA5 = 4'd9,
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RXD_DATA7 = 4'd10,
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RXD_DATA6 = 4'd10,
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RXD_STOP = 4'd11;
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RXD_DATA7 = 4'd11,
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RXD_STOP = 4'd12;
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localparam RX_INTERRUPT_COUNT = 24'h3fffff;
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localparam RX_INTERRUPT_COUNT = 24'h3fffff;
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Line 120... |
// Baud Rate Configuration
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// Baud Rate Configuration
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// -------------------------------------------------------------------------
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// -------------------------------------------------------------------------
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`ifndef Veritak
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`ifndef Veritak
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localparam real UART_BAUD = `AMBER_UART_BAUD; // Hz
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localparam real UART_BAUD = `AMBER_UART_BAUD; // Hz
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`ifdef XILINX_VIRTEX6_FPGA
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localparam real CLK_FREQ = 1000.0 / `AMBER_CLK_DIVIDER ; // MHz
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`else
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localparam real CLK_FREQ = 800.0 / `AMBER_CLK_DIVIDER ; // MHz
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localparam real CLK_FREQ = 800.0 / `AMBER_CLK_DIVIDER ; // MHz
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`endif
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localparam real UART_BIT_PERIOD = 1000000000 / UART_BAUD; // nS
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localparam real UART_BIT_PERIOD = 1000000000 / UART_BAUD; // nS
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localparam real UART_WORD_PERIOD = ( UART_BIT_PERIOD * 12 ); // nS
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localparam real UART_WORD_PERIOD = ( UART_BIT_PERIOD * 12 ); // nS
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localparam real CLK_PERIOD = 1000 / CLK_FREQ; // nS
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localparam real CLK_PERIOD = 1000 / CLK_FREQ; // nS
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localparam real CLKS_PER_WORD = UART_WORD_PERIOD / CLK_PERIOD;
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localparam real CLKS_PER_WORD = UART_WORD_PERIOD / CLK_PERIOD;
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localparam real CLKS_PER_BIT = CLKS_PER_WORD / 12;
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localparam real CLKS_PER_BIT = CLKS_PER_WORD / 12;
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Line 575... |
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RXD_START :
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RXD_START :
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// Filter out glitches and jaggedy transitions
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// Filter out glitches and jaggedy transitions
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if ( rx_start )
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if ( rx_start )
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begin
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begin
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rxd_state <= RXD_START_MID;
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rxd_state <= RXD_START_MID1;
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restart_rx_bit_count <= 1'd1;
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restart_rx_bit_count <= 1'd1;
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end
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end
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else
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else
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restart_rx_bit_count <= 1'd0;
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restart_rx_bit_count <= 1'd0;
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// This state just delays the check on the
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// rx_bit_pulse_count value by 1 clock cycle to
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// give it time to reset
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RXD_START_MID1 :
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rxd_state <= RXD_START_MID;
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RXD_START_MID :
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RXD_START_MID :
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if ( rx_bit_pulse_count == RX_HALFPULSE_COUNT )
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if ( rx_bit_pulse_count == RX_HALFPULSE_COUNT )
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begin
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begin
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rxd_state <= RXD_DATA0;
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rxd_state <= RXD_DATA0;
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restart_rx_bit_count <= 1'd1;
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restart_rx_bit_count <= 1'd1;
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Line 948... |
txd_state == TXD_STOP3 ? "TXD_STOP3" :
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txd_state == TXD_STOP3 ? "TXD_STOP3" :
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"UNKNOWN" ;
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"UNKNOWN" ;
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assign xRXD_STATE = rxd_state == RXD_IDLE ? "RXD_IDLE" :
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assign xRXD_STATE = rxd_state == RXD_IDLE ? "RXD_IDLE" :
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rxd_state == RXD_START ? "RXD_START" :
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rxd_state == RXD_START ? "RXD_START" :
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rxd_state == RXD_START_MID1 ? "RXD_START_MID1":
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rxd_state == RXD_START_MID ? "RXD_START_MID" :
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rxd_state == RXD_START_MID ? "RXD_START_MID" :
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rxd_state == RXD_DATA0 ? "RXD_DATA0" :
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rxd_state == RXD_DATA0 ? "RXD_DATA0" :
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rxd_state == RXD_DATA1 ? "RXD_DATA1" :
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rxd_state == RXD_DATA1 ? "RXD_DATA1" :
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rxd_state == RXD_DATA2 ? "RXD_DATA2" :
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rxd_state == RXD_DATA2 ? "RXD_DATA2" :
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rxd_state == RXD_DATA3 ? "RXD_DATA3" :
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rxd_state == RXD_DATA3 ? "RXD_DATA3" :
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