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`ifndef Veritak
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`ifndef Veritak
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localparam real UART_BAUD = `AMBER_UART_BAUD; // Hz
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localparam real UART_BAUD = `AMBER_UART_BAUD; // Hz
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`ifdef XILINX_VIRTEX6_FPGA
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`ifdef XILINX_VIRTEX6_FPGA
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localparam real CLK_FREQ = 1000.0 / `AMBER_CLK_DIVIDER ; // MHz
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localparam real CLK_FREQ = 1200.0 / `AMBER_CLK_DIVIDER ; // MHz
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`else
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`else
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localparam real CLK_FREQ = 800.0 / `AMBER_CLK_DIVIDER ; // MHz
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localparam real CLK_FREQ = 800.0 / `AMBER_CLK_DIVIDER ; // MHz
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`endif
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`endif
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localparam real UART_BIT_PERIOD = 1000000000 / UART_BAUD; // nS
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localparam real UART_BIT_PERIOD = 1000000000 / UART_BAUD; // nS
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