| Line 58... |
Line 58... |
input i_wb_cyc,
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input i_wb_cyc,
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input i_wb_stb,
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input i_wb_stb,
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output o_wb_ack,
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output o_wb_ack,
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output o_wb_err,
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output o_wb_err,
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output reg o_cmd_en = 'd0, // Command Enable
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output o_cmd_en, // Command Enable
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output reg [2:0] o_cmd_instr = 'd0, // write = 000, read = 001
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output reg [2:0] o_cmd_instr = 'd0, // write = 000, read = 001
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output reg [29:0] o_cmd_byte_addr = 'd0, // Memory address
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output reg [29:0] o_cmd_byte_addr = 'd0, // Memory address
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input i_cmd_full, // DDR3 I/F Command FIFO is full
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input i_cmd_full, // DDR3 I/F Command FIFO is full
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input i_wr_full, // DDR3 I/F Write Data FIFO is full
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input i_wr_full, // DDR3 I/F Write Data FIFO is full
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output reg o_wr_en = 'd0, // Write data enable
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output o_wr_en, // Write data enable
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output reg [15:0] o_wr_mask = 'd0, // 1 bit per byte
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output reg [15:0] o_wr_mask = 'd0, // 1 bit per byte
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output reg [127:0] o_wr_data = 'd0, // 16 bytes write data
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output reg [127:0] o_wr_data = 'd0, // 16 bytes write data
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input [127:0] i_rd_data, // 16 bytes of read data
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input [127:0] i_rd_data, // 16 bytes of read data
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input i_rd_empty // low when read data is valid
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input i_rd_empty // low when read data is valid
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| Line 81... |
Line 81... |
reg start_read_hold = 'd0;
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reg start_read_hold = 'd0;
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reg [29:0] wb_adr_d1;
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reg [29:0] wb_adr_d1;
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wire ddr3_busy;
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wire ddr3_busy;
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reg read_ack = 'd0;
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reg read_ack = 'd0;
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reg read_ready = 1'd1;
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reg read_ready = 1'd1;
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reg cmd_en_r = 'd0;
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reg wr_en_r = 'd0;
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assign start_write = i_wb_stb && i_wb_we && !start_read_d1;
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assign start_write = i_wb_stb && i_wb_we && !start_read_d1;
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assign start_read = i_wb_stb && !i_wb_we && read_ready;
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assign start_read = i_wb_stb && !i_wb_we && read_ready;
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assign ddr3_busy = i_cmd_full || i_wr_full;
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assign ddr3_busy = i_cmd_full;// || i_wr_full;
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assign o_wb_err = 'd0;
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assign o_wb_err = 'd0;
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// ------------------------------------------------------
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// ------------------------------------------------------
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// Outputs
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// Outputs
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// ------------------------------------------------------
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// ------------------------------------------------------
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// Command FIFO
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// Command FIFO
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always @( posedge i_clk )
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always @( posedge i_clk )
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if ( !ddr3_busy )
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begin
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begin
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o_cmd_byte_addr <= {wb_adr_d1[29:4], 4'd0};
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o_cmd_byte_addr <= {wb_adr_d1[29:4], 4'd0};
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o_cmd_en <= !ddr3_busy && ( start_write_d1 || start_read_d1 );
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cmd_en_r <= ( start_write_d1 || start_read_d1 );
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o_cmd_instr <= start_write_d1 ? 3'd0 : 3'd1;
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o_cmd_instr <= start_write_d1 ? 3'd0 : 3'd1;
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end
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end
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assign o_cmd_en = cmd_en_r && !i_cmd_full;
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// ------------------------------------------------------
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// ------------------------------------------------------
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// Write
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// Write
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// ------------------------------------------------------
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// ------------------------------------------------------
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always @( posedge i_clk )
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always @( posedge i_clk )
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if ( !ddr3_busy )
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begin
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begin
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o_wr_en <= start_write;
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wr_en_r <= start_write;
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o_wr_mask <= i_wb_adr[3:2] == 2'd0 ? { 12'hfff, ~i_wb_sel } :
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o_wr_mask <= i_wb_adr[3:2] == 2'd0 ? { 12'hfff, ~i_wb_sel } :
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i_wb_adr[3:2] == 2'd1 ? { 8'hff, ~i_wb_sel, 4'hf } :
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i_wb_adr[3:2] == 2'd1 ? { 8'hff, ~i_wb_sel, 4'hf } :
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i_wb_adr[3:2] == 2'd2 ? { 4'hf, ~i_wb_sel, 8'hff } :
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i_wb_adr[3:2] == 2'd2 ? { 4'hf, ~i_wb_sel, 8'hff } :
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{ ~i_wb_sel, 12'hfff } ;
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{ ~i_wb_sel, 12'hfff } ;
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o_wr_data <= {4{i_wb_dat}};
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o_wr_data <= {4{i_wb_dat}};
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end
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end
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assign o_wr_en = wr_en_r && !i_cmd_full;
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// ------------------------------------------------------
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// ------------------------------------------------------
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// Read
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// Read
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// ------------------------------------------------------
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// ------------------------------------------------------
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always @( posedge i_clk )
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always @( posedge i_clk )
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| Line 128... |
Line 133... |
if ( read_ack )
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if ( read_ack )
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read_ready <= 1'd1;
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read_ready <= 1'd1;
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else if ( start_read )
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else if ( start_read )
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read_ready <= 1'd0;
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read_ready <= 1'd0;
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if ( !ddr3_busy )
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begin
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start_write_d1 <= start_write;
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start_write_d1 <= start_write;
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start_read_d1 <= start_read;
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start_read_d1 <= start_read;
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wb_adr_d1 <= i_mem_ctrl ? {5'd0, i_wb_adr[24:0]} : i_wb_adr[29:0];
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wb_adr_d1 <= i_mem_ctrl ? {5'd0, i_wb_adr[24:0]} : i_wb_adr[29:0];
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end
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if ( start_read )
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if ( start_read )
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start_read_hold <= 1'd1;
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start_read_hold <= 1'd1;
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else if ( read_ack )
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else if ( read_ack )
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start_read_hold <= 1'd0;
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start_read_hold <= 1'd0;
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| Line 149... |
Line 157... |
end
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end
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else
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else
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read_ack <= 1'd0;
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read_ack <= 1'd0;
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end
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end
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assign o_wb_ack = i_wb_stb && ( start_write || read_ack );
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assign o_wb_ack = i_wb_stb && ( start_write || read_ack ) && !i_cmd_full;
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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