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// from http://www.opencores.org/lgpl.shtml //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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// //
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//////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////
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module wb_xs6_ddr3_bridge
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module wb_xs6_ddr3_bridge #(
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(
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parameter WB_DWIDTH = 32,
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parameter WB_SWIDTH = 4
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)(
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input i_clk,
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input i_clk,
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input i_mem_ctrl, // 0=128MB, 1=32MB
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input i_mem_ctrl, // 0=128MB, 1=32MB
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// Wishbone Bus
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// Wishbone Bus
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input [31:0] i_wb_adr,
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input [31:0] i_wb_adr,
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input [3:0] i_wb_sel,
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input [WB_SWIDTH-1:0] i_wb_sel,
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input i_wb_we,
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input i_wb_we,
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output reg [31:0] o_wb_dat = 'd0,
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output reg [WB_DWIDTH-1:0] o_wb_dat = 'd0,
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input [31:0] i_wb_dat,
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input [WB_DWIDTH-1:0] i_wb_dat,
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input i_wb_cyc,
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input i_wb_cyc,
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input i_wb_stb,
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input i_wb_stb,
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output o_wb_ack,
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output o_wb_ack,
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output o_wb_err,
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output o_wb_err,
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input [127:0] i_rd_data, // 16 bytes of read data
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input [127:0] i_rd_data, // 16 bytes of read data
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input i_rd_empty // low when read data is valid
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input i_rd_empty // low when read data is valid
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);
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);
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wire start_write;
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wire write_request;
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wire start_read;
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wire read_request;
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reg start_write_d1;
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reg write_request_r;
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reg start_read_d1;
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reg read_request_r;
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reg start_read_hold = 'd0;
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reg read_active_r = 'd0;
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reg [29:0] wb_adr_d1;
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reg [29:0] wb_adr_r;
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wire ddr3_busy;
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reg cmd_full_r = 1'd0;
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reg read_ack = 'd0;
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reg read_ack_r = 'd0;
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reg read_ready = 1'd1;
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reg read_ready = 1'd1;
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reg cmd_en_r = 'd0;
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reg cmd_en_r = 'd0;
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reg wr_en_r = 'd0;
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reg wr_en_r = 'd0;
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wire write_ack;
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assign start_write = i_wb_stb && i_wb_we && !start_read_d1;
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// Buffer 1 write request
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assign start_read = i_wb_stb && !i_wb_we && read_ready;
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reg write_buf_r = 1'd0;
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assign ddr3_busy = i_cmd_full;// || i_wr_full;
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reg [WB_SWIDTH-1:0] wb_sel_buf_r = 'd0;
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reg [WB_DWIDTH-1:0] wb_dat_buf_r = 'd0;
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reg [31:0] wb_adr_buf_r = 'd0;
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wire [WB_SWIDTH-1:0] wb_sel;
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wire [WB_DWIDTH-1:0] wb_dat;
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wire [31:0] wb_adr;
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assign write_request = i_wb_stb && i_wb_we && !read_request_r;
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assign read_request = i_wb_stb && !i_wb_we && read_ready;
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assign o_wb_err = 'd0;
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assign o_wb_err = 'd0;
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// ------------------------------------------------------
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// ------------------------------------------------------
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// Outputs
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// Outputs
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// ------------------------------------------------------
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// ------------------------------------------------------
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always @( posedge i_clk )
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cmd_full_r <= i_cmd_full;
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// Command FIFO
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// Command FIFO
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always @( posedge i_clk )
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always @( posedge i_clk )
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if ( !ddr3_busy )
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if ( !i_cmd_full )
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begin
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begin
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o_cmd_byte_addr <= {wb_adr_d1[29:4], 4'd0};
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o_cmd_byte_addr <= {wb_adr_r[29:4], 4'd0};
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cmd_en_r <= ( start_write_d1 || start_read_d1 );
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cmd_en_r <= ( write_request_r || read_request_r );
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o_cmd_instr <= start_write_d1 ? 3'd0 : 3'd1;
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o_cmd_instr <= write_request_r ? 3'd0 : 3'd1;
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end
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end
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assign o_cmd_en = cmd_en_r && !i_cmd_full;
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assign o_cmd_en = cmd_en_r && !i_cmd_full;
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// ------------------------------------------------------
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// Write Buffer
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// ------------------------------------------------------
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always @( posedge i_clk )
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if ( i_cmd_full && write_request )
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begin
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write_buf_r <= 1'd1;
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wb_sel_buf_r <= i_wb_sel;
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wb_dat_buf_r <= i_wb_dat;
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wb_adr_buf_r <= i_wb_adr;
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end
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else if ( !i_cmd_full )
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write_buf_r <= 1'd0;
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// ------------------------------------------------------
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// ------------------------------------------------------
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// Write
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// Write
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// ------------------------------------------------------
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// ------------------------------------------------------
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// Select between incoming reqiests and the write request buffer
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assign wb_sel = write_buf_r ? wb_sel_buf_r : i_wb_sel;
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assign wb_dat = write_buf_r ? wb_dat_buf_r : i_wb_dat;
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assign wb_adr = write_buf_r ? wb_adr_buf_r : i_wb_adr;
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generate
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if (WB_DWIDTH == 32) begin :wb32w
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always @( posedge i_clk )
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always @( posedge i_clk )
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if ( !ddr3_busy )
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if ( !i_cmd_full )
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begin
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begin
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wr_en_r <= start_write;
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wr_en_r <= write_request || write_buf_r;
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o_wr_mask <= i_wb_adr[3:2] == 2'd0 ? { 12'hfff, ~i_wb_sel } :
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o_wr_mask <= wb_adr[3:2] == 2'd0 ? { 12'hfff, ~wb_sel } :
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i_wb_adr[3:2] == 2'd1 ? { 8'hff, ~i_wb_sel, 4'hf } :
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wb_adr[3:2] == 2'd1 ? { 8'hff, ~wb_sel, 4'hf } :
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i_wb_adr[3:2] == 2'd2 ? { 4'hf, ~i_wb_sel, 8'hff } :
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wb_adr[3:2] == 2'd2 ? { 4'hf, ~wb_sel, 8'hff } :
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{ ~i_wb_sel, 12'hfff } ;
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{ ~wb_sel, 12'hfff } ;
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o_wr_data <= {4{i_wb_dat}};
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o_wr_data <= {4{wb_dat}};
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end
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end
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end
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else begin : wb128w
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always @( posedge i_clk )
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if ( !i_cmd_full )
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begin
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wr_en_r <= write_request;
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o_wr_mask <= ~wb_sel;
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o_wr_data <= wb_dat;
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end
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end
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endgenerate
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assign o_wr_en = wr_en_r && !i_cmd_full;
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assign o_wr_en = wr_en_r && !i_cmd_full;
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// ------------------------------------------------------
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// ------------------------------------------------------
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// Read
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// Read
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// ------------------------------------------------------
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// ------------------------------------------------------
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always @( posedge i_clk )
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always @( posedge i_clk )
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begin
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begin
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if ( read_ack )
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if ( read_ack_r )
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read_ready <= 1'd1;
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read_ready <= 1'd1;
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else if ( start_read )
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else if ( read_request )
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read_ready <= 1'd0;
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read_ready <= 1'd0;
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if ( !ddr3_busy )
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if ( !i_cmd_full )
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begin
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begin
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start_write_d1 <= start_write;
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write_request_r <= write_request;
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start_read_d1 <= start_read;
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read_request_r <= read_request;
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wb_adr_d1 <= i_mem_ctrl ? {5'd0, i_wb_adr[24:0]} : i_wb_adr[29:0];
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wb_adr_r <= i_mem_ctrl ? {5'd0, i_wb_adr[24:0]} : i_wb_adr[29:0];
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end
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end
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if ( start_read )
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if ( read_request )
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start_read_hold <= 1'd1;
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read_active_r <= 1'd1;
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else if ( read_ack )
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else if ( read_ack_r )
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start_read_hold <= 1'd0;
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read_active_r <= 1'd0;
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if ( i_rd_empty == 1'd0 && start_read_hold )
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if ( i_rd_empty == 1'd0 && read_active_r )
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begin
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read_ack_r <= 1'd1;
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else
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read_ack_r <= 1'd0;
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end
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generate
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if (WB_DWIDTH == 32) begin :wb32r
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always @( posedge i_clk )
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if ( !i_rd_empty && read_active_r )
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o_wb_dat <= i_wb_adr[3:2] == 2'd0 ? i_rd_data[ 31: 0] :
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o_wb_dat <= i_wb_adr[3:2] == 2'd0 ? i_rd_data[ 31: 0] :
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i_wb_adr[3:2] == 2'd1 ? i_rd_data[ 63:32] :
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i_wb_adr[3:2] == 2'd1 ? i_rd_data[ 63:32] :
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i_wb_adr[3:2] == 2'd2 ? i_rd_data[ 95:64] :
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i_wb_adr[3:2] == 2'd2 ? i_rd_data[ 95:64] :
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i_rd_data[127:96] ;
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i_rd_data[127:96] ;
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read_ack <= 1'd1;
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end
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end
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else
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else begin : wb128r
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read_ack <= 1'd0;
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always @( posedge i_clk )
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if ( !i_rd_empty && read_active_r )
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o_wb_dat <= i_rd_data;
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end
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end
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endgenerate
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assign o_wb_ack = i_wb_stb && ( start_write || read_ack ) && !i_cmd_full;
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assign write_ack = write_request && !write_buf_r;
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assign o_wb_ack = ( i_wb_stb && read_ack_r ) || write_ack;
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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