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// Public License along with this source; if not, download it //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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// //
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//////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////
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// TODO add module to switch endianess of ethmac i/f
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module wishbone_arbiter #(
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parameter WB_DWIDTH = 32,
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parameter WB_SWIDTH = 4
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)(
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module wishbone_arbiter (
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input i_wb_clk, // WISHBONE clock
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input i_wb_clk, // WISHBONE clock
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// WISHBONE master 0 - Amber
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// WISHBONE master 0 - Amber
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input [31:0] i_m0_wb_adr,
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input [31:0] i_m0_wb_adr,
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input [3:0] i_m0_wb_sel,
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input [WB_SWIDTH-1:0] i_m0_wb_sel,
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input i_m0_wb_we,
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input i_m0_wb_we,
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output [31:0] o_m0_wb_dat,
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output [WB_DWIDTH-1:0] o_m0_wb_dat,
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input [31:0] i_m0_wb_dat,
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input [WB_DWIDTH-1:0] i_m0_wb_dat,
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input i_m0_wb_cyc,
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input i_m0_wb_cyc,
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input i_m0_wb_stb,
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input i_m0_wb_stb,
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output o_m0_wb_ack,
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output o_m0_wb_ack,
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output o_m0_wb_err,
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output o_m0_wb_err,
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// WISHBONE master 1 - Ethmac
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// WISHBONE master 1 - Ethmac
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input [31:0] i_m1_wb_adr,
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input [31:0] i_m1_wb_adr,
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input [3:0] i_m1_wb_sel,
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input [WB_SWIDTH-1:0] i_m1_wb_sel,
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input i_m1_wb_we,
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input i_m1_wb_we,
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output [31:0] o_m1_wb_dat,
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output [WB_DWIDTH-1:0] o_m1_wb_dat,
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input [31:0] i_m1_wb_dat,
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input [WB_DWIDTH-1:0] i_m1_wb_dat,
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input i_m1_wb_cyc,
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input i_m1_wb_cyc,
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input i_m1_wb_stb,
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input i_m1_wb_stb,
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output o_m1_wb_ack,
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output o_m1_wb_ack,
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output o_m1_wb_err,
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output o_m1_wb_err,
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// WISHBONE slave 0 - Ethmac
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// WISHBONE slave 0 - Ethmac
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output [31:0] o_s0_wb_adr,
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output [31:0] o_s0_wb_adr,
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output [3:0] o_s0_wb_sel,
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output [WB_SWIDTH-1:0] o_s0_wb_sel,
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output o_s0_wb_we,
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output o_s0_wb_we,
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input [31:0] i_s0_wb_dat,
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input [WB_DWIDTH-1:0] i_s0_wb_dat,
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output [31:0] o_s0_wb_dat,
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output [WB_DWIDTH-1:0] o_s0_wb_dat,
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output o_s0_wb_cyc,
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output o_s0_wb_cyc,
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output o_s0_wb_stb,
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output o_s0_wb_stb,
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input i_s0_wb_ack,
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input i_s0_wb_ack,
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input i_s0_wb_err,
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input i_s0_wb_err,
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// WISHBONE slave 1 - Boot Memory
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// WISHBONE slave 1 - Boot Memory
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output [31:0] o_s1_wb_adr,
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output [31:0] o_s1_wb_adr,
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output [3:0] o_s1_wb_sel,
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output [WB_SWIDTH-1:0] o_s1_wb_sel,
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output o_s1_wb_we,
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output o_s1_wb_we,
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input [31:0] i_s1_wb_dat,
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input [WB_DWIDTH-1:0] i_s1_wb_dat,
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output [31:0] o_s1_wb_dat,
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output [WB_DWIDTH-1:0] o_s1_wb_dat,
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output o_s1_wb_cyc,
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output o_s1_wb_cyc,
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output o_s1_wb_stb,
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output o_s1_wb_stb,
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input i_s1_wb_ack,
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input i_s1_wb_ack,
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input i_s1_wb_err,
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input i_s1_wb_err,
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// WISHBONE slave 2 - Main Memory
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// WISHBONE slave 2 - Main Memory
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output [31:0] o_s2_wb_adr,
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output [31:0] o_s2_wb_adr,
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output [3:0] o_s2_wb_sel,
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output [WB_SWIDTH-1:0] o_s2_wb_sel,
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output o_s2_wb_we,
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output o_s2_wb_we,
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input [31:0] i_s2_wb_dat,
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input [WB_DWIDTH-1:0] i_s2_wb_dat,
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output [31:0] o_s2_wb_dat,
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output [WB_DWIDTH-1:0] o_s2_wb_dat,
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output o_s2_wb_cyc,
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output o_s2_wb_cyc,
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output o_s2_wb_stb,
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output o_s2_wb_stb,
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input i_s2_wb_ack,
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input i_s2_wb_ack,
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input i_s2_wb_err,
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input i_s2_wb_err,
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// WISHBONE slave 3 - UART 0
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// WISHBONE slave 3 - UART 0
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output [31:0] o_s3_wb_adr,
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output [31:0] o_s3_wb_adr,
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output [3:0] o_s3_wb_sel,
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output [WB_SWIDTH-1:0] o_s3_wb_sel,
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output o_s3_wb_we,
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output o_s3_wb_we,
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input [31:0] i_s3_wb_dat,
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input [WB_DWIDTH-1:0] i_s3_wb_dat,
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output [31:0] o_s3_wb_dat,
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output [WB_DWIDTH-1:0] o_s3_wb_dat,
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output o_s3_wb_cyc,
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output o_s3_wb_cyc,
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output o_s3_wb_stb,
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output o_s3_wb_stb,
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input i_s3_wb_ack,
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input i_s3_wb_ack,
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input i_s3_wb_err,
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input i_s3_wb_err,
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// WISHBONE slave 4 - UART 1
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// WISHBONE slave 4 - UART 1
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output [31:0] o_s4_wb_adr,
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output [31:0] o_s4_wb_adr,
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output [3:0] o_s4_wb_sel,
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output [WB_SWIDTH-1:0] o_s4_wb_sel,
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output o_s4_wb_we,
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output o_s4_wb_we,
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input [31:0] i_s4_wb_dat,
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input [WB_DWIDTH-1:0] i_s4_wb_dat,
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output [31:0] o_s4_wb_dat,
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output [WB_DWIDTH-1:0] o_s4_wb_dat,
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output o_s4_wb_cyc,
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output o_s4_wb_cyc,
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output o_s4_wb_stb,
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output o_s4_wb_stb,
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input i_s4_wb_ack,
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input i_s4_wb_ack,
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input i_s4_wb_err,
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input i_s4_wb_err,
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// WISHBONE slave 5 - Test Module
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// WISHBONE slave 5 - Test Module
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output [31:0] o_s5_wb_adr,
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output [31:0] o_s5_wb_adr,
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output [3:0] o_s5_wb_sel,
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output [WB_SWIDTH-1:0] o_s5_wb_sel,
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output o_s5_wb_we,
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output o_s5_wb_we,
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input [31:0] i_s5_wb_dat,
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input [WB_DWIDTH-1:0] i_s5_wb_dat,
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output [31:0] o_s5_wb_dat,
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output [WB_DWIDTH-1:0] o_s5_wb_dat,
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output o_s5_wb_cyc,
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output o_s5_wb_cyc,
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output o_s5_wb_stb,
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output o_s5_wb_stb,
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input i_s5_wb_ack,
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input i_s5_wb_ack,
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input i_s5_wb_err,
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input i_s5_wb_err,
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// WISHBONE slave 6 - Timer Module
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// WISHBONE slave 6 - Timer Module
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output [31:0] o_s6_wb_adr,
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output [31:0] o_s6_wb_adr,
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output [3:0] o_s6_wb_sel,
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output [WB_SWIDTH-1:0] o_s6_wb_sel,
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output o_s6_wb_we,
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output o_s6_wb_we,
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input [31:0] i_s6_wb_dat,
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input [WB_DWIDTH-1:0] i_s6_wb_dat,
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output [31:0] o_s6_wb_dat,
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output [WB_DWIDTH-1:0] o_s6_wb_dat,
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output o_s6_wb_cyc,
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output o_s6_wb_cyc,
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output o_s6_wb_stb,
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output o_s6_wb_stb,
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input i_s6_wb_ack,
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input i_s6_wb_ack,
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input i_s6_wb_err,
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input i_s6_wb_err,
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// WISHBONE slave 7 - Interrupt Controller
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// WISHBONE slave 7 - Interrupt Controller
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output [31:0] o_s7_wb_adr,
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output [31:0] o_s7_wb_adr,
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output [3:0] o_s7_wb_sel,
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output [WB_SWIDTH-1:0] o_s7_wb_sel,
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output o_s7_wb_we,
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output o_s7_wb_we,
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input [31:0] i_s7_wb_dat,
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input [WB_DWIDTH-1:0] i_s7_wb_dat,
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output [31:0] o_s7_wb_dat,
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output [WB_DWIDTH-1:0] o_s7_wb_dat,
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output o_s7_wb_cyc,
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output o_s7_wb_cyc,
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output o_s7_wb_stb,
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output o_s7_wb_stb,
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input i_s7_wb_ack,
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input i_s7_wb_ack,
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input i_s7_wb_err
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input i_s7_wb_err
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);
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);
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`include "memory_configuration.v"
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`include "memory_configuration.v"
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reg m0_wb_cyc_r = 'd0;
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reg m0_wb_hold_r = 'd0;
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reg m1_wb_cyc_r = 'd0;
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reg m1_wb_hold_r = 'd0;
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wire m0_in_cycle;
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// wire m0_in_cycle;
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wire m1_in_cycle;
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// wire m1_in_cycle;
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wire current_master;
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wire current_master;
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reg current_master_r = 'd0;
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reg current_master_r = 'd0;
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wire next_master;
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wire next_master;
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wire select_master;
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wire select_master;
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wire [3:0] current_slave;
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wire [3:0] current_slave;
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wire [31:0] master_adr;
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wire [31:0] master_adr;
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wire [3:0] master_sel;
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wire [WB_SWIDTH-1:0] master_sel;
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wire master_we;
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wire master_we;
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wire [31:0] master_wdat;
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wire [WB_DWIDTH-1:0] master_wdat;
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wire master_cyc;
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wire master_cyc;
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wire master_stb;
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wire master_stb;
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wire [31:0] master_rdat;
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wire [WB_DWIDTH-1:0] master_rdat;
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wire master_ack;
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wire master_ack;
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wire master_err;
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wire master_err;
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// Arbitrate between m0 and m1. Ethmac (m0) always gets priority
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// Arbitrate between m0 and m1. Ethmac (m0) always gets priority
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assign next_master = i_m0_wb_cyc ? 1'd0 : 1'd1;
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assign next_master = i_m0_wb_cyc ? 1'd0 : 1'd1;
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// Use cyc signal for arbitration so block accesses are not split up
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// Use cyc signal for arbitration so block accesses are not split up
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assign m0_in_cycle = m0_wb_cyc_r && i_m0_wb_cyc;
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// assign m0_in_cycle = m0_wb_hold_r && !master_ack;
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assign m1_in_cycle = m1_wb_cyc_r && i_m1_wb_cyc;
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// assign m1_in_cycle = m1_wb_hold_r && !master_ack;
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// only select a new bus master when the current bus master
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// only select a new bus master when the current bus master
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// de-asserts the cyc signal
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// daccess ends
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assign select_master = current_master_r ? !m1_in_cycle : !m0_in_cycle;
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assign select_master = current_master_r ? !m1_wb_hold_r : !m0_wb_hold_r;
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assign current_master = select_master ? next_master : current_master_r;
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assign current_master = select_master ? next_master : current_master_r;
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always @( posedge i_wb_clk )
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always @( posedge i_wb_clk )
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begin
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begin
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current_master_r <= current_master;
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current_master_r <= current_master;
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m0_wb_cyc_r <= i_m0_wb_cyc;
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m0_wb_hold_r <= i_m0_wb_stb && !o_m0_wb_ack;
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m1_wb_cyc_r <= i_m1_wb_cyc;
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m1_wb_hold_r <= i_m1_wb_stb && !o_m1_wb_ack;
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end
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end
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// Arbitrate between slaves
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// Arbitrate between slaves
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assign current_slave = in_ethmac ( master_adr ) ? 4'd0 : // Ethmac
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assign current_slave = in_ethmac ( master_adr ) ? 4'd0 : // Ethmac
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| Line 217... |
Line 223... |
in_ic ( master_adr ) ? 4'd7 : // Interrupt Controller
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in_ic ( master_adr ) ? 4'd7 : // Interrupt Controller
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4'd2 ; // default to main memory
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4'd2 ; // default to main memory
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assign master_adr = current_master ? i_m1_wb_adr : i_m0_wb_adr ;
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assign master_adr = current_master ? i_m1_wb_adr : i_m0_wb_adr ;
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// Switch endianess of ethmac Master
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assign master_sel = current_master ? i_m1_wb_sel : i_m0_wb_sel ;
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assign master_sel = current_master ? i_m1_wb_sel : {i_m0_wb_sel[0], i_m0_wb_sel[1],
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assign master_wdat = current_master ? i_m1_wb_dat : i_m0_wb_dat ;
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i_m0_wb_sel[2], i_m0_wb_sel[3]};
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assign master_wdat = current_master ? i_m1_wb_dat : {i_m0_wb_dat[7:0], i_m0_wb_dat[15:8],
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i_m0_wb_dat[23:16],i_m0_wb_dat[31:24]} ;
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assign master_we = current_master ? i_m1_wb_we : i_m0_wb_we ;
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assign master_we = current_master ? i_m1_wb_we : i_m0_wb_we ;
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assign master_cyc = current_master ? i_m1_wb_cyc : i_m0_wb_cyc ;
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assign master_cyc = current_master ? i_m1_wb_cyc : i_m0_wb_cyc ;
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assign master_stb = current_master ? i_m1_wb_stb : i_m0_wb_stb ;
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assign master_stb = current_master ? i_m1_wb_stb : i_m0_wb_stb ;
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Line 330... |
current_slave == 4'd7 ? i_s7_wb_err :
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current_slave == 4'd7 ? i_s7_wb_err :
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i_s2_wb_err ;
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i_s2_wb_err ;
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// Ethmac Master Outputs
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// Ethmac Master Outputs
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// Switch endianess of ethmac Master
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assign o_m0_wb_dat = master_rdat;
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assign o_m0_wb_dat = {master_rdat[7:0], master_rdat[15:8],
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master_rdat[23:16],master_rdat[31:24]};
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assign o_m0_wb_ack = current_master ? 1'd0 : master_ack ;
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assign o_m0_wb_ack = current_master ? 1'd0 : master_ack ;
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assign o_m0_wb_err = current_master ? 1'd0 : master_err ;
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assign o_m0_wb_err = current_master ? 1'd0 : master_err ;
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// Amber Master Outputs
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// Amber Master Outputs
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assign o_m1_wb_dat = master_rdat;
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assign o_m1_wb_dat = master_rdat;
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