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Line 171... |
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`include "memory_configuration.vh"
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`include "memory_configuration.vh"
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reg m0_wb_hold_r = 'd0;
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reg m0_wb_hold_r = 'd0;
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reg m1_wb_hold_r = 'd0;
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reg m1_wb_hold_r = 'd0;
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// wire m0_in_cycle;
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// wire m1_in_cycle;
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wire current_master;
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wire current_master;
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reg current_master_r = 'd0;
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reg current_master_r = 'd0;
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wire next_master;
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wire next_master;
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wire select_master;
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wire select_master;
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wire [3:0] current_slave;
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wire [3:0] current_slave;
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Line 273... |
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// Test Module Outputs
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// Test Module Outputs
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assign o_s5_wb_adr = master_adr;
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assign o_s5_wb_adr = master_adr;
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assign o_s5_wb_dat = master_wdat;
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assign o_s5_wb_dat = master_wdat;
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assign o_s5_wb_sel = master_sel;
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assign o_s5_wb_sel = master_sel;
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assign o_s5_wb_we = current_slave == 5'd5 ? master_we : 1'd0;
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assign o_s5_wb_we = current_slave == 4'd5 ? master_we : 1'd0;
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assign o_s5_wb_cyc = current_slave == 5'd5 ? master_cyc : 1'd0;
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assign o_s5_wb_cyc = current_slave == 4'd5 ? master_cyc : 1'd0;
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assign o_s5_wb_stb = current_slave == 5'd5 ? master_stb : 1'd0;
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assign o_s5_wb_stb = current_slave == 4'd5 ? master_stb : 1'd0;
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// Timers Outputs
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// Timers Outputs
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assign o_s6_wb_adr = master_adr;
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assign o_s6_wb_adr = master_adr;
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assign o_s6_wb_dat = master_wdat;
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assign o_s6_wb_dat = master_wdat;
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assign o_s6_wb_sel = master_sel;
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assign o_s6_wb_sel = master_sel;
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assign o_s6_wb_we = current_slave == 6'd6 ? master_we : 1'd0;
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assign o_s6_wb_we = current_slave == 4'd6 ? master_we : 1'd0;
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assign o_s6_wb_cyc = current_slave == 6'd6 ? master_cyc : 1'd0;
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assign o_s6_wb_cyc = current_slave == 4'd6 ? master_cyc : 1'd0;
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assign o_s6_wb_stb = current_slave == 6'd6 ? master_stb : 1'd0;
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assign o_s6_wb_stb = current_slave == 4'd6 ? master_stb : 1'd0;
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// Interrupt Controller
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// Interrupt Controller
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assign o_s7_wb_adr = master_adr;
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assign o_s7_wb_adr = master_adr;
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assign o_s7_wb_dat = master_wdat;
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assign o_s7_wb_dat = master_wdat;
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assign o_s7_wb_sel = master_sel;
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assign o_s7_wb_sel = master_sel;
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