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//////////////////////////////////////////////////////////////////
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// //
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// Global testbench defines //
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// //
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// This file is part of the Amber project //
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// http://www.opencores.org/project,amber //
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// //
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// Description //
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// Contains a set of defines for each module so if the module //
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// hierarchy changes, hierarchical references to signals //
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// will still work as long as this file is updated. //
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// //
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// Author(s): //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// //
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//////////////////////////////////////////////////////////////////
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// //
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// Copyright (C) 2010 Authors and OPENCORES.ORG //
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// //
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// This source file may be used and distributed without //
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// restriction provided that this copyright statement is not //
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// removed from the file and that any derivative work contains //
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// the original copyright notice and the associated disclaimer. //
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// //
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// This source file is free software; you can redistribute it //
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// and/or modify it under the terms of the GNU Lesser General //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any //
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// later version. //
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// //
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// This source is distributed in the hope that it will be //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// details. //
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// //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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//////////////////////////////////////////////////////////////////
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// ---------------------------------------------------------------
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// Module hierarchy defines
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// ---------------------------------------------------------------
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`ifndef _GLOBAL_DEFINES
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`define _GLOBAL_DEFINES
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`ifndef AMBER_TIMEOUT
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`define AMBER_TIMEOUT 0
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`endif
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`define U_TB tb
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`define U_SYSTEM `U_TB.u_system
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`define U_AMBER `U_SYSTEM.u_amber
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`define U_FETCH `U_AMBER.u_fetch
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`define U_MMU `U_FETCH.u_mmu
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`define U_CACHE `U_FETCH.u_cache
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`define U_COPRO15 `U_AMBER.u_coprocessor
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`define U_EXECUTE `U_AMBER.u_execute
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`define U_WB `U_AMBER.u_write_back
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`define U_REGISTER_BANK `U_EXECUTE.u_register_bank
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`define U_DECODE `U_AMBER.u_decode
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`define U_DECOMPILE `U_DECODE.u_decompile
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`define U_L2CACHE `U_SYSTEM.u_l2cache
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`define U_TEST_MODULE `U_SYSTEM.u_test_module
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`ifdef AMBER_A25_CORE
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`define U_MEM `U_AMBER.u_mem
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`define U_DCACHE `U_MEM.u_dcache
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`define U_WISHBONE `U_AMBER.u_wishbone
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`define U_BOOT_MEM `U_SYSTEM.boot_mem128.u_boot_mem
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`else
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`define U_WISHBONE `U_FETCH.u_wishbone
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`define U_BOOT_MEM `U_SYSTEM.boot_mem32.u_boot_mem
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`endif
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// ---------------------------------------------------------------
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`define TB_DEBUG_MESSAGE $display("\nDEBUG in %m @ tick %8d ", `U_TB.clk_count );
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`define TB_WARNING_MESSAGE $display("\nWARNING in %m @ tick %8d", `U_TB.clk_count );
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`define TB_ERROR_MESSAGE $display("\nFATAL ERROR in %m @ tick %8d", `U_TB.clk_count ); force `U_TB.testfail = 1'd1;
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`ifdef XILINX_FPGA
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// Full DDR3 memory Model
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`define U_RAM tb.u_ddr3_model_c3.memory
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`else
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// Simplified Main Memory Model
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`define U_RAM tb.u_system.u_main_mem.ram
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`endif
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`endif
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