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*** Steps to create the Spartan-6 DDR3 memory interface for the SP605 development board.
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*** Steps to create the Spartan-6 DDR3 memory interface for the SP605 development board.
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These instructions are based on using Xilinx ISE 11.5
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These instructions are based on using Xilinx ISE 14.5
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Use Coregen/MIG 3.3 to create the controller.
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Run coregen
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Open the project hw/vlog/xs6_ddr3/coregen_sp605.cgp
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Under Project IP, select the Core Name "MIG Virtex-6 and Spartan-6",
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right mouse on it and select Regenerate 9Under Original Project Settings)
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Answer Yes to 'Do you wish to continue?' twice. The core generation process then runs in a few seconds.
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Exit coregen.
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This is the controller configuration, for reference.
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- Component Name: ddr3
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- Component Name: ddr3
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- Bank 3 Memory Type DDR3 SDRAM
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- Bank 3 Memory Type DDR3 SDRAM
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- Frequency: 400MHz
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- Frequency: 400MHz
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- Memory Part: MT41J64M16XX-187E
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- Memory Part: MT41J64M16XX-187E
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- Configuration Selection: One 128-bit bi-directional port
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- Configuration Selection: One 128-bit bi-directional port
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- Memory Address Mapping Selection: Row, Bank, Column
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- Memory Address Mapping Selection: Row, Bank, Column
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Once the controller is generated copy all the Verilog files from the user_design/rtl directory to $AMBER_BASE/hw/vlog/xs6_ddr3.
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Once the controller is generated copy all the Verilog files from the
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hw/vlog/xs6_ddr3/user_design/rtl and hw/vlog/xs6_ddr3/user_design/rtl/mcb_controller
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directories to $AMBER_BASE/hw/vlog/xs6_ddr3. Then make the following modifications
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1. ddr3
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line 167 change
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localparam C3_CLKFBOUT_MULT = 2;
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to
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localparam C3_CLKFBOUT_MULT = 4;
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Then make the following modifications
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1. ddr3.v
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2. infrastructure.v
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Rename this module to mcb_ddr3.v.
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Comment out line 126, (* KEEP = "TRUE" *) wire sys_clk_ibufg;
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Replace the inputs c3_sys_clk_p, c3_sys_clk_n with sys_clk_ibufg.
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Comment out the IBUFG instance u_ibufg_sys_clk on lines 156 to 160.
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Delete the outputs c3_clk0 and c3_rst0.
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Change the CLKIN1 signal on line 202 from sys_clk_ibufg to sys_clk.
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2. memc3_infrastructure.v
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Replace the inputs sys_clk_p, sys_clk_n with sys_clk_ibufg.
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Delete the outputs clk0 and rst0.
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Delete the line with (* KEEP = "TRUE" *) wire sys_clk_ibufg;
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Change the localparam from
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There is already an IBUFGDS on that signal in clocks_resets.v so the
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localparam CLK_PERIOD_NS = C_MEMCLK_PERIOD / 1000.0;
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one in infrastructure.v is not needed.
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to
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localparam CLK_PERIOD_NS = C_MEMCLK_PERIOD / 500.0;
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In order to use Impact on CentOS 6, you need to install a USB driver.
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sudo yum install libusb-devel
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Then download and make the usb driver from http://rmdir.de/~michael/xilinx/
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Once its successfully compiled run setup_pcusb to add the device IDs to the Xilinx installation.
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You also need to install the fxload package
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sudo rpm -i fxload-2008_10_13-3.el6.i686.rpm
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And reboot after installing it.
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Delete the generate statement from lines 124 to 154
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Then power on the SP605 board and connect its USB-JTAG port to your PC.
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Then run impact as follows
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export LD_PRELOAD=/your-path/libusb-driver.so
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impact
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Impact should now be able to auto-detect the FPFA card. Right click on the FPGA and select the bitfile to load into it.
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On the PLL_ADV instantiation,
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Change the parameter CLKFBOUT_MULT from 2 to 4.
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Disconnect the CLKOUT2 output
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Delete the U_BUFG_CLK0 instantiation.
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Delete the rst0_sync_r logic.
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