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[/] [amber/] [trunk/] [sw/] [include/] [amber_registers.h] - Diff between revs 31 and 61

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Rev 31 Rev 61
Line 48... Line 48... 
#define ADR_AMBER_TEST_UART_STATUS     0xf0000014
 
#define ADR_AMBER_TEST_UART_STATUS     0xf0000014
 
#define ADR_AMBER_TEST_UART_TXD        0xf0000018
 
#define ADR_AMBER_TEST_UART_TXD        0xf0000018
 
#define ADR_AMBER_TEST_SIM_CTRL        0xf000001c
 
#define ADR_AMBER_TEST_SIM_CTRL        0xf000001c
 
#define ADR_AMBER_TEST_MEM_CTRL        0xf0000020
 
#define ADR_AMBER_TEST_MEM_CTRL        0xf0000020
 
#define ADR_AMBER_TEST_CYCLES          0xf0000024
 
#define ADR_AMBER_TEST_CYCLES          0xf0000024
 
 
 
#define ADR_AMBER_TEST_LED             0xf0000028
 
 
 
#define ADR_AMBER_TEST_PHY_RST         0xf000002c
 
 
 
 
 
 
 
 
 
/* Allow access to the random register over
 
/* Allow access to the random register over
 
   a 16-word address range to load a series
 
   a 16-word address range to load a series
 
   of random numbers using lmd instruction. */
 
   of random numbers using lmd instruction. */
 
#define ADR_AMBER_TEST_RANDOM_NUM      0xf0000100
 
#define ADR_AMBER_TEST_RANDOM_NUM      0xf0000100
Line 70... Line 73... 
#define ADR_AMBER_TEST_RANDOM_NUM12    0xf0000130
 
#define ADR_AMBER_TEST_RANDOM_NUM12    0xf0000130
 
#define ADR_AMBER_TEST_RANDOM_NUM13    0xf0000134
 
#define ADR_AMBER_TEST_RANDOM_NUM13    0xf0000134
 
#define ADR_AMBER_TEST_RANDOM_NUM14    0xf0000138
 
#define ADR_AMBER_TEST_RANDOM_NUM14    0xf0000138
 
#define ADR_AMBER_TEST_RANDOM_NUM15    0xf000013c
 
#define ADR_AMBER_TEST_RANDOM_NUM15    0xf000013c
 
 
 
 
 
 
 
#define ADR_AMBER_IC_IRQ0_STATUS       0x14000000
 
 
 
#define ADR_AMBER_IC_IRQ0_RAWSTAT      0x14000004
 
#define ADR_AMBER_IC_IRQ0_ENABLESET    0x14000008
 
#define ADR_AMBER_IC_IRQ0_ENABLESET    0x14000008
 
#define ADR_AMBER_IC_IRQ1_ENABLESET    0x14000048
 
#define ADR_AMBER_IC_IRQ0_ENABLECLR    0x1400000c
 
#define ADR_AMBER_IC_INT_SOFTSET_0     0x14000010
 
#define ADR_AMBER_IC_INT_SOFTSET_0     0x14000010
 
#define ADR_AMBER_IC_INT_SOFTCLEAR_0   0x14000014
 
#define ADR_AMBER_IC_INT_SOFTCLEAR_0   0x14000014
 
 
 
#define ADR_AMBER_IC_FIRQ0_STATUS      0x14000020
 
 
 
#define ADR_AMBER_IC_FIRQ0_RAWSTAT     0x14000024
 
 
 
#define ADR_AMBER_IC_FIRQ0_ENABLESET   0x14000028
 
 
 
#define ADR_AMBER_IC_FIRQ0_ENABLECLR   0x1400002c
 
 
 
#define ADR_AMBER_IC_IRQ1_STATUS       0x14000040
 
 
 
#define ADR_AMBER_IC_IRQ1_RAWSTAT      0x14000044
 
 
 
#define ADR_AMBER_IC_IRQ1_ENABLESET    0x14000048
 
 
 
#define ADR_AMBER_IC_IRQ1_ENABLECLR    0x1400004c
 
#define ADR_AMBER_IC_INT_SOFTSET_1     0x14000050
 
#define ADR_AMBER_IC_INT_SOFTSET_1     0x14000050
 
#define ADR_AMBER_IC_INT_SOFTCLEAR_1   0x14000054
 
#define ADR_AMBER_IC_INT_SOFTCLEAR_1   0x14000054
 
 
 
#define ADR_AMBER_IC_FIRQ1_STATUS      0x14000060
 
 
 
#define ADR_AMBER_IC_FIRQ1_RAWSTAT     0x14000064
 
 
 
#define ADR_AMBER_IC_FIRQ1_ENABLESET   0x14000068
 
 
 
#define ADR_AMBER_IC_FIRQ1_ENABLECLR   0x1400006c
 
 
 
#define ADR_AMBER_IC_INT_SOFTSET_2     0x14000090
 
 
 
#define ADR_AMBER_IC_INT_SOFTCLEAR_2   0x14000094
 
 
 
#define ADR_AMBER_IC_INT_SOFTSET_3     0x140000d0
 
 
 
#define ADR_AMBER_IC_INT_SOFTCLEAR_3   0x140000d4
 
 
 
 
 
 
 
 
 
#define ADR_AMBER_CT_TIMER0_LOAD       0x13000000
 
#define ADR_AMBER_CT_TIMER0_LOAD       0x13000000
 
 
 
#define ADR_AMBER_TM_TIMER0_LOAD       0x13000000
 
 
 
#define ADR_AMBER_TM_TIMER0_VALUE      0x13000004
 
 
 
#define ADR_AMBER_TM_TIMER0_CTRL       0x13000008
 
 
 
#define ADR_AMBER_TM_TIMER0_CLR        0x1300000c
 
#define ADR_AMBER_CT_TIMER1_LOAD       0x13000100
 
#define ADR_AMBER_CT_TIMER1_LOAD       0x13000100
 
 
 
#define ADR_AMBER_TM_TIMER1_LOAD       0x13000100
 
 
 
#define ADR_AMBER_TM_TIMER1_VALUE      0x13000104
 
 
 
#define ADR_AMBER_TM_TIMER1_CTRL       0x13000108
 
 
 
#define ADR_AMBER_TM_TIMER1_CLR        0x1300010c
 
#define ADR_AMBER_CT_TIMER2_LOAD       0x13000200
 
#define ADR_AMBER_CT_TIMER2_LOAD       0x13000200
 
 
 
#define ADR_AMBER_TM_TIMER2_LOAD       0x13000200
 
 
 
#define ADR_AMBER_TM_TIMER2_VALUE      0x13000204
 
 
 
#define ADR_AMBER_TM_TIMER2_CTRL       0x13000208
 
 
 
#define ADR_AMBER_TM_TIMER2_CLR        0x1300020c
 
 
 
 
 
#define ADR_AMBER_UART0_DR             0x16000000
 
#define ADR_AMBER_UART0_DR             0x16000000
 
#define ADR_AMBER_UART0_RSR            0x16000004
 
#define ADR_AMBER_UART0_RSR            0x16000004
 
#define ADR_AMBER_UART0_LCRH           0x16000008
 
#define ADR_AMBER_UART0_LCRH           0x16000008
 
#define ADR_AMBER_UART0_LCRM           0x1600000c
 
#define ADR_AMBER_UART0_LCRM           0x1600000c
Line 104... Line 138... 
#define ADR_AMBER_UART1_ICR            0x1700001c
 
#define ADR_AMBER_UART1_ICR            0x1700001c
 
 
 
 
 
#define ADR_AMBER_CORE_CTRL            0x1300031c
 
#define ADR_AMBER_CORE_CTRL            0x1300031c
 
 
 
 
 
#define ADR_ETHMAC_MODER               0x20000000
 
#define ADR_ETHMAC_MODER               0x20000000
 
 
 
#define ADR_ETHMAC_INT_SOURCE          0x20000004
 
 
 
#define ADR_ETHMAC_INT_MASK            0x20000008
 
#define ADR_ETHMAC_MIIMODER            0x20000028
 
#define ADR_ETHMAC_MIIMODER            0x20000028
 
#define ADR_ETHMAC_MIICOMMAND          0x2000002C
 
#define ADR_ETHMAC_MIICOMMAND          0x2000002C
 
#define ADR_ETHMAC_MIIADDRESS          0x20000030
 
#define ADR_ETHMAC_MIIADDRESS          0x20000030
 
#define ADR_ETHMAC_MIITXDATA           0x20000034
 
#define ADR_ETHMAC_MIITXDATA           0x20000034
 
#define ADR_ETHMAC_MIIRXDATA           0x20000038
 
#define ADR_ETHMAC_MIIRXDATA           0x20000038
 
#define ADR_ETHMAC_MIISTATUS           0x2000003C
 
#define ADR_ETHMAC_MIISTATUS           0x2000003C
 
 
 
#define ADR_ETHMAC_MAC_ADDR0           0x20000040
 
 
 
#define ADR_ETHMAC_MAC_ADDR1           0x20000044
 
 
 
 
 
#define ADR_ETHMAC_BDBASE              0x20000400
 
#define ADR_ETHMAC_BDBASE              0x20000400
 
 
 
 
 
#define ADR_HIBOOT_BASE                0x28000000
 
#define ADR_HIBOOT_BASE                0x28000000
 
 
 
 
 
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