Line 10... |
Line 10... |
},
|
},
|
'ports' => {
|
'ports' => {
|
'tag_o' => {
|
'tag_o' => {
|
'outport_type' => 'concatenate',
|
'outport_type' => 'concatenate',
|
'connect_name' => 'tag_i',
|
'connect_name' => 'tag_i',
|
'connect_type' => 'input',
|
|
'range' => 'TAGw-1 : 0',
|
|
'name' => 'tag_o',
|
'name' => 'tag_o',
|
|
'range' => 'TAGw-1:0',
|
|
'connect_type' => 'input',
|
'connect_range' => 'TAGw-1 : 0',
|
'connect_range' => 'TAGw-1 : 0',
|
|
'default_out' => 'Active low',
|
'type' => 'output'
|
'type' => 'output'
|
},
|
},
|
'stb_o' => {
|
'cyc_o' => {
|
'outport_type' => 'concatenate',
|
'outport_type' => 'concatenate',
|
'connect_name' => 'stb_i',
|
'connect_name' => 'cyc_i',
|
'connect_type' => 'input',
|
'name' => 'cyc_o',
|
'range' => '',
|
'range' => '',
|
'name' => 'stb_o',
|
'connect_type' => 'input',
|
'connect_range' => '',
|
'connect_range' => '',
|
|
'default_out' => 'Active low',
|
'type' => 'output'
|
'type' => 'output'
|
},
|
},
|
'cyc_o' => {
|
'stb_o' => {
|
'outport_type' => 'concatenate',
|
'outport_type' => 'concatenate',
|
'connect_name' => 'cyc_i',
|
'connect_name' => 'stb_i',
|
'connect_type' => 'input',
|
'name' => 'stb_o',
|
'range' => '',
|
'range' => '',
|
'name' => 'cyc_o',
|
'connect_type' => 'input',
|
'connect_range' => '',
|
'connect_range' => '',
|
|
'default_out' => 'Active low',
|
'type' => 'output'
|
'type' => 'output'
|
},
|
},
|
'dat_i' => {
|
'dat_i' => {
|
'outport_type' => 'concatenate',
|
'outport_type' => 'concatenate',
|
'connect_name' => 'dat_o',
|
'connect_name' => 'dat_o',
|
'connect_type' => 'output',
|
|
'range' => 'Dw-1 : 0',
|
|
'name' => 'dat_i',
|
'name' => 'dat_i',
|
|
'range' => 'Dw-1:0',
|
|
'connect_type' => 'output',
|
'connect_range' => 'Dw-1 : 0',
|
'connect_range' => 'Dw-1 : 0',
|
|
'default_out' => 'Active low',
|
'type' => 'input'
|
'type' => 'input'
|
},
|
},
|
|
'bte_o' => {
|
|
'outport_type' => 'concatenate',
|
|
'connect_name' => 'bte_i',
|
|
'name' => 'bte_o',
|
|
'range' => 'BTEw-1:0',
|
|
'connect_type' => 'input',
|
|
'connect_range' => 'BTEw-1:0',
|
|
'default_out' => 'Active low',
|
|
'type' => 'output'
|
|
},
|
|
'dat_o' => {
|
|
'outport_type' => 'concatenate',
|
|
'connect_name' => 'dat_i',
|
|
'name' => 'dat_o',
|
|
'range' => 'Dw-1:0',
|
|
'connect_type' => 'input',
|
|
'connect_range' => 'Dw-1:0',
|
|
'default_out' => 'Active low',
|
|
'type' => 'output'
|
|
},
|
'err_i' => {
|
'err_i' => {
|
'outport_type' => 'concatenate',
|
'outport_type' => 'concatenate',
|
'connect_name' => 'err_o',
|
'connect_name' => 'err_o',
|
'connect_type' => 'output',
|
|
'range' => '',
|
|
'name' => 'err_i',
|
'name' => 'err_i',
|
|
'range' => '',
|
|
'connect_type' => 'output',
|
'connect_range' => '',
|
'connect_range' => '',
|
|
'default_out' => 'Active low',
|
'type' => 'input'
|
'type' => 'input'
|
},
|
},
|
'dat_o' => {
|
'cti_o' => {
|
'outport_type' => 'concatenate',
|
'outport_type' => 'concatenate',
|
'connect_name' => 'dat_i',
|
'connect_name' => 'cti_i',
|
|
'name' => 'cti_o',
|
|
'range' => 'CTIw-1:0',
|
'connect_type' => 'input',
|
'connect_type' => 'input',
|
'range' => 'Dw-1 : 0',
|
'connect_range' => 'CTIw-1:0',
|
'name' => 'dat_o',
|
'default_out' => 'Active low',
|
'connect_range' => 'Dw-1 : 0',
|
|
'type' => 'output'
|
'type' => 'output'
|
},
|
},
|
'adr_o' => {
|
'adr_o' => {
|
'outport_type' => 'concatenate',
|
'outport_type' => 'concatenate',
|
'connect_name' => 'adr_i',
|
'connect_name' => 'adr_i',
|
'connect_type' => 'input',
|
|
'range' => 'Aw-1 : 0',
|
|
'name' => 'adr_o',
|
'name' => 'adr_o',
|
|
'range' => 'Aw-1:0',
|
|
'connect_type' => 'input',
|
'connect_range' => 'Aw-1 : 0',
|
'connect_range' => 'Aw-1 : 0',
|
|
'default_out' => 'Active low',
|
'type' => 'output'
|
'type' => 'output'
|
},
|
},
|
'we_o' => {
|
'rty_i' => {
|
'outport_type' => 'concatenate',
|
'outport_type' => 'concatenate',
|
'connect_name' => 'we_i',
|
'connect_name' => 'rty_o',
|
'connect_type' => 'input',
|
'name' => 'rty_i',
|
'range' => '',
|
'range' => '',
|
'name' => 'we_o',
|
'connect_type' => 'output',
|
'connect_range' => '',
|
'connect_range' => '',
|
'type' => 'output'
|
'default_out' => 'Active low',
|
|
'type' => 'input'
|
},
|
},
|
'rty_i' => {
|
'we_o' => {
|
'outport_type' => 'concatenate',
|
'outport_type' => 'concatenate',
|
'connect_name' => 'rty_o',
|
'connect_name' => 'we_i',
|
'connect_type' => 'output',
|
'name' => 'we_o',
|
'range' => '',
|
'range' => '',
|
'name' => 'rty_i',
|
'connect_type' => 'input',
|
'connect_range' => '',
|
'connect_range' => '',
|
'type' => 'input'
|
'default_out' => 'Active low',
|
|
'type' => 'output'
|
},
|
},
|
'sel_o' => {
|
'sel_o' => {
|
'outport_type' => 'concatenate',
|
'outport_type' => 'concatenate',
|
'connect_name' => 'sel_i',
|
'connect_name' => 'sel_i',
|
'connect_type' => 'input',
|
|
'range' => 'SELw-1 : 0',
|
|
'name' => 'sel_o',
|
'name' => 'sel_o',
|
|
'range' => 'SELw-1:0',
|
|
'connect_type' => 'input',
|
'connect_range' => 'SELw-1 : 0',
|
'connect_range' => 'SELw-1 : 0',
|
|
'default_out' => 'Active low',
|
'type' => 'output'
|
'type' => 'output'
|
},
|
},
|
'ack_i' => {
|
'ack_i' => {
|
'outport_type' => 'concatenate',
|
'outport_type' => 'concatenate',
|
'connect_name' => 'ack_o',
|
'connect_name' => 'ack_o',
|
'connect_type' => 'output',
|
|
'range' => '',
|
|
'name' => 'ack_i',
|
'name' => 'ack_i',
|
|
'range' => '',
|
|
'connect_type' => 'output',
|
'connect_range' => '',
|
'connect_range' => '',
|
|
'default_out' => 'Active low',
|
'type' => 'input'
|
'type' => 'input'
|
}
|
}
|
},
|
},
|
'file_name' => '/home/alireza/Mywork/develop/gui/main/lib/verilog/bus.v',
|
'file_name' => '/home/alireza/Mywork/mpsoc/perl_gui/lib/verilog/bus.v',
|
'module_name' => 'wb_slave_socket',
|
'module_name' => 'wb_slave_socket',
|
'type' => 'socket',
|
'type' => 'socket',
|
'category' => 'wishbone'
|
'category' => 'wishbone'
|
}, 'intfc_gen' );
|
}, 'intfc_gen' );
|