OpenCores
URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [perl_gui/] [lib/] [perl/] [soc_gen.pl] - Diff between revs 25 and 28

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 25 Rev 28
Line 6... Line 6...
use ip;
use ip;
use interface;
use interface;
use POSIX 'strtol';
use POSIX 'strtol';
 
 
use File::Path;
use File::Path;
use File::Find;
#use File::Find;
use File::Copy;
use File::Copy;
use File::Copy::Recursive qw(dircopy);
use File::Copy::Recursive qw(dircopy);
use Cwd 'abs_path';
use Cwd 'abs_path';
 
 
 
 
Line 164... Line 164...
                  $value=~ s/\D//g;
                  $value=~ s/\D//g;
                  $min=~ s/\D//g;
                  $min=~ s/\D//g;
                  $max=~ s/\D//g;
                  $max=~ s/\D//g;
                  $step=~ s/\D//g;
                  $step=~ s/\D//g;
                  my $spin=gen_spin($min,$max,$step);
                  my $spin=gen_spin($min,$max,$step);
                  $spin->set_value($value);
                  if(defined $value) {$spin->set_value($value);}
 
                  else {$spin->set_value($min);}
                  $table->attach ($spin, 3, 4, $row, $row+1,'expand','shrink',2,2);
                  $table->attach ($spin, 3, 4, $row, $row+1,'expand','shrink',2,2);
                  $spin-> signal_connect("value_changed" => sub{ $new_param_value{$p}=$spin->get_value_as_int(); });
                  $spin-> signal_connect("value_changed" => sub{ $new_param_value{$p}=$spin->get_value_as_int(); });
 
 
                 # $box=def_label_spin_help_box ($param,$info, $value,$min,$max,$step, 2);
                 # $box=def_label_spin_help_box ($param,$info, $value,$min,$max,$step, 2);
                }
                }
Line 851... Line 852...
################
################
#       generate_soc
#       generate_soc
#################
#################
 
 
sub generate_soc{
sub generate_soc{
        my ($soc,$info)=@_;
        my ($soc,$info,$target_dir,$hw_path,$sw_path,$gen_top,$gen_hw_lib)=@_;
        my $name=$soc->object_get_attribute('soc_name');
        my $name=$soc->object_get_attribute('soc_name');
                if (length($name)>0){
 
                        my @tmp=split('_',$name);
 
                        if ( $tmp[-1] =~ /^[0-9]+$/ ){
 
                                message_dialog("The soc name must not end with '_number'!");
 
                                return 0;
 
                        }
 
 
 
                        my ($file_v,$top_v,$readme)=soc_generate_verilog($soc);
 
 
                my ($file_v,$top_v,$readme,$prog)=soc_generate_verilog($soc);
 
 
                        # Write object file
                        # Write object file
                        open(FILE,  ">lib/soc/$name.SOC") || die "Can not open: $!";
                        open(FILE,  ">lib/soc/$name.SOC") || die "Can not open: $!";
                        print FILE perl_file_header("$name.SOC");
                        print FILE perl_file_header("$name.SOC");
                        print FILE Data::Dumper->Dump([\%$soc],[$name]);
                print FILE Data::Dumper->Dump([\%$soc],['soc']);
                        close(FILE) || die "Error closing file: $!";
                        close(FILE) || die "Error closing file: $!";
 
 
                        # Write verilog file
                        # Write verilog file
                        open(FILE,  ">lib/verilog/$name.v") || die "Can not open: $!";
                        open(FILE,  ">lib/verilog/$name.v") || die "Can not open: $!";
                        print FILE $file_v;
                        print FILE $file_v;
                        close(FILE) || die "Error closing file: $!";
                        close(FILE) || die "Error closing file: $!";
 
 
                        # Write Top module file
                        # Write Top module file
 
                if($gen_top){
                        my $l=autogen_warning().get_license_header("${name}_top.v");
                        my $l=autogen_warning().get_license_header("${name}_top.v");
                        open(FILE,  ">lib/verilog/${name}_top.v") || die "Can not open: $!";
                        open(FILE,  ">lib/verilog/${name}_top.v") || die "Can not open: $!";
                        print FILE "$l\n$top_v";
                        print FILE "$l\n$top_v";
                        close(FILE) || die "Error closing file: $!";
                        close(FILE) || die "Error closing file: $!";
 
                }
 
 
                        # Write readme file
                        # Write readme file
                        open(FILE,  ">lib/verilog/README") || die "Can not open: $!";
                        open(FILE,  ">lib/verilog/README") || die "Can not open: $!";
                        print FILE $readme;
                        print FILE $readme;
                        close(FILE) || die "Error closing file: $!";
                        close(FILE) || die "Error closing file: $!";
 
 
                        # copy all files in project work directory
 
 
                # Write memory prog file
 
                open(FILE,  ">lib/verilog/write_memory.sh") || die "Can not open: $!";
 
                print FILE $prog;
 
                close(FILE) || die "Error closing file: $!";
 
 
                        my $dir = Cwd::getcwd();
                        my $dir = Cwd::getcwd();
                        #make target dir
 
                        my $project_dir   = abs_path("$dir/../../");
                        my $project_dir   = abs_path("$dir/../../");
                        my $target_dir  = "$project_dir/mpsoc_work/SOC/$name";
                if($gen_hw_lib){
                        mkpath("$target_dir/src_verilog/lib/",1,01777);
 
                        mkpath("$target_dir/sw",1,01777);
                        #make target dir
 
                        my $hw_lib="$hw_path/lib";
 
                        mkpath("$hw_lib/",1,01777);
 
                        mkpath("$sw_path/",1,01777);
 
 
                #copy hdl codes in src_verilog
                #copy hdl codes in src_verilog
 
 
                my ($file_ref,$warnings)= get_all_files_list($soc,"hdl_files");
                my ($file_ref,$warnings)= get_all_files_list($soc,"hdl_files");
 
 
                    copy_file_and_folders($file_ref,$project_dir,"$target_dir/src_verilog/lib");
                        copy_file_and_folders($file_ref,$project_dir,$hw_lib);
 
 
                        show_info(\$info,$warnings)                     if(defined $warnings);
                        show_info(\$info,$warnings)                     if(defined $warnings);
 
 
 
 
                #copy jtag control files 
                #copy jtag control files 
                my @jtags=(("/mpsoc/src_peripheral/jtag/jtag_wb"),("jtag"));
                my @jtags=(("/mpsoc/src_peripheral/jtag/jtag_wb"),("jtag"));
                copy_file_and_folders(\@jtags,$project_dir,"$target_dir/src_verilog/lib");
                        copy_file_and_folders(\@jtags,$project_dir,$hw_lib);
 
                        move ("$dir/lib/verilog/$name.v","$hw_path/");
                #my @pathes=("$dir/../src_peripheral","$dir/../src_noc","$dir/../src_processor");
                        move ("$dir/lib/verilog/${name}_top.v","$hw_path/");
                #foreach my $p(@pathes){
                        move ("$dir/lib/verilog/README" ,"$sw_path/");
                #       find(
                        move ("$dir/lib/verilog/write_memory.sh" ,"$sw_path/");
                #               sub {
                }
                #                       return unless ( -f $_ );
 
                #                       $_ =~ /\.v$/ && copy( $File::Find::name, "$target_dir/src_verilog/lib/" );
 
                #               },
 
                #       $p
 
                        #       );
 
                #}
 
 
 
 
 
                move ("$dir/lib/verilog/$name.v","$target_dir/src_verilog/");
 
                move ("$dir/lib/verilog/${name}_top.v","$target_dir/src_verilog/");
 
                move ("$dir/lib/verilog/README" ,"$target_dir/sw/");
 
                # Copy Software files
                # Copy Software files
                        ($file_ref,$warnings)= get_all_files_list($soc,"sw_files");
                my ($file_ref,$warnings)= get_all_files_list($soc,"sw_files");
                        copy_file_and_folders($file_ref,$project_dir,"$target_dir/sw");
                copy_file_and_folders($file_ref,$project_dir,$sw_path);
 
 
                # Write system.h and Software gen files
                # Write system.h and Software gen files
                        generate_header_file($soc,$project_dir,$target_dir,$dir);
                generate_header_file($soc,$project_dir,$sw_path,$dir);
 
 
 
 
 
 
 
 
 
 
                # Write main.c file if not exist
                # Write main.c file if not exist
                my $n="$target_dir/sw/main.c";
                my $n="$sw_path/main.c";
                if (!(-f "$n")) {
                if (!(-f "$n")) {
                        # Write main.c
                        # Write main.c
                        open(FILE,  ">$n") || die "Can not open: $!";
                        open(FILE,  ">$n") || die "Can not open: $!";
                        print FILE main_c_template($name);
                        print FILE main_c_template($name);
                        close(FILE) || die "Error closing file: $!";
                        close(FILE) || die "Error closing file: $!";
Line 945... Line 938...
                }
                }
 
 
 
 
 
 
 
 
                        message_dialog("SoC \"$name\" has been created successfully at $target_dir/ " );
 
                        exec($^X, $0, @ARGV);# reset ProNoC to apply changes
 
 
 
                }else {
 
                        message_dialog("Please define the SoC name!");
 
 
 
                }
 
 
 
return 1;
 
}
}
 
 
 
 
sub main_c_template{
sub main_c_template{
        my $hdr=shift;
        my $hdr=shift;
Line 1417... Line 1403...
        my $infc = interface->interface_new();
        my $infc = interface->interface_new();
        my $ip = ip->lib_new ();
        my $ip = ip->lib_new ();
        my $soc = soc->soc_new();
        my $soc = soc->soc_new();
        set_gui_status($soc,"ideal",0);
        set_gui_status($soc,"ideal",0);
        #my $soc= eval { do 'lib/soc/soc.SOC' };
        #my $soc= eval { do 'lib/soc/soc.SOC' };
 
        #message_dialog("$ENV{'PRONOC_WORK'}\n");
 
 
        # main window
        # main window
        #my $window = def_win_size(1000,800,"Top");
        #my $window = def_win_size(1000,800,"Top");
        #  The main table containg the lib tree, selected modules and info section 
        #  The main table containg the lib tree, selected modules and info section 
        my $main_table = Gtk2::Table->new (20, 12, FALSE);
        my $main_table = Gtk2::Table->new (20, 12, FALSE);
Line 1469... Line 1455...
        $main_table->attach_defaults ($entrybox,3, 7, 19,20);
        $main_table->attach_defaults ($entrybox,3, 7, 19,20);
        $main_table->attach ($wb, 7, 10, 19,20,'expand','shrink',2,2);
        $main_table->attach ($wb, 7, 10, 19,20,'expand','shrink',2,2);
        $main_table->attach ($generate, 10, 12, 19,20,'expand','shrink',2,2);
        $main_table->attach ($generate, 10, 12, 19,20,'expand','shrink',2,2);
 
 
 
 
        #check soc status every 0.5 second. referesh device table if there is any changes 
 
        Glib::Timeout->add (100, sub{
 
                my ($state,$timeout)= get_gui_status($soc);
 
 
 
                if ($timeout>0){
 
                        $timeout--;
 
                        set_gui_status($soc,$state,$timeout);
 
 
 
 
 
 
        $generate-> signal_connect("clicked" => sub{
 
                my $name=$soc->object_get_attribute('soc_name');
 
 
 
                if (length($name)==0){
 
                        message_dialog("Please define the SoC name!");
 
                        return ;
                }
                }
                elsif( $state ne "ideal" ){
 
                        $refresh_dev_win->clicked;
 
                        my $saved_name=$soc->object_get_attribute('soc_name',undef);
 
                        if(defined $saved_name) {$entry->set_text($saved_name);}
 
                        set_gui_status($soc,"ideal",0);
 
                }
 
                return TRUE;
 
 
 
        } );
 
 
 
 
                my @tmp=split('_',$name);
 
                if ( $tmp[-1] =~ /^[0-9]+$/ ){
 
                        message_dialog("The soc name must not end with '_number'!");
 
                        return ;
 
                }
 
                if ( $name =~ /\W+/ ){
 
                        message_dialog('The soc name must not contain any non-word character:("./\()\':,.;<>~!@#$%^&*|+=[]{}`~?-")!")');
 
                        return ;
 
                }
 
 
        $generate-> signal_connect("clicked" => sub{
                my $target_dir  = "$ENV{'PRONOC_WORK'}/SOC/$name";
                generate_soc($soc,$info);
                my $hw_dir      = "$target_dir/src_verilog";
                $refresh_dev_win->clicked;
                my $sw_path     = "$target_dir/sw";
 
 
 
                $soc->object_add_attribute('global_param','CORE_ID',0);
 
                generate_soc($soc,$info,$target_dir,$hw_dir,$sw_path,1,1);
 
                message_dialog("SoC \"$name\" has been created successfully at $target_dir/ " );
 
                exec($^X, $0, @ARGV);# reset ProNoC to apply changes    
 
 
        });
        });
 
 
        $wb-> signal_connect("clicked" => sub{
        $wb-> signal_connect("clicked" => sub{
                wb_address_setting($soc);
                wb_address_setting($soc);
Line 1509... Line 1502...
 
 
        my $sc_win = new Gtk2::ScrolledWindow (undef, undef);
        my $sc_win = new Gtk2::ScrolledWindow (undef, undef);
                $sc_win->set_policy( "automatic", "automatic" );
                $sc_win->set_policy( "automatic", "automatic" );
                $sc_win->add_with_viewport($main_table);
                $sc_win->add_with_viewport($main_table);
 
 
 
 
 
 
 
        #check soc status every 0.5 second. referesh device table if there is any changes 
 
        Glib::Timeout->add (100, sub{
 
                my ($state,$timeout)= get_gui_status($soc);
 
 
 
                if ($timeout>0){
 
                        $timeout--;
 
                        set_gui_status($soc,$state,$timeout);
 
 
 
                }
 
                elsif( $state ne "ideal" ){
 
                        $refresh_dev_win->clicked;
 
                        my $saved_name=$soc->object_get_attribute('soc_name',undef);
 
                        if(defined $saved_name) {$entry->set_text($saved_name);}
 
                        set_gui_status($soc,"ideal",0);
 
                }
 
                return TRUE;
 
 
 
        } );
 
 
 
 
 
 
        return $sc_win;
        return $sc_win;
        #return $main_table;
        #return $main_table;
 
 
 
 
}
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.