URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [perl_gui/] [lib/] [perl/] [verilog_gen.pl] - Diff between revs 43 and 45

Rev 43	Rev 45
Line 784...	Line 784...
`}#foreach my $num`	`}#foreach my $num`
`}#foreach my $plug`	`}#foreach my $plug`
`}#foreach my $instance_id`	`}#foreach my $instance_id`

`#Generate memory programming command`	`#Generate memory programming command`
`my $prog='#!/bin/sh`	`my $prog='#!/bin/bash`

`#JTAG_INTFC="$PRONOC_WORK/toolchain/bin/JTAG_INTFC"`	`#JTAG_INTFC="$PRONOC_WORK/toolchain/bin/JTAG_INTFC"`
`source ./jtag_intfc.sh`	`source ./jtag_intfc.sh`

`';`	`';`
Line 870...	Line 870...
`** Program the memories`	`** Program the memories`
`***********************`	`***********************`

`If the memory core and jtag_wb are connected to the same wishbone bus, you can program the memory using`	`If the memory core and jtag_wb are connected to the same wishbone bus, you can program the memory using`

`sh program.sh`	`bash program.sh`



`***************************`	`***************************`
`** soc parameters`	`** soc parameters`