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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [perl_gui/] [lib/] [verilog/] [bus.v] - Diff between revs 16 and 17

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Rev 16	Rev 17
Line 35...	Line 35...


`parameter Dw = 32, // maximum data width`	`parameter Dw = 32, // maximum data width`
`parameter Aw = 32, // address width`	`parameter Aw = 32, // address width`
`parameter SELw = 2,`	`parameter SELw = 2,`
`parameter TAGw = 3 //merged {tga,tgb,tgc}`	`parameter TAGw = 3 , //merged {tga,tgb,tgc}`
	`parameter CTIw = 3,`
	`parameter BTEw = 2`


`)`	`)`
`(`	`(`

Line 56...	Line 58...
`input [Dw-1 : 0] dat_i,`	`input [Dw-1 : 0] dat_i,`
`input [SELw-1 : 0] sel_i,`	`input [SELw-1 : 0] sel_i,`
`input [TAGw-1 : 0] tag_i,`	`input [TAGw-1 : 0] tag_i,`
`input we_i,`	`input we_i,`
`input stb_i,`	`input stb_i,`
`input cyc_i`	`input cyc_i,`
	`input [CTIw-1 : 0] cti_i,`
	`input [BTEw-1 : 0] bte_i`

`//address compar`	`//address compar`
`//m_grant_addr,`	`//m_grant_addr,`
`//s_sel_one_hot,`	`//s_sel_one_hot,`

Line 84...	Line 88...


`parameter Dw = 32, // maximum data width`	`parameter Dw = 32, // maximum data width`
`parameter Aw = 32, // address width`	`parameter Aw = 32, // address width`
`parameter SELw = 2,`	`parameter SELw = 2,`
`parameter TAGw = 3 //merged {tga,tgb,tgc}`	`parameter TAGw = 3, //merged {tga,tgb,tgc}`
	`parameter CTIw = 3,`
	`parameter BTEw = 2`


`)`	`)`
`(`	`(`

Line 99...	Line 105...
`output [SELw-1 : 0] sel_o,`	`output [SELw-1 : 0] sel_o,`
`output [TAGw-1 : 0] tag_o,`	`output [TAGw-1 : 0] tag_o,`
`output we_o,`	`output we_o,`
`output cyc_o,`	`output cyc_o,`
`output stb_o,`	`output stb_o,`
	`output [CTIw-1 : 0] cti_o,`
	`output [BTEw-1 : 0] bte_o,`


`input [DwS-1 : 0] dat_i,`	`input [DwS-1 : 0] dat_i,`
`input ack_i,`	`input ack_i,`
`input err_i,`	`input err_i,`

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [perl_gui/] [lib/] [verilog/] [bus.v] - Diff between revs 16 and 17