| Line 1... |
Line 1... |
`timescale 1ns/1ps
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`include "pronoc_def.v"
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//`define MONITORE_PATH
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//`define MONITORE_PATH
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/**********************************************************************
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/**********************************************************************
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** File: input_ports.sv
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** File: input_ports.sv
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**
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**
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| Line 26... |
Line 26... |
** NoC router input Port. It consists of input buffer, control FIFO
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** NoC router input Port. It consists of input buffer, control FIFO
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** and request masking/generation control modules
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** and request masking/generation control modules
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**
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**
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**************************************************************/
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**************************************************************/
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module input_ports
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module input_ports
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import pronoc_pkg::*;
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import pronoc_pkg::*;
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#(
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#(
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parameter P=5
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parameter P=5
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)(
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)(
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| Line 40... |
Line 43... |
flit_in_all,
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flit_in_all,
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flit_in_wr_all,
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flit_in_wr_all,
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reset_ivc_all,
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reset_ivc_all,
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flit_is_tail_all,
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flit_is_tail_all,
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ivc_request_all,
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ivc_request_all,
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dest_port_encoded_all,
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dest_port_all,
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dest_port_all,
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candidate_ovcs_all,
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flit_out_all,
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flit_out_all,
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assigned_ovc_num_all,
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assigned_ovc_not_full_all,
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assigned_ovc_not_full_all,
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ovc_is_assigned_all,
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ovc_is_assigned_all,
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sel,
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sel,
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port_pre_sel,
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port_pre_sel,
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swap_port_presel,
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swap_port_presel,
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nonspec_first_arbiter_granted_ivc_all,
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nonspec_first_arbiter_granted_ivc_all,
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credit_out_all,
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destport_clear_all,
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destport_clear,
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vc_weight_is_consumed_all,
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vc_weight_is_consumed_all,
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iport_weight_is_consumed_all,
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iport_weight_is_consumed_all,
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iport_weight_all,
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iport_weight_all,
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oports_weight_all,
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oports_weight_all,
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granted_dest_port_all,
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granted_dest_port_all,
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| Line 97... |
Line 99... |
input [PFw-1 : 0] flit_in_all;
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input [PFw-1 : 0] flit_in_all;
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input [P-1 : 0] flit_in_wr_all;
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input [P-1 : 0] flit_in_wr_all;
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output [PV-1 : 0] reset_ivc_all;
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output [PV-1 : 0] reset_ivc_all;
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output [PV-1 : 0] flit_is_tail_all;
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output [PV-1 : 0] flit_is_tail_all;
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output [PV-1 : 0] ivc_request_all;
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output [PV-1 : 0] ivc_request_all;
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output [PVDSTPw-1 : 0] dest_port_encoded_all;
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output [PV-1 : 0] credit_out_all;
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output [PVP_1-1 : 0] dest_port_all;
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output [PVP_1-1 : 0] dest_port_all;
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output [PVV-1 : 0] candidate_ovcs_all;
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output [PFw-1 : 0] flit_out_all;
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output [PFw-1 : 0] flit_out_all;
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output [PVV-1 : 0] assigned_ovc_num_all;
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input [PV-1 : 0] assigned_ovc_not_full_all;
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input [PV-1 : 0] assigned_ovc_not_full_all;
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output [PV-1 : 0] ovc_is_assigned_all;
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output [PV-1 : 0] ovc_is_assigned_all;
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input [PV-1 : 0] sel;
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input [PV-1 : 0] sel;
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input [PPSw-1 : 0] port_pre_sel;
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input [PPSw-1 : 0] port_pre_sel;
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input [PV-1 : 0] swap_port_presel;
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input [PV-1 : 0] swap_port_presel;
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input [PV-1 : 0] nonspec_first_arbiter_granted_ivc_all;
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input [PV-1 : 0] nonspec_first_arbiter_granted_ivc_all;
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input [PVDSTPw-1 : 0] destport_clear_all;
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output [WP-1 : 0] iport_weight_all;
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output [WP-1 : 0] iport_weight_all;
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output [PV-1 : 0] vc_weight_is_consumed_all;
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output [PV-1 : 0] vc_weight_is_consumed_all;
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output [P-1 : 0] iport_weight_is_consumed_all;
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output [P-1 : 0] iport_weight_is_consumed_all;
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input [PP_1-1 : 0] granted_dest_port_all;
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input [PP_1-1 : 0] granted_dest_port_all;
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output [WPP-1 : 0] oports_weight_all;
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output [WPP-1 : 0] oports_weight_all;
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output ivc_info_t ivc_info [P-1 : 0][V-1 : 0];
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output ivc_info_t ivc_info [P-1 : 0][V-1 : 0];
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input vsa_ctrl_t vsa_ctrl_in [P-1: 0];
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input vsa_ctrl_t vsa_ctrl_in [P-1: 0];
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input ssa_ctrl_t ssa_ctrl_in [P-1: 0];
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input ssa_ctrl_t ssa_ctrl_in [P-1: 0];
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input smart_ctrl_t smart_ctrl_in [P-1 : 0];
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input smart_ctrl_t smart_ctrl_in [P-1 : 0];
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output [CRDTw-1 : 0 ] credit_init_val_out [P-1 : 0][V-1 : 0];
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output [CRDTw-1 : 0 ] credit_init_val_out [P-1 : 0][V-1 : 0];
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input refresh_w_counter;
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input refresh_w_counter;
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input [DSTPw-1 : 0] destport_clear [P-1 : 0][V-1 : 0];
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genvar i;
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genvar i;
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generate
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generate
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for(i=0;i
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for(i=0;i
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input_queue_per_port
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input_queue_per_port
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// iport_reg_base
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// iport_reg_base
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#(
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#(
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.SW_LOC(i),
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.SW_LOC(i),
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.P(P)
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.P(P)
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)
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)
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the_input_queue_per_port
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the_input_queue_per_port
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(
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(
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.credit_out(credit_out_all [(i+1)*V-1 : i*V]),
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.current_r_addr(current_r_addr),
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.current_r_addr(current_r_addr),
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.neighbors_r_addr(neighbors_r_addr),
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.neighbors_r_addr(neighbors_r_addr),
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.ivc_num_getting_sw_grant(ivc_num_getting_sw_grant [(i+1)*V-1 : i*V]),// for non spec ivc_num_getting_first_sw_grant,
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.ivc_num_getting_sw_grant(ivc_num_getting_sw_grant [(i+1)*V-1 : i*V]),// for non spec ivc_num_getting_first_sw_grant,
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.any_ivc_sw_request_granted(any_ivc_sw_request_granted_all [i]),
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.any_ivc_sw_request_granted(any_ivc_sw_request_granted_all [i]),
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.flit_in(flit_in_all[(i+1)*Fw-1 : i*Fw]),
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.flit_in(flit_in_all[(i+1)*Fw-1 : i*Fw]),
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.flit_in_wr(flit_in_wr_all[i]),
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.flit_in_wr(flit_in_wr_all[i]),
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.reset_ivc(reset_ivc_all [(i+1)*V-1 : i*V]),
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.reset_ivc(reset_ivc_all [(i+1)*V-1 : i*V]),
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.flit_is_tail(flit_is_tail_all [(i+1)*V-1 : i*V]),
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.flit_is_tail(flit_is_tail_all [(i+1)*V-1 : i*V]),
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.ivc_request(ivc_request_all [(i+1)*V-1 : i*V]),
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.ivc_request(ivc_request_all [(i+1)*V-1 : i*V]),
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.dest_port_encoded(dest_port_encoded_all [(i+1)*DSTPw*V-1 : i*DSTPw*V]),
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.dest_port(dest_port_all [(i+1)*P_1*V-1 : i*P_1*V]),
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.dest_port(dest_port_all [(i+1)*P_1*V-1 : i*P_1*V]),
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.candidate_ovcs(candidate_ovcs_all [(i+1) * VV -1 : i*VV]),
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.flit_out(flit_out_all [(i+1)*Fw-1 : i*Fw]),
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.flit_out(flit_out_all [(i+1)*Fw-1 : i*Fw]),
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.assigned_ovc_num(assigned_ovc_num_all [(i+1)*VV-1 : i*VV]),
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.assigned_ovc_not_full(assigned_ovc_not_full_all [(i+1)*V-1 : i*V]),
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.assigned_ovc_not_full(assigned_ovc_not_full_all [(i+1)*V-1 : i*V]),
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.ovc_is_assigned(ovc_is_assigned_all [(i+1)*V-1 : i*V]),
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.ovc_is_assigned(ovc_is_assigned_all [(i+1)*V-1 : i*V]),
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.sel(sel [(i+1)*V-1 : i*V]),
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.sel(sel [(i+1)*V-1 : i*V]),
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.port_pre_sel(port_pre_sel),
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.port_pre_sel(port_pre_sel),
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.swap_port_presel(swap_port_presel[(i+1)*V-1 : i*V]),
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.swap_port_presel(swap_port_presel[(i+1)*V-1 : i*V]),
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.nonspec_first_arbiter_granted_ivc(nonspec_first_arbiter_granted_ivc_all[(i+1)*V-1 : i*V]),
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.nonspec_first_arbiter_granted_ivc(nonspec_first_arbiter_granted_ivc_all[(i+1)*V-1 : i*V]),
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.reset(reset),
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.reset(reset),
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.clk(clk),
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.clk(clk),
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.destport_clear(destport_clear_all[(i+1)*DSTPw*V-1 : i*DSTPw*V]),
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.destport_clear(destport_clear [i]),
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.iport_weight(iport_weight_all[(i+1)*W-1 : i*W]),
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.iport_weight(iport_weight_all[(i+1)*W-1 : i*W]),
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.oports_weight(oports_weight_all[(i+1)*WP-1 : i*WP]),
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.oports_weight(oports_weight_all[(i+1)*WP-1 : i*WP]),
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.vc_weight_is_consumed(vc_weight_is_consumed_all [(i+1)*V-1 : i*V]),
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.vc_weight_is_consumed(vc_weight_is_consumed_all [(i+1)*V-1 : i*V]),
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.iport_weight_is_consumed(iport_weight_is_consumed_all[i]),
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.iport_weight_is_consumed(iport_weight_is_consumed_all[i]),
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.refresh_w_counter(refresh_w_counter),
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.refresh_w_counter(refresh_w_counter),
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| Line 193... |
Line 200... |
#(
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#(
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parameter P = 5, // router port num
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parameter P = 5, // router port num
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parameter SW_LOC = 0
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parameter SW_LOC = 0
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)(
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)(
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current_r_addr,
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current_r_addr,
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credit_out,
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neighbors_r_addr,
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neighbors_r_addr,
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ivc_num_getting_sw_grant,// for non spec ivc_num_getting_first_sw_grant,
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ivc_num_getting_sw_grant,// for non spec ivc_num_getting_first_sw_grant,
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any_ivc_sw_request_granted,
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any_ivc_sw_request_granted,
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flit_in,
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flit_in,
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flit_in_wr,
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flit_in_wr,
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reset_ivc,
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reset_ivc,
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flit_is_tail,
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flit_is_tail,
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ivc_request,
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ivc_request,
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dest_port_encoded,
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dest_port,
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dest_port,
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candidate_ovcs,
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flit_out,
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flit_out,
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assigned_ovc_num,
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assigned_ovc_not_full,
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assigned_ovc_not_full,
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ovc_is_assigned,
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ovc_is_assigned,
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sel,
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sel,
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port_pre_sel,
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port_pre_sel,
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swap_port_presel,
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swap_port_presel,
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| Line 230... |
Line 235... |
ssa_ctrl_in,
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ssa_ctrl_in,
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credit_init_val_out
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credit_init_val_out
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);
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);
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function integer log2;
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input integer number; begin
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log2=(number <=1) ? 1: 0;
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while(2**log2
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log2=log2+1;
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end
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end
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endfunction // log2
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localparam PORT_B = port_buffer_size(SW_LOC);
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localparam
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PORT_B = port_buffer_size(SW_LOC),
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PORT_Bw= log2(PORT_B);
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localparam
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localparam
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VV = V * V,
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VV = V * V,
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| Line 270... |
Line 270... |
PRAw= P * RAw;
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PRAw= P * RAw;
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/* verilator lint_on WIDTH */
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/* verilator lint_on WIDTH */
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input reset, clk;
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input reset, clk;
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output [V-1 : 0] credit_out;
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input [RAw-1 : 0] current_r_addr;
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input [RAw-1 : 0] current_r_addr;
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input [PRAw-1: 0] neighbors_r_addr;
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input [PRAw-1: 0] neighbors_r_addr;
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output [V-1 : 0] ivc_num_getting_sw_grant;
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output [V-1 : 0] ivc_num_getting_sw_grant;
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input any_ivc_sw_request_granted;
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input any_ivc_sw_request_granted;
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input [Fw-1 : 0] flit_in;
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input [Fw-1 : 0] flit_in;
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input flit_in_wr;
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input flit_in_wr;
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output [V-1 : 0] reset_ivc;
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output [V-1 : 0] reset_ivc;
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output [V-1 : 0] flit_is_tail;
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output [V-1 : 0] flit_is_tail;
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output [V-1 : 0] ivc_request;
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output [V-1 : 0] ivc_request;
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output [VDSTPw-1 : 0] dest_port_encoded;
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output [VP_1-1 : 0] dest_port;
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output [VP_1-1 : 0] dest_port;
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output [VV-1 : 0] candidate_ovcs;
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output [Fw-1 : 0] flit_out;
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output [Fw-1 : 0] flit_out;
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output [VV-1 : 0] assigned_ovc_num;
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input [V-1 : 0] assigned_ovc_not_full;
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input [V-1 : 0] assigned_ovc_not_full;
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output [V-1 : 0] ovc_is_assigned;
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output [V-1 : 0] ovc_is_assigned;
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input [V-1 : 0] sel;
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input [V-1 : 0] sel;
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input [V-1 : 0] nonspec_first_arbiter_granted_ivc;
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input [V-1 : 0] nonspec_first_arbiter_granted_ivc;
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input [(DSTPw*V)-1 : 0] destport_clear;
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input [DSTPw-1 : 0] destport_clear [V-1 : 0];
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output reg [WEIGHTw-1 : 0] iport_weight;
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output [WEIGHTw-1 : 0] iport_weight;
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output [V-1 : 0] vc_weight_is_consumed;
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output [V-1 : 0] vc_weight_is_consumed;
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output iport_weight_is_consumed;
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output iport_weight_is_consumed;
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input refresh_w_counter;
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input refresh_w_counter;
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input [P_1-1 : 0] granted_dest_port;
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input [P_1-1 : 0] granted_dest_port;
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output [WP-1 : 0] oports_weight;
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output [WP-1 : 0] oports_weight;
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| Line 305... |
Line 303... |
input smart_ctrl_t smart_ctrl_in;
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input smart_ctrl_t smart_ctrl_in;
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input vsa_ctrl_t vsa_ctrl_in;
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input vsa_ctrl_t vsa_ctrl_in;
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input ssa_ctrl_t ssa_ctrl_in;
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input ssa_ctrl_t ssa_ctrl_in;
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output [CRDTw-1 : 0 ] credit_init_val_out [V-1 : 0];
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output [CRDTw-1 : 0 ] credit_init_val_out [V-1 : 0];
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wire [DSTPw-1 : 0] dest_port_encoded [V-1 : 0];
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//for multicast
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wire [DSTPw-1 : 0] dest_port_multi [V-1 : 0];
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wire [V-1 : 0] multiple_dest,dst_onhot0;
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wire [DSTPw-1 : 0] clear_dspt_mulicast [V-1 : 0];
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wire [VV-1 : 0] candidate_ovcs;
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wire [Cw-1 : 0] class_in;
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wire [Cw-1 : 0] class_in;
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wire [DSTPw-1 : 0] destport_in,destport_in_encoded;
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wire [DSTPw-1 : 0] destport_in,destport_in_encoded;
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wire [VDSTPw-1 : 0] lk_destination_encoded;
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wire [VDSTPw-1 : 0] lk_destination_encoded;
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wire [EAw-1 : 0] dest_e_addr_in;
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wire [DAw-1 : 0] dest_e_addr_in;
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wire [EAw-1 : 0] src_e_addr_in;
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wire [EAw-1 : 0] src_e_addr_in;
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wire [V-1 : 0] vc_num_in;
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wire [V-1 : 0] vc_num_in;
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wire [V-1 : 0] hdr_flit_wr,flit_wr;
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wire [V-1 : 0] hdr_flit_wr,flit_wr;
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wire [VV-1 : 0] assigned_ovc_num;
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wire [DSTPw-1 : 0] lk_destination_in_encoded;
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wire [DSTPw-1 : 0] lk_destination_in_encoded;
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wire [WEIGHTw-1 : 0] weight_in;
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wire [WEIGHTw-1 : 0] weight_in;
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wire [Fw-1 : 0] buffer_out;
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wire [Fw-1 : 0] buffer_out;
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wire hdr_flg_in,tail_flg_in;
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wire hdr_flg_in,tail_flg_in;
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| Line 336... |
Line 342... |
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wire odd_column = current_r_addr[0];
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wire odd_column = current_r_addr[0];
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wire [P-1 : 0] destport_one_hot [V-1 :0];
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wire [P-1 : 0] destport_one_hot [V-1 :0];
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wire [V-1 : 0] mux_out[V-1 : 0];
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wire [V-1 : 0] mux_out[V-1 : 0];
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wire [V-1 : 0] dstport_fifo_not_empty;
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logic [WEIGHTw-1 : 0] iport_weight_next;
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|
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assign smart_hdr_en = (SMART_EN) ? smart_ctrl_in.ivc_num_getting_ovc_grant: {V{1'b0}};
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assign smart_hdr_en = (SMART_EN) ? smart_ctrl_in.ivc_num_getting_ovc_grant: {V{1'b0}};
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assign reset_ivc = smart_ctrl_in.ivc_reset | ssa_ctrl_in.ivc_reset | vsa_ctrl_in.ivc_reset;
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assign reset_ivc = smart_ctrl_in.ivc_reset | ssa_ctrl_in.ivc_reset | vsa_ctrl_in.ivc_reset;
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assign ivc_num_getting_sw_grant = ssa_ctrl_in.ivc_num_getting_sw_grant | vsa_ctrl_in.ivc_num_getting_sw_grant;
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assign ivc_num_getting_sw_grant = ssa_ctrl_in.ivc_num_getting_sw_grant | vsa_ctrl_in.ivc_num_getting_sw_grant;
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assign flit_wr =(flit_in_wr )? vc_num_in : {V{1'b0}};
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assign flit_wr =(flit_in_wr )? vc_num_in : {V{1'b0}};
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assign rd_hdr_fwft_fifo = ssa_ctrl_in.ivc_reset | vsa_ctrl_in.ivc_reset | (smart_ctrl_in.ivc_reset & ~ smart_ctrl_in.ivc_single_flit_pck);
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assign rd_hdr_fwft_fifo = (ssa_ctrl_in.ivc_reset | vsa_ctrl_in.ivc_reset | (smart_ctrl_in.ivc_reset & ~ smart_ctrl_in.ivc_single_flit_pck)) & ~ multiple_dest;
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assign wr_hdr_fwft_fifo = hdr_flit_wr | (smart_hdr_en & ~ smart_ctrl_in.ivc_single_flit_pck);
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assign wr_hdr_fwft_fifo = hdr_flit_wr | (smart_hdr_en & ~ smart_ctrl_in.ivc_single_flit_pck);
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assign ivc_request = ivc_not_empty;
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assign ivc_request = ivc_not_empty;
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wire [V-1 : 0] flit_is_tail2;
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register #(.W(V)) reg1(
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|
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pronoc_register #(.W(V)) reg1(
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.in (ovc_is_assigned_next),
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.in (ovc_is_assigned_next),
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.reset (reset ),
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.reset (reset ),
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.clk (clk ),
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.clk (clk ),
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.out (ovc_is_assigned ));
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.out (ovc_is_assigned ));
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|
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register #(.W(VV)) reg2(
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pronoc_register #(.W(VV)) reg2(
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.in (assigned_ovc_num_next),
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.in (assigned_ovc_num_next),
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.reset (reset ),
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.reset (reset ),
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.clk (clk ),
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.clk (clk ),
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.out (assigned_ovc_num ));
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.out (assigned_ovc_num ));
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|
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register #(.W(V)) reg3(
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pronoc_register #(.W(V)) reg3(
|
.in (rd_hdr_fwft_fifo),
|
.in (rd_hdr_fwft_fifo),
|
.reset (reset ),
|
.reset (reset ),
|
.clk (clk ),
|
.clk (clk ),
|
.out (rd_hdr_fwft_fifo_delay ));
|
.out (rd_hdr_fwft_fifo_delay ));
|
|
|
register #(.W(V)) reg4(
|
pronoc_register #(.W(V)) reg4(
|
.in (wr_hdr_fwft_fifo),
|
.in (wr_hdr_fwft_fifo),
|
.reset (reset ),
|
.reset (reset ),
|
.clk (clk ),
|
.clk (clk ),
|
.out (wr_hdr_fwft_fifo_delay ));
|
.out (wr_hdr_fwft_fifo_delay ));
|
|
|
|
pronoc_register #(.W(WEIGHTw), .RESET_TO(1)) reg5(
|
|
.in (iport_weight_next ),
|
|
.reset (reset ),
|
|
.clk (clk ),
|
|
.out (iport_weight ));
|
|
|
`ifdef SYNC_RESET_MODE
|
|
always @ (posedge clk )begin
|
pronoc_register #(.W(V)) credit_reg (
|
`else
|
.in (ivc_num_getting_sw_grant & ~ multiple_dest),
|
always @ (posedge clk or posedge reset)begin
|
.reset (reset),
|
`endif
|
.clk (clk),
|
if(reset) begin
|
.out (credit_out));
|
iport_weight <= 1;
|
|
end else begin
|
|
if(hdr_flit_wr != {V{1'b0}}) iport_weight <= (weight_in=={WEIGHTw{1'b0}})? 1 : weight_in; // the minimum weight is 1
|
|
end
|
|
|
always @ (*)begin
|
|
iport_weight_next = iport_weight;
|
|
if(hdr_flit_wr != {V{1'b0}}) iport_weight_next = (weight_in=={WEIGHTw{1'b0}})? 1 : weight_in; // the minimum weight is 1
|
end
|
end
|
|
|
|
|
//extract header flit info
|
//extract header flit info
|
extract_header_flit_info #(
|
extract_header_flit_info #(
|
| Line 410... |
Line 430... |
|
|
|
|
genvar i;
|
genvar i;
|
generate
|
generate
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1)) begin : multi_local
|
if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1) && CAST_TYPE== "UNICAST") begin : multi_local
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
|
|
|
|
|
|
mesh_tori_endp_addr_decode #(
|
mesh_tori_endp_addr_decode #(
|
| Line 432... |
Line 452... |
.el(endp_l_in),
|
.el(endp_l_in),
|
.valid( )
|
.valid( )
|
);
|
);
|
end
|
end
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
if ( TOPOLOGY == "FMESH") begin : fmesh
|
if ( TOPOLOGY == "FMESH" && CAST_TYPE== "UNICAST" ) begin : fmesh
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
|
|
|
|
|
|
fmesh_endp_addr_decode #(
|
fmesh_endp_addr_decode #(
|
| Line 482... |
Line 502... |
one_hot_to_bin #(.ONE_HOT_WIDTH(V),.BIN_WIDTH(Vw)) conv (
|
one_hot_to_bin #(.ONE_HOT_WIDTH(V),.BIN_WIDTH(Vw)) conv (
|
.one_hot_code(assigned_ovc_num[(i+1)*V-1 : i*V]),
|
.one_hot_code(assigned_ovc_num[(i+1)*V-1 : i*V]),
|
.bin_code(ivc_info[i].assigned_ovc_bin)
|
.bin_code(ivc_info[i].assigned_ovc_bin)
|
);
|
);
|
|
|
|
assign ivc_info[i].single_flit_pck =
|
|
/* verilator lint_off WIDTH */
|
|
(PCK_TYPE == "SINGLE_FLIT")? 1'b1 :
|
|
/* verilator lint_on WIDTH */
|
|
(MIN_PCK_SIZE == 1)? flit_is_tail[i] & ~ovc_is_assigned[i] : 1'b0;
|
assign ivc_info[i].ivc_req = ivc_request[i];
|
assign ivc_info[i].ivc_req = ivc_request[i];
|
assign ivc_info[i].class_num = class_out[i];
|
assign ivc_info[i].class_num = class_out[i];
|
assign ivc_info[i].flit_is_tail = flit_is_tail[i];
|
assign ivc_info[i].flit_is_tail = flit_is_tail[i];
|
assign ivc_info[i].assigned_ovc_not_full=assigned_ovc_not_full[i];
|
assign ivc_info[i].assigned_ovc_not_full=assigned_ovc_not_full[i];
|
assign ivc_info[i].candidate_ovc= candidate_ovcs [(i+1)*V-1 : i*V];
|
assign ivc_info[i].candidate_ovc= candidate_ovcs [(i+1)*V-1 : i*V];
|
assign ivc_info[i].ovc_is_assigned = ovc_is_assigned[i];
|
assign ivc_info[i].ovc_is_assigned = ovc_is_assigned[i];
|
assign ivc_info[i].assigned_ovc_num= assigned_ovc_num[(i+1)*V-1 : i*V];
|
assign ivc_info[i].assigned_ovc_num= assigned_ovc_num[(i+1)*V-1 : i*V];
|
assign ivc_info[i].dest_port_encoded=dest_port_encoded[(i+1)*DSTPw-1 : i*DSTPw];
|
assign ivc_info[i].dest_port_encoded=dest_port_encoded[i];
|
//assign ivc_info[i].getting_swa_first_arbiter_grant=nonspec_first_arbiter_granted_ivc[i];
|
//assign ivc_info[i].getting_swa_first_arbiter_grant=nonspec_first_arbiter_granted_ivc[i];
|
//assign ivc_info[i].getting_swa_grant=ivc_num_getting_sw_grant[i];
|
//assign ivc_info[i].getting_swa_grant=ivc_num_getting_sw_grant[i];
|
if(P==MAX_P) begin :max_
|
if(P==MAX_P) begin :max_
|
assign ivc_info[i].destport_one_hot= destport_one_hot[i];
|
assign ivc_info[i].destport_one_hot= destport_one_hot[i];
|
end else begin : no_max
|
end else begin : no_max
|
| Line 510... |
Line 534... |
$finish;
|
$finish;
|
end
|
end
|
end
|
end
|
//synthesis translate_on
|
//synthesis translate_on
|
|
|
|
|
|
|
|
|
|
|
class_ovc_table #(
|
class_ovc_table #(
|
.CVw(CVw),
|
.CVw(CVw),
|
.CLASS_SETTING(CLASS_SETTING),
|
.CLASS_SETTING(CLASS_SETTING),
|
.C(C),
|
.C(C),
|
.V(V)
|
.V(V)
|
| Line 522... |
Line 550... |
(
|
(
|
.class_in(class_out[i]),
|
.class_in(class_out[i]),
|
.candidate_ovcs(candidate_ovcs [(i+1)*V-1 : i*V])
|
.candidate_ovcs(candidate_ovcs [(i+1)*V-1 : i*V])
|
);
|
);
|
|
|
if(PCK_TYPE == "MULTI_FLIT") begin : multi
|
if(PCK_TYPE == "MULTI_FLIT") begin : multi_flit
|
|
|
always @ (*) begin
|
always @ (*) begin
|
ovc_is_assigned_next[i] = ovc_is_assigned[i];
|
ovc_is_assigned_next[i] = ovc_is_assigned[i];
|
if( vsa_ctrl_in.ivc_reset[i] |
|
if( vsa_ctrl_in.ivc_reset[i] |
|
ssa_ctrl_in.ivc_reset[i] |
|
ssa_ctrl_in.ivc_reset[i] |
|
| Line 557... |
Line 585... |
.sel ({vsa_ctrl_in.ivc_num_getting_ovc_grant[i],ssa_ctrl_in.ivc_num_getting_ovc_grant[i],smart_ctrl_in.ivc_num_getting_ovc_grant[i]} ),
|
.sel ({vsa_ctrl_in.ivc_num_getting_ovc_grant[i],ssa_ctrl_in.ivc_num_getting_ovc_grant[i],smart_ctrl_in.ivc_num_getting_ovc_grant[i]} ),
|
.out (mux_out[i] )
|
.out (mux_out[i] )
|
);
|
);
|
|
|
|
|
|
/*
|
//tail fifo
|
//tail fifo
|
fwft_fifo #(
|
fwft_fifo #(
|
.DATA_WIDTH(1),
|
.DATA_WIDTH(1),
|
.MAX_DEPTH (PORT_B),
|
.MAX_DEPTH (PORT_B),
|
.IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
|
.IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
|
| Line 577... |
Line 605... |
.recieve_more_than_0 ( ),
|
.recieve_more_than_0 ( ),
|
.recieve_more_than_1 ( ),
|
.recieve_more_than_1 ( ),
|
.reset (reset),
|
.reset (reset),
|
.clk (clk)
|
.clk (clk)
|
);
|
);
|
end else begin :single
|
*/
|
assign flit_is_tail[i]=1'b1;
|
|
|
end else begin :single_flit
|
|
//assign flit_is_tail[i]=1'b1;
|
assign ovc_is_assigned_next[i] = 1'b0;
|
assign ovc_is_assigned_next[i] = 1'b0;
|
|
|
always @(*) begin
|
always @(*) begin
|
assigned_ovc_num_next[(i+1)*V-1 : i*V] = assigned_ovc_num[(i+1)*V-1 : i*V] ;
|
assigned_ovc_num_next[(i+1)*V-1 : i*V] = assigned_ovc_num[(i+1)*V-1 : i*V] ;
|
if(vsa_ctrl_in.ivc_num_getting_ovc_grant[i] | ssa_ctrl_in.ivc_num_getting_ovc_grant[i]) begin
|
if(vsa_ctrl_in.ivc_num_getting_ovc_grant[i] | ssa_ctrl_in.ivc_num_getting_ovc_grant[i]) begin
|
| Line 654... |
Line 684... |
);
|
);
|
end else begin :c_num_1
|
end else begin :c_num_1
|
assign class_out[i] = 1'b0;
|
assign class_out[i] = 1'b0;
|
end
|
end
|
|
|
//lk_dst_fifo
|
|
fwft_fifo #(
|
|
.DATA_WIDTH(DSTPw),
|
|
.MAX_DEPTH (MAX_PCK),
|
|
.IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
|
|
)
|
|
lk_dest_fifo
|
|
(
|
|
.din (lk_destination_in_encoded),
|
|
.wr_en (wr_hdr_fwft_fifo_delay [i]), // Write enable
|
|
.rd_en (rd_hdr_fwft_fifo_delay [i]), // Read the next word
|
|
.dout (lk_destination_encoded [(i+1)*DSTPw-1 : i*DSTPw]), // Data out
|
|
.full (),
|
|
.nearly_full (),
|
|
.recieve_more_than_0 (),
|
|
.recieve_more_than_1 (),
|
|
.reset (reset),
|
|
.clk (clk)
|
|
|
|
);
|
//localparam CAST_TYPE = "UNICAST"; // multicast is not yet supported
|
localparam CAST_TYPE = "UNICAST"; // multicast is not yet supported
|
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
if(CAST_TYPE!= "UNICAST") begin : no_unicast
|
if(CAST_TYPE!= "UNICAST") begin : muticast
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
|
|
|
// for multicast we send one packet to each direction in order. The priority is according to DoR routing dimentions
|
|
|
fwft_fifo_with_output_clear #(
|
fwft_fifo_with_output_clear #(
|
.DATA_WIDTH(DSTPw),
|
.DATA_WIDTH(DSTPw),
|
.MAX_DEPTH (MAX_PCK),
|
.MAX_DEPTH (MAX_PCK),
|
.IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
|
.IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
|
)
|
)
|
dest_fifo
|
dest_fifo
|
(
|
(
|
.din(destport_in_encoded),
|
.din(destport_in_encoded),
|
.wr_en(wr_hdr_fwft_fifo[i]), // Write enable
|
.wr_en(wr_hdr_fwft_fifo[i]), // Write enable
|
.rd_en(rd_hdr_fwft_fifo[i]), // Read the next word
|
.rd_en(rd_hdr_fwft_fifo[i]), // Read the next word
|
.dout(dest_port_encoded[(i+1)*DSTPw-1 : i*DSTPw]), // Data out
|
.dout(dest_port_multi[i]), // Data out
|
.full(),
|
.full(),
|
.nearly_full(),
|
.nearly_full(),
|
.recieve_more_than_0(),
|
.recieve_more_than_0(),
|
.recieve_more_than_1(),
|
.recieve_more_than_1(),
|
.reset(reset),
|
.reset(reset),
|
.clk(clk),
|
.clk(clk),
|
.clear(destport_clear[(i+1)*DSTPw-1 : i*DSTPw]) // clear the destination ports once it got its flit
|
.clear(clear_dspt_mulicast [i]) // clear the destination port once it got the entire packet
|
|
);
|
|
|
|
//TODO remove multiple_dest[i] to see if it works?
|
|
|
|
assign clear_dspt_mulicast [i] = (reset_ivc[i] & multiple_dest[i]) ? dest_port_encoded[i] : {DSTPw{1'b0}};
|
|
|
|
// a fix priority arbiter.
|
|
multicast_dst_sel sel(
|
|
.destport_in(dest_port_multi[i]),
|
|
.destport_out(dest_port_encoded[i])
|
);
|
);
|
|
|
|
//check if we have multiple port to send a packet to
|
|
is_onehot0 #(
|
|
.IN_WIDTH(DSTPw)
|
|
)
|
|
one_h
|
|
(
|
|
.in(dest_port_multi[i]),
|
|
.result(dst_onhot0[i])
|
|
);
|
|
assign multiple_dest[i]=~dst_onhot0[i];
|
|
|
|
|
|
end else begin : unicast
|
|
assign multiple_dest[i] = 1'b0;
|
|
|
|
|
|
//lk_dst_fifo
|
|
fwft_fifo #(
|
|
.DATA_WIDTH(DSTPw),
|
|
.MAX_DEPTH (MAX_PCK),
|
|
.IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
|
|
)
|
|
lk_dest_fifo
|
|
(
|
|
.din (lk_destination_in_encoded),
|
|
.wr_en (wr_hdr_fwft_fifo_delay [i]), // Write enable
|
|
.rd_en (rd_hdr_fwft_fifo_delay [i]), // Read the next word
|
|
.dout (lk_destination_encoded [(i+1)*DSTPw-1 : i*DSTPw]), // Data out
|
|
.full (),
|
|
.nearly_full (),
|
|
.recieve_more_than_0 (),
|
|
.recieve_more_than_1 (),
|
|
.reset (reset),
|
|
.clk (clk)
|
|
|
|
);
|
|
|
|
|
|
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
end else if( ROUTE_TYPE=="DETERMINISTIC") begin : dtrmn_dest
|
if( ROUTE_TYPE=="DETERMINISTIC") begin : dtrmn_dest
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
//destport_fifo
|
//destport_fifo
|
fwft_fifo #(
|
fwft_fifo #(
|
.DATA_WIDTH(DSTPw),
|
.DATA_WIDTH(DSTPw),
|
.MAX_DEPTH (MAX_PCK),
|
.MAX_DEPTH (MAX_PCK),
|
| Line 720... |
Line 775... |
dest_fifo
|
dest_fifo
|
(
|
(
|
.din(destport_in_encoded),
|
.din(destport_in_encoded),
|
.wr_en(wr_hdr_fwft_fifo[i]), // Write enable
|
.wr_en(wr_hdr_fwft_fifo[i]), // Write enable
|
.rd_en(rd_hdr_fwft_fifo[i]), // Read the next word
|
.rd_en(rd_hdr_fwft_fifo[i]), // Read the next word
|
.dout(dest_port_encoded[(i+1)*DSTPw-1 : i*DSTPw]), // Data out
|
.dout(dest_port_encoded[i]), // Data out
|
.full(),
|
.full(),
|
.nearly_full(),
|
.nearly_full(),
|
.recieve_more_than_0(),
|
.recieve_more_than_0(),
|
.recieve_more_than_1(),
|
.recieve_more_than_1(),
|
.reset(reset),
|
.reset(reset),
|
| Line 741... |
Line 796... |
dest_fifo
|
dest_fifo
|
(
|
(
|
.din(destport_in_encoded),
|
.din(destport_in_encoded),
|
.wr_en(wr_hdr_fwft_fifo[i]), // Write enable
|
.wr_en(wr_hdr_fwft_fifo[i]), // Write enable
|
.rd_en(rd_hdr_fwft_fifo[i]), // Read the next word
|
.rd_en(rd_hdr_fwft_fifo[i]), // Read the next word
|
.dout(dest_port_encoded[(i+1)*DSTPw-1 : i*DSTPw]), // Data out
|
.dout(dest_port_encoded[i]), // Data out
|
.full(),
|
.full(),
|
.nearly_full(),
|
.nearly_full(),
|
.recieve_more_than_0(),
|
.recieve_more_than_0(),
|
.recieve_more_than_1(),
|
.recieve_more_than_1(),
|
.reset(reset),
|
.reset(reset),
|
.clk(clk),
|
.clk(clk),
|
.clear(destport_clear[(i+1)*DSTPw-1 : i*DSTPw]) // clear other destination ports once one of them is selected
|
.clear(destport_clear[i]) // clear other destination ports once one of them is selected
|
);
|
);
|
|
|
|
|
end
|
end
|
|
end//unicast
|
|
|
|
|
destp_generator #(
|
destp_generator #(
|
.TOPOLOGY(TOPOLOGY),
|
.TOPOLOGY(TOPOLOGY),
|
.ROUTE_NAME(ROUTE_NAME),
|
.ROUTE_NAME(ROUTE_NAME),
|
| Line 767... |
Line 822... |
.P(P),
|
.P(P),
|
.DSTPw(DSTPw),
|
.DSTPw(DSTPw),
|
.PLw(PLw),
|
.PLw(PLw),
|
.PPSw(PPSw),
|
.PPSw(PPSw),
|
.SELF_LOOP_EN (SELF_LOOP_EN),
|
.SELF_LOOP_EN (SELF_LOOP_EN),
|
.SW_LOC(SW_LOC)
|
.SW_LOC(SW_LOC),
|
|
.CAST_TYPE(CAST_TYPE)
|
)
|
)
|
decoder
|
decoder
|
(
|
(
|
.destport_one_hot (destport_one_hot[i]),
|
.destport_one_hot (destport_one_hot[i]),
|
.dest_port_encoded(dest_port_encoded[(i+1)*DSTPw-1 : i*DSTPw]),
|
.dest_port_encoded(dest_port_encoded[i]),
|
.dest_port_out(dest_port[(i+1)*P_1-1 : i*P_1]),
|
.dest_port_out(dest_port[(i+1)*P_1-1 : i*P_1]),
|
.endp_localp_num(endp_localp_num[(i+1)*PLw-1 : i*PLw]),
|
.endp_localp_num(endp_localp_num[(i+1)*PLw-1 : i*PLw]),
|
.swap_port_presel(swap_port_presel[i]),
|
.swap_port_presel(swap_port_presel[i]),
|
.port_pre_sel(port_pre_sel),
|
.port_pre_sel(port_pre_sel),
|
.odd_column(odd_column)
|
.odd_column(odd_column)
|
);
|
);
|
|
|
|
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1)) begin : multi_local
|
if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1) && (CAST_TYPE== "UNICAST")) begin : multi_local
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
// the router has multiple local ports. Save the destination local port
|
// the router has multiple local ports. Save the destination local port
|
|
|
|
|
|
|
| Line 807... |
Line 863... |
.recieve_more_than_1(),
|
.recieve_more_than_1(),
|
.reset(reset),
|
.reset(reset),
|
.clk(clk)
|
.clk(clk)
|
);
|
);
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
end else if ( TOPOLOGY == "FMESH") begin : fmesh
|
end else if ( TOPOLOGY == "FMESH" && CAST_TYPE== "UNICAST") begin : fmesh
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
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|
|
fwft_fifo #(
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fwft_fifo #(
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.DATA_WIDTH(Pw),
|
.DATA_WIDTH(Pw),
|
.MAX_DEPTH (MAX_PCK),
|
.MAX_DEPTH (MAX_PCK),
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| Line 902... |
Line 958... |
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/* verilator lint_off WIDTH */
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/* verilator lint_off WIDTH */
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if(COMBINATION_TYPE == "COMB_NONSPEC") begin : nonspec
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if(COMBINATION_TYPE == "COMB_NONSPEC") begin : nonspec
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/* verilator lint_on WIDTH */
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/* verilator lint_on WIDTH */
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|
|
|
|
|
|
|
|
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/*
|
|
|
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always @(posedge clk)
|
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if ((ivc_not_empty & flit_is_tail2) != (ivc_not_empty & flit_is_tail))begin
|
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$display("ERROR: %b !=%b",flit_is_tail2 , flit_is_tail ) ;
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$finish;
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end
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*/
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|
|
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|
flit_buffer #(
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flit_buffer #(
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.V(V),
|
|
.B(PORT_B), // buffer space :flit per VC
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.B(PORT_B), // buffer space :flit per VC
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.PCK_TYPE(PCK_TYPE),
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|
.Fw(Fw),
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.DEBUG_EN(DEBUG_EN),
|
|
.SSA_EN(SSA_EN)
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.SSA_EN(SSA_EN)
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)
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)
|
the_flit_buffer
|
the_flit_buffer
|
(
|
(
|
|
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| Line 922... |
Line 987... |
.rd_en(any_ivc_sw_request_granted), // Read the next word
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.rd_en(any_ivc_sw_request_granted), // Read the next word
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.dout(buffer_out), // Data out
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.dout(buffer_out), // Data out
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.vc_not_empty(ivc_not_empty),
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.vc_not_empty(ivc_not_empty),
|
.reset(reset),
|
.reset(reset),
|
.clk(clk),
|
.clk(clk),
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.ssa_rd(ssa_ctrl_in.ivc_num_getting_sw_grant)
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.ssa_rd(ssa_ctrl_in.ivc_num_getting_sw_grant),
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.multiple_dest( multiple_dest ),
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.sub_rd_ptr_ld(reset_ivc) ,
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|
.flit_is_tail(flit_is_tail)
|
);
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);
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|
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end else begin :spec//not nonspec comb
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end else begin :spec//not nonspec comb
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|
|
|
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flit_buffer #(
|
flit_buffer #(
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.V(V),
|
|
.B(PORT_B), // buffer space :flit per VC
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.B(PORT_B), // buffer space :flit per VC
|
.PCK_TYPE(PCK_TYPE),
|
|
.Fw(Fw),
|
|
.DEBUG_EN(DEBUG_EN),
|
|
.SSA_EN(SSA_EN)
|
.SSA_EN(SSA_EN)
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)
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)
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the_flit_buffer
|
the_flit_buffer
|
(
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(
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.din(flit_in), // Data in
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.din(flit_in), // Data in
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.vc_num_wr(vc_num_in),//write vertual chanel
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.vc_num_wr(vc_num_in),//write virtual channel
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.vc_num_rd(ivc_num_getting_sw_grant),//read vertual chanel
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.vc_num_rd(ivc_num_getting_sw_grant),//read virtual channel
|
.wr_en(flit_in_wr), // Write enable
|
.wr_en(flit_in_wr), // Write enable
|
.rd_en(any_ivc_sw_request_granted), // Read the next word
|
.rd_en(any_ivc_sw_request_granted), // Read the next word
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.dout(buffer_out), // Data out
|
.dout(buffer_out), // Data out
|
.vc_not_empty(ivc_not_empty),
|
.vc_not_empty(ivc_not_empty),
|
.reset(reset),
|
.reset(reset),
|
.clk(clk),
|
.clk(clk),
|
.ssa_rd(ssa_ctrl_in.ivc_num_getting_sw_grant)
|
.ssa_rd(ssa_ctrl_in.ivc_num_getting_sw_grant),
|
|
.multiple_dest( multiple_dest ),
|
|
.sub_rd_ptr_ld(reset_ivc) ,
|
|
.flit_is_tail(flit_is_tail)
|
|
|
);
|
);
|
|
|
end
|
end
|
endgenerate
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|
|
|
|
|
|
/* verilator lint_off WIDTH */
|
|
if(CAST_TYPE== "UNICAST") begin : unicast
|
|
/* verilator lint_on WIDTH */
|
look_ahead_routing #(
|
look_ahead_routing #(
|
.T1(T1),
|
.T1(T1),
|
.T2(T2),
|
.T2(T2),
|
.T3(T3),
|
.T3(T3),
|
.T4(T4),
|
.T4(T4),
|
.P(P),
|
.P(P),
|
.RAw(RAw),
|
.RAw(RAw),
|
.EAw(EAw),
|
.EAw(EAw),
|
|
.DAw(DAw),
|
.DSTPw(DSTPw),
|
.DSTPw(DSTPw),
|
.SW_LOC(SW_LOC),
|
.SW_LOC(SW_LOC),
|
.TOPOLOGY(TOPOLOGY),
|
.TOPOLOGY(TOPOLOGY),
|
.ROUTE_NAME(ROUTE_NAME),
|
.ROUTE_NAME(ROUTE_NAME),
|
.ROUTE_TYPE(ROUTE_TYPE)
|
.ROUTE_TYPE(ROUTE_TYPE)
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| Line 978... |
Line 1050... |
.destport_encoded(destport_in_encoded),
|
.destport_encoded(destport_in_encoded),
|
.lkdestport_encoded(lk_destination_in_encoded),
|
.lkdestport_encoded(lk_destination_in_encoded),
|
.reset(reset),
|
.reset(reset),
|
.clk(clk)
|
.clk(clk)
|
);
|
);
|
|
end // unicast
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|
|
|
|
|
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endgenerate
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|
|
|
|
|
|
header_flit_update_lk_route_ovc #(
|
header_flit_update_lk_route_ovc #(
|
.P(P)
|
.P(P)
|
)
|
)
|
the_flit_update
|
the_flit_update
|
| Line 1003... |
Line 1082... |
//synthesis translate_off
|
//synthesis translate_off
|
//synopsys translate_off
|
//synopsys translate_off
|
generate
|
generate
|
if(DEBUG_EN) begin :debg
|
if(DEBUG_EN) begin :debg
|
|
|
|
|
|
|
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
if((|vsa_ctrl_in.ivc_num_getting_sw_grant) & (|ssa_ctrl_in.ivc_num_getting_sw_grant))begin
|
if((|vsa_ctrl_in.ivc_num_getting_sw_grant) & (|ssa_ctrl_in.ivc_num_getting_sw_grant))begin
|
$display("%t: ERROR: VSA/SSA conflict: an input port cannot get both sva and ssa grant at the same time %m",$time);
|
$display("%t: ERROR: VSA/SSA conflict: an input port cannot get both sva and ssa grant at the same time %m",$time);
|
$finish;
|
$finish;
|
end
|
end
|
| Line 1023... |
Line 1104... |
if( ~ $onehot0( {vsa_ctrl_in.ivc_num_getting_ovc_grant[i],ssa_ctrl_in.ivc_num_getting_ovc_grant[i],(smart_ctrl_in.ivc_num_getting_ovc_grant[i]&& (PCK_TYPE == "MULTI_FLIT"))})) begin
|
if( ~ $onehot0( {vsa_ctrl_in.ivc_num_getting_ovc_grant[i],ssa_ctrl_in.ivc_num_getting_ovc_grant[i],(smart_ctrl_in.ivc_num_getting_ovc_grant[i]&& (PCK_TYPE == "MULTI_FLIT"))})) begin
|
$display("%t: ERROR: ivc num %d getting more than one ovc grant from VSA,SSA,SMART: %m",$time,i);
|
$display("%t: ERROR: ivc num %d getting more than one ovc grant from VSA,SSA,SMART: %m",$time,i);
|
$finish;
|
$finish;
|
end
|
end
|
end//always
|
end//always
|
|
|
|
|
|
|
|
always @(posedge clk) begin
|
|
if((dest_port [(i+1)*P_1-1 : i*P_1] == {P_1{1'b0}}) && (ivc_request[i]==1'b1)) begin
|
|
$display ("%t: ERROR: The destination port is not set for an active IVC request: %m \n",$time);
|
|
$finish;
|
end
|
end
|
|
end
|
|
end//for
|
|
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS")) begin : mesh_based
|
if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && CAST_TYPE== "UNICAST") begin : mesh_based
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
|
|
debug_mesh_tori_route_ckeck #(
|
debug_mesh_tori_route_ckeck #(
|
.T1(T1),
|
.T1(T1),
|
.T2(T2),
|
.T2(T2),
|
| Line 1103... |
Line 1193... |
parameter P=5,
|
parameter P=5,
|
parameter DSTPw=4,
|
parameter DSTPw=4,
|
parameter PLw=1,
|
parameter PLw=1,
|
parameter PPSw=4,
|
parameter PPSw=4,
|
parameter SW_LOC=0,
|
parameter SW_LOC=0,
|
parameter SELF_LOOP_EN="NO"
|
parameter SELF_LOOP_EN="NO",
|
|
parameter CAST_TYPE = "UNICAST"
|
|
|
)
|
)
|
(
|
(
|
destport_one_hot,
|
destport_one_hot,
|
dest_port_encoded,
|
dest_port_encoded,
|
| Line 1126... |
Line 1217... |
input swap_port_presel;
|
input swap_port_presel;
|
input [PPSw-1 : 0] port_pre_sel;
|
input [PPSw-1 : 0] port_pre_sel;
|
input odd_column;
|
input odd_column;
|
|
|
generate
|
generate
|
|
|
|
/* verilator lint_off WIDTH */
|
|
if(CAST_TYPE!= "UNICAST") begin : muticast
|
|
/* verilator lint_on WIDTH */
|
|
// destination port is not coded for multicast/broadcast
|
|
if( SELF_LOOP_EN=="NO") begin : nslp
|
|
remove_sw_loc_one_hot #(
|
|
.P(P),
|
|
.SW_LOC(SW_LOC)
|
|
)
|
|
remove_sw_loc
|
|
(
|
|
.destport_in(dest_port_encoded),
|
|
.destport_out(dest_port_out)
|
|
);
|
|
end else begin : slp
|
|
assign dest_port_out = dest_port_encoded;
|
|
end
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
if(TOPOLOGY == "FATTREE" ) begin : fat
|
end else if(TOPOLOGY == "FATTREE" ) begin : fat
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
fattree_destp_generator #(
|
fattree_destp_generator #(
|
.K(T1),
|
.K(T1),
|
.P(P),
|
.P(P),
|
.SW_LOC(SW_LOC),
|
.SW_LOC(SW_LOC),
|
| Line 1180... |
Line 1289... |
.dest_port_out(dest_port_out),
|
.dest_port_out(dest_port_out),
|
.swap_port_presel(swap_port_presel),
|
.swap_port_presel(swap_port_presel),
|
.port_pre_sel(port_pre_sel),
|
.port_pre_sel(port_pre_sel),
|
.odd_column(odd_column)// only needed for odd even routing
|
.odd_column(odd_column)// only needed for odd even routing
|
);
|
);
|
|
/* verilator lint_off WIDTH */
|
end else if (TOPOLOGY == "FMESH") begin :fmesh
|
end else if (TOPOLOGY == "FMESH") begin :fmesh
|
|
/* verilator lint_on WIDTH */
|
fmesh_destp_generator #(
|
fmesh_destp_generator #(
|
.ROUTE_NAME(ROUTE_NAME),
|
.ROUTE_NAME(ROUTE_NAME),
|
.ROUTE_TYPE(ROUTE_TYPE),
|
.ROUTE_TYPE(ROUTE_TYPE),
|
.P(P),
|
.P(P),
|
.DSTPw(DSTPw),
|
.DSTPw(DSTPw),
|
