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URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_noc/] [ss_allocator.sv] - Diff between revs 54 and 55

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Rev 54 Rev 55
Line 50... Line 50... 
       // assigned_ovc_not_full_all,
 
       // assigned_ovc_not_full_all,
 
       // dest_port_encoded_all,
 
       // dest_port_encoded_all,
 
       // assigned_ovc_num_all,
 
       // assigned_ovc_num_all,
 
       // ovc_is_assigned_all,
 
       // ovc_is_assigned_all,
 
        ivc_info,
 
        ivc_info,
 
 
 
        ovc_info,
 
        ssa_ctrl_o
 
        ssa_ctrl_o
 
   );
 
   );
 
 
 
 
 
 
 
 
 
    localparam  PV          =   V   *   P,
 
    localparam  PV          =   V   *   P,
Line 86... Line 87... 
    input   [PV-1           :   0]  ovc_avalable_all;
 
    input   [PV-1           :   0]  ovc_avalable_all;
 
 
 
 
 
 
 
 
 
    input   reset,clk;
 
    input   reset,clk;
 
    input   ivc_info_t   ivc_info   [P-1 : 0][V-1 : 0];
 
    input   ivc_info_t   ivc_info   [P-1 : 0][V-1 : 0];
 
 
 
    input   ovc_info_t   ovc_info   [P-1 : 0][V-1 : 0];
 
    output  ssa_ctrl_t   ssa_ctrl_o [P-1 : 0];
 
    output  ssa_ctrl_t   ssa_ctrl_o [P-1 : 0];
 
 
 
 
 
 
 
 
 
    wire   [PV-1      :   0] ovc_allocated_all;
 
    wire   [PV-1      :   0] ovc_allocated_all;
 
    wire   [PV-1      :   0] ovc_released_all;
 
    wire   [PV-1      :   0] ovc_released_all;
Line 112... Line 114... 
    wire [PV-1       : 0] ivc_request_all;
 
    wire [PV-1       : 0] ivc_request_all;
 
    wire [PV-1       : 0] assigned_ovc_not_full_all;
 
    wire [PV-1       : 0] assigned_ovc_not_full_all;
 
    wire [PVDSTPw-1  : 0] dest_port_encoded_all;
 
    wire [PVDSTPw-1  : 0] dest_port_encoded_all;
 
    wire [PVV-1      : 0] assigned_ovc_num_all;
 
    wire [PVV-1      : 0] assigned_ovc_num_all;
 
    wire [PV-1       : 0] ovc_is_assigned_all;
 
    wire [PV-1       : 0] ovc_is_assigned_all;
 
 
 
    wire [MAX_P-1     : 0] destport_one_hot [PV-1 : 0];
 
 
 
 
 
        genvar i;
 
        genvar i;
 
    // there is no ssa for local port in 5 and 3 port routers
 
    // there is no ssa for local port in 5 and 3 port routers
 
    generate
 
    generate
 
    for (i=0; i
 
    for (i=0; i
 
 
 
 
 
        localparam  C_PORT  = i/V;
 
        localparam  C_PORT  = i/V;
 
        localparam  SS_PORT = strieght_port (P,C_PORT);
 
        localparam  SS_PORT = strieght_port (P,C_PORT);
 
 
 
 
 
        assign ivc_request_all[i] = ivc_info[C_PORT][i%V].ivc_req;
 
        assign ivc_request_all[i] = ivc_info[C_PORT][i%V].ivc_req;
 
        assign assigned_ovc_not_full_all[i] = ivc_info[C_PORT][i%V].assigned_ovc_not_full;
 
        assign assigned_ovc_not_full_all[i] = ~ovc_info[SS_PORT][i%V].full;
 
 
 
        //assign assigned_ovc_not_full_all[i] = ivc_info[C_PORT][i%V].assigned_ovc_not_full;
 
 
 
 
 
        assign dest_port_encoded_all [(i+1)*DSTPw-1 : i*DSTPw] = ivc_info[C_PORT][i%V].dest_port_encoded;
 
        assign dest_port_encoded_all [(i+1)*DSTPw-1 : i*DSTPw] = ivc_info[C_PORT][i%V].dest_port_encoded;
 
        assign assigned_ovc_num_all[(i+1)*V-1 : i*V] = ivc_info[C_PORT][i%V].assigned_ovc_num;
 
        assign assigned_ovc_num_all[(i+1)*V-1 : i*V] = ivc_info[C_PORT][i%V].assigned_ovc_num;
 
        assign ovc_is_assigned_all[i] = ivc_info[C_PORT][i%V].ovc_is_assigned;
 
        assign ovc_is_assigned_all[i] = ivc_info[C_PORT][i%V].ovc_is_assigned;
 
 
 
 
 
 
 
        assign destport_one_hot[i] = ivc_info[C_PORT][i%V].destport_one_hot;
 
 
 
 
 
 
 
 
 
        if (SS_PORT == DISABLED)begin : no_prefrable
 
        if (SS_PORT == DISABLED)begin : no_prefrable
 
 
 
 
 
 
 
 
Line 182... Line 188... 
                .granted_ovc_num(granted_ovc_num_all[(i+1)*V-1 : i*V]),
 
                .granted_ovc_num(granted_ovc_num_all[(i+1)*V-1 : i*V]),
 
                .ivc_num_getting_sw_grant(ivc_num_getting_sw_grant_all[i]),
 
                .ivc_num_getting_sw_grant(ivc_num_getting_sw_grant_all[i]),
 
                .ivc_num_getting_ovc_grant(ivc_num_getting_ovc_grant_all[i]),
 
                .ivc_num_getting_ovc_grant(ivc_num_getting_ovc_grant_all[i]),
 
                .ivc_reset(ivc_reset_all[i]),
 
                .ivc_reset(ivc_reset_all[i]),
 
                .single_flit_pck(single_flit_pck_all[i]),
 
                .single_flit_pck(single_flit_pck_all[i]),
 
 
 
                .destport_one_hot(destport_one_hot[i]),
 
                .decreased_credit_in_ss_ovc(decreased_credit_in_ss_ovc[i])
 
                .decreased_credit_in_ss_ovc(decreased_credit_in_ss_ovc[i])
 
                //synthesis translate_off
 
                //synthesis translate_off
 
                //synopsys  translate_off
 
                //synopsys  translate_off
 
                ,.clk(clk)
 
                ,.clk(clk)
 
                //synopsys  translate_on
 
                //synopsys  translate_on
Line 263... Line 270... 
        destport_encoded,
 
        destport_encoded,
 
        ovc_released,
 
        ovc_released,
 
        ovc_allocated,
 
        ovc_allocated,
 
        decreased_credit_in_ss_ovc,
 
        decreased_credit_in_ss_ovc,
 
        single_flit_pck,
 
        single_flit_pck,
 
 
 
        destport_one_hot,
 
        ivc_reset
 
        ivc_reset
 
//synthesis translate_off
 
//synthesis translate_off
 
//synopsys  translate_off
 
//synopsys  translate_off
 
        ,clk
 
        ,clk
 
//synopsys  translate_on
 
//synopsys  translate_on
Line 294... Line 302... 
    input                          ivc_request;
 
    input                          ivc_request;
 
    input                          assigned_ovc_not_full;
 
    input                          assigned_ovc_not_full;
 
    input   [DSTPw-1      :    0]  destport_encoded;//exsited packet destination port
 
    input   [DSTPw-1      :    0]  destport_encoded;//exsited packet destination port
 
    input                          assigned_to_ssovc;
 
    input                          assigned_to_ssovc;
 
    input                          ovc_is_assigned;
 
    input                          ovc_is_assigned;
 
 
 
    input   [MAX_P-1       :    0]  destport_one_hot;
 
 
 
 
 
    output reg [V-1          :   0]  granted_ovc_num;
 
    output reg [V-1          :   0]  granted_ovc_num;
 
    output                        ivc_num_getting_sw_grant;
 
    output                        ivc_num_getting_sw_grant;
 
    output                        ivc_num_getting_ovc_grant;
 
    output                        ivc_num_getting_ovc_grant;
 
    output                        ovc_released;
 
    output                        ovc_released;
Line 337... Line 346... 
        (MIN_PCK_SIZE==1)?  hdr_flg & tail_flg : 1'b0;
 
        (MIN_PCK_SIZE==1)?  hdr_flg & tail_flg : 1'b0;
 
    /* verilator lint_on WIDTH */
 
    /* verilator lint_on WIDTH */
 
 
 
 
 
 
 
 
 
    wire   condition_1_2_valid;
 
    wire   condition_1_2_valid;
 
 
 
    wire [DAw-1 : 0]  dest_e_addr_in;
 
 
 
 
 
    extract_header_flit_info #(
 
    extract_header_flit_info #(
 
        .DATA_w(0)
 
        .DATA_w(0)
 
       )
 
       )
 
       extractor
 
       extractor
Line 348... Line 358... 
        .flit_in(flit_in),
 
        .flit_in(flit_in),
 
        .flit_in_wr(flit_in_wr),
 
        .flit_in_wr(flit_in_wr),
 
        .class_o(),
 
        .class_o(),
 
        .destport_o(destport_in_encoded),
 
        .destport_o(destport_in_encoded),
 
        .src_e_addr_o( ),
 
        .src_e_addr_o( ),
 
        .dest_e_addr_o( ),
 
        .dest_e_addr_o(dest_e_addr_in ),
 
        .vc_num_o(vc_num_in),
 
        .vc_num_o(vc_num_in),
 
        .hdr_flit_wr_o( ),
 
        .hdr_flit_wr_o( ),
 
        .hdr_flg_o(hdr_flg),
 
        .hdr_flg_o(hdr_flg),
 
        .tail_flg_o(tail_flg),
 
        .tail_flg_o(tail_flg),
 
        .weight_o( ),
 
        .weight_o( ),
Line 368... Line 378... 
 
 
 
 
//check destination port is ss
 
//check destination port is ss
 
wire ss_port_hdr_flit, ss_port_nonhdr_flit;
 
wire ss_port_hdr_flit, ss_port_nonhdr_flit;
 
 
 
 
 
ssa_check_destport #(
 
ssa_check_destport #(
 
    .TOPOLOGY(TOPOLOGY),
 
 
 
    .ROUTE_TYPE(ROUTE_TYPE),
 
 
 
    .SW_LOC(SW_LOC),
 
    .SW_LOC(SW_LOC),
 
    .P(P),
 
    .P(P),
 
    .DEBUG_EN(DEBUG_EN),
 
 
 
    .DSTPw(DSTPw),
 
 
 
    .SS_PORT(SS_PORT)
 
    .SS_PORT(SS_PORT)
 
)
 
)
 
 check_destport
 
 check_destport
 
(
 
(
 
    .destport_encoded(destport_encoded),
 
    .destport_encoded(destport_encoded),
 
    .destport_in_encoded(destport_in_encoded),
 
    .destport_in_encoded(destport_in_encoded),
 
 
 
    .destport_one_hot(destport_one_hot),
 
    .ss_port_hdr_flit(ss_port_hdr_flit),
 
    .ss_port_hdr_flit(ss_port_hdr_flit),
 
 
 
    .dest_e_addr_in(dest_e_addr_in),
 
 
 
 
 
    .ss_port_nonhdr_flit(ss_port_nonhdr_flit)
 
    .ss_port_nonhdr_flit(ss_port_nonhdr_flit)
 
//synthesis translate_off
 
//synthesis translate_off
 
//synopsys  translate_off
 
//synopsys  translate_off
 
    ,.clk(clk),
 
    ,.clk(clk),
 
    .ivc_num_getting_sw_grant(ivc_num_getting_sw_grant),
 
    .ivc_num_getting_sw_grant(ivc_num_getting_sw_grant),
Line 444... Line 453... 
 
 
 
 
endmodule
 
endmodule
 
 
 
 
 
 
 
 
 
 
 
 
 
module ssa_check_destport #(
 
module ssa_check_destport
 
    parameter TOPOLOGY = "MESH",
 
        import pronoc_pkg::*;
 
    parameter ROUTE_TYPE="DETERMINISTIC",
 
#(
 
    parameter SW_LOC = 0,
 
    parameter SW_LOC = 0,
 
    parameter P=5,
 
    parameter P=5,
 
    parameter DEBUG_EN = 0,
 
 
 
    parameter DSTPw = P-1,
 
 
 
    parameter SS_PORT=0
 
    parameter SS_PORT=0
 
)(
 
)(
 
    destport_encoded, //non header flit dest port
 
    destport_encoded, //non header flit dest port
 
    destport_in_encoded, // header flit packet dest port
 
    destport_in_encoded, // header flit packet dest port
 
    ss_port_hdr_flit, // asserted if the header incomming flit goes to ss port
 
    ss_port_hdr_flit, // asserted if the header incomming flit goes to ss port
 
    ss_port_nonhdr_flit // assert if the body or tail incomming flit goes to ss port
 
    ss_port_nonhdr_flit, // assert if the body or tail incomming flit goes to ss port
 
 
 
    dest_e_addr_in,
 
 
 
    destport_one_hot
 
 
 
 
 
//synthesis translate_off
 
//synthesis translate_off
 
//synopsys  translate_off
 
//synopsys  translate_off
 
    ,clk,
 
    ,clk,
 
    ivc_num_getting_sw_grant,
 
    ivc_num_getting_sw_grant,
 
    hdr_flg
 
    hdr_flg
Line 473... Line 483... 
    input clk,   ivc_num_getting_sw_grant, hdr_flg;
 
    input clk,   ivc_num_getting_sw_grant, hdr_flg;
 
//synopsys  translate_on
 
//synopsys  translate_on
 
//synthesis translate_on
 
//synthesis translate_on
 
 
 
 
 
    input [DSTPw-1 : 0] destport_encoded, destport_in_encoded;
 
    input [DSTPw-1 : 0] destport_encoded, destport_in_encoded;
 
 
 
    input [MAX_P-1 : 0] destport_one_hot; // buffered flit destination port
 
 
 
    input [DAw-1 : 0]  dest_e_addr_in;
 
    output ss_port_hdr_flit, ss_port_nonhdr_flit;
 
    output ss_port_hdr_flit, ss_port_nonhdr_flit;
 
 
 
 
 
    generate
 
    generate
 
    /* verilator lint_off WIDTH */
 
    /* verilator lint_off WIDTH */
 
    if(TOPOLOGY == "FATTREE") begin : fat
 
    if(TOPOLOGY == "FATTREE") begin : fat
Line 492... Line 504... 
        .destport_in_encoded(destport_in_encoded),
 
        .destport_in_encoded(destport_in_encoded),
 
        .ss_port_hdr_flit(ss_port_hdr_flit),
 
        .ss_port_hdr_flit(ss_port_hdr_flit),
 
        .ss_port_nonhdr_flit(ss_port_nonhdr_flit)
 
        .ss_port_nonhdr_flit(ss_port_nonhdr_flit)
 
       );
 
       );
 
     /* verilator lint_off WIDTH */
 
     /* verilator lint_off WIDTH */
 
    end else if (TOPOLOGY == "MESH" || TOPOLOGY == "TORUS" || TOPOLOGY == "FMESH") begin : mesh
 
    end else if (TOPOLOGY == "MESH" || TOPOLOGY == "TORUS" ) begin : mesh
 
    /* verilator lint_on WIDTH */
 
    /* verilator lint_on WIDTH */
 
 
 
 
 
        mesh_torus_ssa_check_destport #(
 
        mesh_torus_ssa_check_destport #(
 
            .ROUTE_TYPE(ROUTE_TYPE),
 
            .ROUTE_TYPE(ROUTE_TYPE),
 
            .SW_LOC(SW_LOC),
 
            .SW_LOC(SW_LOC),
Line 518... Line 530... 
            .hdr_flg(hdr_flg)
 
            .hdr_flg(hdr_flg)
 
            //synopsys  translate_on
 
            //synopsys  translate_on
 
            //synthesis translate_on
 
            //synthesis translate_on
 
 
 
 
 
        );
 
        );
 
 
 
    /* verilator lint_off WIDTH */
 
 
 
    end else if (TOPOLOGY == "FMESH") begin :fmesh
 
 
 
    /* verilator lint_on WIDTH */
 
 
 
        localparam
 
 
 
                ELw = log2(T3),
 
 
 
                Pw  = log2(P),
 
 
 
                PLw = (TOPOLOGY == "FMESH") ? Pw : ELw;
 
 
 
 
 
 
 
        wire [Pw-1 : 0] endp_p_in;
 
 
 
        wire [MAX_P-1 : 0] destport_one_hot_in;
 
 
 
 
 
 
 
        fmesh_endp_addr_decode #(
 
 
 
                        .T1(T1),
 
 
 
                        .T2(T2),
 
 
 
                        .T3(T3),
 
 
 
                        .EAw(EAw)
 
 
 
                )
 
 
 
                endp_addr_decode
 
 
 
                (
 
 
 
                        .e_addr(dest_e_addr_in),
 
 
 
                        .ex(),
 
 
 
                        .ey(),
 
 
 
                        .ep(endp_p_in),
 
 
 
                        .valid()
 
 
 
                );
 
 
 
 
 
 
 
        destp_generator #(
 
 
 
                        .TOPOLOGY(TOPOLOGY),
 
 
 
                        .ROUTE_NAME(ROUTE_NAME),
 
 
 
                        .ROUTE_TYPE(ROUTE_TYPE),
 
 
 
                        .T1(T1),
 
 
 
                        .NL(T3),
 
 
 
                        .P(P),
 
 
 
                        .DSTPw(DSTPw),
 
 
 
                        .PLw(PLw),
 
 
 
                        .PPSw(PPSw),
 
 
 
                        .SELF_LOOP_EN (SELF_LOOP_EN),
 
 
 
                        .SW_LOC(SW_LOC),
 
 
 
                        .CAST_TYPE(CAST_TYPE)
 
 
 
                )
 
 
 
                decoder
 
 
 
                (
 
 
 
                        .destport_one_hot (destport_one_hot_in),
 
 
 
                        .dest_port_encoded(destport_in_encoded),
 
 
 
                        .dest_port_out( ),
 
 
 
                        .endp_localp_num(endp_p_in),
 
 
 
                        .swap_port_presel(1'b0),
 
 
 
                        .port_pre_sel({PPSw{1'b0}}),
 
 
 
                        .odd_column(1'b0)
 
 
 
                );
 
 
 
 
 
 
 
 
 
 
 
    assign ss_port_nonhdr_flit = destport_one_hot [SS_PORT];
 
 
 
    assign ss_port_hdr_flit    = destport_one_hot_in [SS_PORT];
 
 
 
 
 
        end else begin : line
 
        end else begin : line
 
            line_ring_ssa_check_destport #(
 
            line_ring_ssa_check_destport #(
 
               .ROUTE_TYPE(ROUTE_TYPE),
 
               .ROUTE_TYPE(ROUTE_TYPE),
 
                .SW_LOC(SW_LOC),
 
                .SW_LOC(SW_LOC),
 
                .P(P),
 
                .P(P),

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