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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_noc/] [tree_route.v] - Diff between revs 48 and 54

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Rev 48 Rev 54
Line 277... Line 277...
    input  [PLKw-1 : 0]  neighbors_rx;
    input  [PLKw-1 : 0]  neighbors_rx;
    input  [PLw-1 : 0]  neighbors_ry;
    input  [PLw-1 : 0]  neighbors_ry;
    output [DSPw-1: 0]    lkdestport_encoded;
    output [DSPw-1: 0]    lkdestport_encoded;
    input                   reset,clk;
    input                   reset,clk;
 
 
    reg  [DSPw-1 :0]    destport_encoded_delayed;
    wire  [DSPw-1 :0]    destport_encoded_delayed;
    reg  [LKw-1 :0]    dest_addr_encoded_delayed;
    wire  [LKw-1 :0]    dest_addr_encoded_delayed;
 
 
     tree_deterministic_look_ahead_routing #(
     tree_deterministic_look_ahead_routing #(
        .P(P),
        .P(P),
        .ROUTE_NAME(ROUTE_NAME),
        .ROUTE_NAME(ROUTE_NAME),
        .K(K),
        .K(K),
Line 295... Line 295...
        .neighbors_rx(neighbors_rx),
        .neighbors_rx(neighbors_rx),
        .neighbors_ry(neighbors_ry),
        .neighbors_ry(neighbors_ry),
        .lkdestport_encoded(lkdestport_encoded)
        .lkdestport_encoded(lkdestport_encoded)
     );
     );
 
 
 
      pronoc_register #(.W(DSPw)) reg1 (.in(destport_encoded  ), .out(destport_encoded_delayed), .reset(reset), .clk(clk));
 
      pronoc_register #(.W(LKw )) reg2 (.in(dest_addr_encoded ), .out(dest_addr_encoded_delayed),.reset(reset), .clk(clk));
 
 
 
 
 
 
`ifdef SYNC_RESET_MODE
 
    always @ (posedge clk )begin
 
`else
 
    always @ (posedge clk or posedge reset)begin
 
`endif
 
        if(reset)begin
 
            destport_encoded_delayed <= {DSPw{1'b0}};
 
            dest_addr_encoded_delayed<= {LKw{1'b0}};
 
        end else begin
 
            destport_encoded_delayed<=destport_encoded;
 
            dest_addr_encoded_delayed<=dest_addr_encoded;
 
        end//else reset
 
    end//always
 
 
 
endmodule
endmodule
 
 
 
 
 
 

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