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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_c/] [jtag/] [test_rtl/] [jtag_ram_test/] [src_verilog/] [lib/] [generic_ram.v] - Diff between revs 38 and 48

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Rev 38 Rev 48
Line 52... Line 52... 
   clk,
 
   clk,
 
   q_a,
 
   q_a,
 
   q_b
 
   q_b
 
);
 
);
 
 
 
 
 
 
 
/* verilator lint_off WIDTH */
 
localparam BYTE_ENw= ( BYTE_WR_EN == "YES")? Dw/8 : 1;
 
localparam BYTE_ENw= ( BYTE_WR_EN == "YES")? Dw/8 : 1;
 
 
 
/* verilator lint_on WIDTH */
 
 
 
 
 
    input [(Dw-1):0] data_a, data_b;
 
    input [(Dw-1):0] data_a, data_b;
 
    input [(Aw-1):0] addr_a, addr_b;
 
    input [(Aw-1):0] addr_a, addr_b;
 
    input [BYTE_ENw-1   :       0]       byteena_a, byteena_b;
 
    input [BYTE_ENw-1   :       0]       byteena_a, byteena_b;
 
    input we_a, we_b, clk;
 
    input we_a, we_b, clk;
 
    output  [(Dw-1):0] q_a, q_b;
 
    output  [(Dw-1):0] q_a, q_b;
 
 
 
 
 
generate
 
generate
 
 
 
/* verilator lint_off WIDTH */
 
if   ( BYTE_WR_EN == "NO") begin : no_byten
 
if   ( BYTE_WR_EN == "NO") begin : no_byten
 
 
 
/* verilator lint_on WIDTH */
 
        dual_port_ram #(
 
        dual_port_ram #(
 
                .Dw (Dw),
 
                .Dw (Dw),
 
                .Aw (Aw),
 
                .Aw (Aw),
 
                .INITIAL_EN(INITIAL_EN),
 
                .INITIAL_EN(INITIAL_EN),
 
                .INIT_FILE(INIT_FILE)
 
                .INIT_FILE(INIT_FILE)
Line 138... Line 141... 
   we,
 
   we,
 
   clk,
 
   clk,
 
   q
 
   q
 
 
 
 
 
);
 
);
 
 
 
/* verilator lint_off WIDTH */
 
        localparam BYTE_ENw= ( BYTE_WR_EN == "YES")? Dw/8 : 1;
 
        localparam BYTE_ENw= ( BYTE_WR_EN == "YES")? Dw/8 : 1;
 
 
 
/* verilator lint_on WIDTH */
 
 
 
 
 
        input [(Dw-1):0] data;
 
        input [(Dw-1):0] data;
 
        input [(Aw-1):0] addr;
 
        input [(Aw-1):0] addr;
 
        input [BYTE_ENw-1       :       0]       byteen;
 
        input [BYTE_ENw-1       :       0]       byteen;
 
        input we, clk;
 
        input we, clk;
 
        output  [(Dw-1):0] q;
 
        output  [(Dw-1):0] q;
 
 
 
 
 
generate
 
generate
 
 
 
/* verilator lint_off WIDTH */
 
if   ( BYTE_WR_EN == "NO") begin : no_byten
 
if   ( BYTE_WR_EN == "NO") begin : no_byten
 
 
 
/* verilator lint_on WIDTH */
 
 
 
 
 
        single_port_ram #(
 
        single_port_ram #(
 
                .Dw (Dw),
 
                .Dw (Dw),
 
                .Aw (Aw),
 
                .Aw (Aw),
 
                .INITIAL_EN(INITIAL_EN),
 
                .INITIAL_EN(INITIAL_EN),
Line 247... Line 252... 
    // Declare the RAM variable
 
    // Declare the RAM variable
 
    reg [Dw-1:0] ram[2**Aw-1:0];
 
    reg [Dw-1:0] ram[2**Aw-1:0];
 
 
 
 
 
        // initial the memory if the file is defined
 
        // initial the memory if the file is defined
 
        generate
 
        generate
 
 
 
            /* verilator lint_off WIDTH */
 
                if (INITIAL_EN == "YES") begin : init
 
                if (INITIAL_EN == "YES") begin : init
 
 
 
                /* verilator lint_on WIDTH */
 
                    initial $readmemh(INIT_FILE,ram);
 
                    initial $readmemh(INIT_FILE,ram);
 
                end
 
                end
 
        endgenerate
 
        endgenerate
 
 
 
 
 
 
 
 
Line 326... Line 333... 
        // Declare the RAM variable
 
        // Declare the RAM variable
 
        reg [Dw-1:0] ram [2**Aw-1:0];
 
        reg [Dw-1:0] ram [2**Aw-1:0];
 
 
 
 
 
        // initial the memory if the file is defined
 
        // initial the memory if the file is defined
 
        generate
 
        generate
 
 
 
            /* verilator lint_off WIDTH */
 
                if (INITIAL_EN == "YES") begin : init
 
                if (INITIAL_EN == "YES") begin : init
 
 
 
                /* verilator lint_on WIDTH */
 
                    initial $readmemh(INIT_FILE,ram);
 
                    initial $readmemh(INIT_FILE,ram);
 
                end
 
                end
 
        endgenerate
 
        endgenerate
 
 
 
 
 
        always @ (posedge clk)
 
        always @ (posedge clk)
Line 386... Line 395... 
    // Declare the RAM variable
 
    // Declare the RAM variable
 
    reg [Dw-1:0] ram[2**Aw-1:0];
 
    reg [Dw-1:0] ram[2**Aw-1:0];
 
 
 
 
 
        // initial the memory if the file is defined
 
        // initial the memory if the file is defined
 
        generate
 
        generate
 
 
 
            /* verilator lint_off WIDTH */
 
                if (INITIAL_EN == "YES") begin : init
 
                if (INITIAL_EN == "YES") begin : init
 
 
 
                /* verilator lint_on WIDTH */
 
                    initial $readmemh(INIT_FILE,ram);
 
                    initial $readmemh(INIT_FILE,ram);
 
                end
 
                end
 
        endgenerate
 
        endgenerate
 
 
 
 
 
    // Variable to hold the registered read address
 
    // Variable to hold the registered read address

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