URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [mor1kx-3.1/] [rtl/] [verilog/] [mor1kx_true_dpram_sclk.v] - Diff between revs 38 and 42

Rev 38	Rev 42
Line 7...	Line 7...
`Description: True dual port ram with single clock`	`Description: True dual port ram with single clock`

`Copyright (C) 2013 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>`	`Copyright (C) 2013 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>`

`******************************************************************************/`	`******************************************************************************/`
	`timescale 1ns/1ps
`module mor1kx_true_dpram_sclk`	`module mor1kx_true_dpram_sclk`
`#(`	`#(`
`parameter ADDR_WIDTH = 32,`	`parameter ADDR_WIDTH = 32,`
`parameter DATA_WIDTH = 32`	`parameter DATA_WIDTH = 32`
`)`	`)`