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URL https://opencores.org/ocsvn/ao486/ao486/trunk

Subversion Repositories ao486

[/] [ao486/] [trunk/] [rtl/] [ao486/] [ao486_hw.tcl] - Diff between revs 2 and 7

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Rev 2 Rev 7
Line 1... Line 1...
# TCL File Generated by Component Editor 13.1
# TCL File Generated by Component Editor 14.0
# Sun Mar 30 12:22:06 CEST 2014
# Mon Aug 18 22:50:23 CEST 2014
# DO NOT MODIFY
# DO NOT MODIFY
 
 
 
 
# 
# 
# ao486 "ao486" v1.0
# ao486 "ao486" v1.0
#  2014.03.30.12:22:06
#  2014.08.18.22:50:23
# 
# 
# 
# 
 
 
# 
# 
# request TCL package from ACDS 13.1
# request TCL package from ACDS 14.0
# 
# 
package require -exact qsys 13.1
package require -exact qsys 14.0
 
 
 
 
# 
# 
# module ao486
# module ao486
# 
# 
Line 26... Line 26...
set_module_property GROUP ao486
set_module_property GROUP ao486
set_module_property AUTHOR ""
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME ao486
set_module_property DISPLAY_NAME ao486
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property EDITABLE true
set_module_property ANALYZE_HDL AUTO
 
set_module_property REPORT_TO_TALKBACK false
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property ALLOW_GREYBOX_GENERATION false
 
set_module_property REPORT_HIERARCHY false
 
 
 
 
# 
# 
# file sets
# file sets
# 
# 
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL ao486
set_fileset_property QUARTUS_SYNTH TOP_LEVEL ao486
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
 
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file ao486.v VERILOG PATH ao486.v TOP_LEVEL_FILE
add_fileset_file ao486.v VERILOG PATH ao486.v TOP_LEVEL_FILE
add_fileset_file avalon_io.v VERILOG PATH avalon_io.v
add_fileset_file avalon_io.v VERILOG PATH avalon_io.v
add_fileset_file defines.v VERILOG PATH defines.v
add_fileset_file defines.v VERILOG PATH defines.v
add_fileset_file exception.v VERILOG PATH exception.v
add_fileset_file exception.v VERILOG PATH exception.v
add_fileset_file global_regs.v VERILOG PATH global_regs.v
add_fileset_file global_regs.v VERILOG PATH global_regs.v
Line 156... Line 157...
set_interface_property avalon_memory doStreamReads false
set_interface_property avalon_memory doStreamReads false
set_interface_property avalon_memory doStreamWrites false
set_interface_property avalon_memory doStreamWrites false
set_interface_property avalon_memory holdTime 0
set_interface_property avalon_memory holdTime 0
set_interface_property avalon_memory linewrapBursts false
set_interface_property avalon_memory linewrapBursts false
set_interface_property avalon_memory maximumPendingReadTransactions 0
set_interface_property avalon_memory maximumPendingReadTransactions 0
 
set_interface_property avalon_memory maximumPendingWriteTransactions 0
set_interface_property avalon_memory readLatency 0
set_interface_property avalon_memory readLatency 0
set_interface_property avalon_memory readWaitTime 1
set_interface_property avalon_memory readWaitTime 1
set_interface_property avalon_memory setupTime 0
set_interface_property avalon_memory setupTime 0
set_interface_property avalon_memory timingUnits Cycles
set_interface_property avalon_memory timingUnits Cycles
set_interface_property avalon_memory writeWaitTime 0
set_interface_property avalon_memory writeWaitTime 0
Line 183... Line 185...
# 
# 
# connection point interrupt
# connection point interrupt
# 
# 
add_interface interrupt conduit end
add_interface interrupt conduit end
set_interface_property interrupt associatedClock clock
set_interface_property interrupt associatedClock clock
set_interface_property interrupt associatedReset reset_sink
set_interface_property interrupt associatedReset ""
set_interface_property interrupt ENABLED true
set_interface_property interrupt ENABLED true
set_interface_property interrupt EXPORT_OF ""
set_interface_property interrupt EXPORT_OF ""
set_interface_property interrupt PORT_NAME_MAP ""
set_interface_property interrupt PORT_NAME_MAP ""
set_interface_property interrupt CMSIS_SVD_VARIABLES ""
set_interface_property interrupt CMSIS_SVD_VARIABLES ""
set_interface_property interrupt SVD_ADDRESS_GROUP ""
set_interface_property interrupt SVD_ADDRESS_GROUP ""
 
 
add_interface_port interrupt interrupt_do export Input 1
add_interface_port interrupt interrupt_do interrupt_do Input 1
add_interface_port interrupt interrupt_vector export Input 8
add_interface_port interrupt interrupt_vector interrupt_vector Input 8
add_interface_port interrupt interrupt_done export Output 1
add_interface_port interrupt interrupt_done interrupt_done Output 1
 
 
 
 
# 
# 
# connection point avalon_io
# connection point avalon_io
# 
# 
Line 210... Line 212...
set_interface_property avalon_io doStreamReads false
set_interface_property avalon_io doStreamReads false
set_interface_property avalon_io doStreamWrites false
set_interface_property avalon_io doStreamWrites false
set_interface_property avalon_io holdTime 0
set_interface_property avalon_io holdTime 0
set_interface_property avalon_io linewrapBursts false
set_interface_property avalon_io linewrapBursts false
set_interface_property avalon_io maximumPendingReadTransactions 0
set_interface_property avalon_io maximumPendingReadTransactions 0
 
set_interface_property avalon_io maximumPendingWriteTransactions 0
set_interface_property avalon_io readLatency 0
set_interface_property avalon_io readLatency 0
set_interface_property avalon_io readWaitTime 1
set_interface_property avalon_io readWaitTime 1
set_interface_property avalon_io setupTime 0
set_interface_property avalon_io setupTime 0
set_interface_property avalon_io timingUnits Cycles
set_interface_property avalon_io timingUnits Cycles
set_interface_property avalon_io writeWaitTime 0
set_interface_property avalon_io writeWaitTime 0
Line 231... Line 234...
add_interface_port avalon_io avalon_io_write write Output 1
add_interface_port avalon_io avalon_io_write write Output 1
add_interface_port avalon_io avalon_io_writedata writedata Output 32
add_interface_port avalon_io avalon_io_writedata writedata Output 32
add_interface_port avalon_io avalon_io_waitrequest waitrequest Input 1
add_interface_port avalon_io avalon_io_waitrequest waitrequest Input 1
 
 
 
 
# 
 
# connection point reset_only_ao486
 
# 
 
add_interface reset_only_ao486 reset end
 
set_interface_property reset_only_ao486 associatedClock clock
 
set_interface_property reset_only_ao486 synchronousEdges DEASSERT
 
set_interface_property reset_only_ao486 ENABLED true
 
set_interface_property reset_only_ao486 EXPORT_OF ""
 
set_interface_property reset_only_ao486 PORT_NAME_MAP ""
 
set_interface_property reset_only_ao486 CMSIS_SVD_VARIABLES ""
 
set_interface_property reset_only_ao486 SVD_ADDRESS_GROUP ""
 
 
 
add_interface_port reset_only_ao486 rst_internal_n reset_n Input 1
 
 
 
 
 
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