| Line 1781... |
Line 1781... |
<a name="l01788"></a>01788 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a4d9196508aad9e995d45bfda3f7c6884">`SIZE_4</a><span class="vhdlchar"></span>) && (<span class="vhdlchar">ir</span>[<span class="vhdllogic">12</span>] == <span class="vhdllogic">1'b0</span>))
|
<a name="l01788"></a>01788 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a4d9196508aad9e995d45bfda3f7c6884">`SIZE_4</a><span class="vhdlchar"></span>) && (<span class="vhdlchar">ir</span>[<span class="vhdllogic">12</span>] == <span class="vhdllogic">1'b0</span>))
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<a name="l01789"></a>01789 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a0e07cba66f352b53ebb2dd2a48c58cff">`SIZE_5</a><span class="vhdlchar"></span>) && (<span class="vhdlchar">ir</span>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b1</span>))
|
<a name="l01789"></a>01789 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a0e07cba66f352b53ebb2dd2a48c58cff">`SIZE_5</a><span class="vhdlchar"></span>) && (<span class="vhdlchar">ir</span>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b1</span>))
|
<a name="l01790"></a>01790 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a3ce4d5e820fe7c438d0bd9c7f067ac3f">`SIZE_6</a><span class="vhdlchar"></span>) && (<span class="vhdlchar">ir</span>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b000</span>));
|
<a name="l01790"></a>01790 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a3ce4d5e820fe7c438d0bd9c7f067ac3f">`SIZE_6</a><span class="vhdlchar"></span>) && (<span class="vhdlchar">ir</span>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b000</span>));
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<a name="l01791"></a>01791 <span class="vhdlkeyword">end</span>
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<a name="l01791"></a>01791 <span class="vhdlkeyword">end</span>
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<a name="l01792"></a>01792 <span class="vhdlkeyword">end</span>
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<a name="l01792"></a>01792 <span class="vhdlkeyword">end</span>
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<a name="l01793"></a>01793 <span class="keyword">/*OPTIM </span>
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<a name="l01793"></a>01793
|
<a name="l01794"></a>01794 <span class="keyword"> else if(size_control == `SIZE_BYTE) size <= 2'b00;</span>
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<a name="l01794"></a><a class="code" href="classregisters.html#a098bb8c5f886c173a49d1e015dd37289">01794</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
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<a name="l01795"></a>01795 <span class="keyword"> else if(size_control == `SIZE_WORD) size <= 2'b01;</span>
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<a name="l01795"></a>01795 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <a class="code" href="classregisters.html#a69652ae311e16ddcb1bb0dbc90744156">ea_reg</a> <= <span class="vhdllogic">3'b000</span>;
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<a name="l01796"></a>01796 <span class="keyword"> else if(size_control == `SIZE_LONG) size <= 2'b10;</span>
|
<a name="l01796"></a>01796 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a87fed6b8d7f55252c49ab2fc43d39d9a">ea_reg_control</a> == <a class="code" href="ao68000_8v.html#ab608c5385657295b902b8ffc21c43d03">`EA_REG_IR_2_0</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a69652ae311e16ddcb1bb0dbc90744156">ea_reg</a> <= <span class="vhdlchar">ir</span>[<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>];
|
<a name="l01797"></a>01797 <span class="keyword"> else if(size_control == `SIZE_1) size <= ( ir[7:6] == 2'b00 ) ? 2'b01 : 2'b10;</span>
|
<a name="l01797"></a>01797 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a87fed6b8d7f55252c49ab2fc43d39d9a">ea_reg_control</a> == <a class="code" href="ao68000_8v.html#a56f29ecaaf69843219c88d8e0f252048">`EA_REG_IR_11_9</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a69652ae311e16ddcb1bb0dbc90744156">ea_reg</a> <= <span class="vhdlchar">ir</span>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>];
|
<a name="l01798"></a>01798 <span class="keyword"> else if(size_control == `SIZE_1_PLUS) size <= ( ir[7:6] == 2'b10 ) ? 2'b01 : 2'b10;</span>
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<a name="l01798"></a>01798 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a87fed6b8d7f55252c49ab2fc43d39d9a">ea_reg_control</a> == <a class="code" href="ao68000_8v.html#af2b8ce7c793c79dee8394ad309a1ef71">`EA_REG_MOVEM_REG_2_0</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a69652ae311e16ddcb1bb0dbc90744156">ea_reg</a> <= <span class="vhdlchar">movem_modreg</span>[<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>];
|
<a name="l01799"></a>01799 <span class="keyword"> else if(size_control == `SIZE_2) size <= ( ir[6] == 1'b0 ) ? 2'b01 : 2'b10;</span>
|
<a name="l01799"></a>01799 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a87fed6b8d7f55252c49ab2fc43d39d9a">ea_reg_control</a> == <a class="code" href="ao68000_8v.html#aa5ef414e1c0f769a38cdd8b3aeef5184">`EA_REG_3b111</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a69652ae311e16ddcb1bb0dbc90744156">ea_reg</a> <= <span class="vhdllogic">3'b111</span>;
|
<a name="l01800"></a>01800 <span class="keyword"> else if(size_control == `SIZE_3) size <= ( ir[7:6] == 2'b00 ) ? 2'b00 : ( ( ir[7:6] == 2'b01 ) ? 2'b01 : 2'b10 );</span>
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<a name="l01800"></a>01800 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a87fed6b8d7f55252c49ab2fc43d39d9a">ea_reg_control</a> == <a class="code" href="ao68000_8v.html#ab4936576a8613273a6487d2b78812c55">`EA_REG_3b100</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a69652ae311e16ddcb1bb0dbc90744156">ea_reg</a> <= <span class="vhdllogic">3'b100</span>;
|
<a name="l01801"></a>01801 <span class="keyword"> else if(size_control == `SIZE_4) size <= ( ir[13:12] == 2'b01 ) ? 2'b00 : ( ( ir[13:12] == 2'b11 ) ? 2'b01 : 2'b10 );</span>
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<a name="l01801"></a>01801 <span class="vhdlkeyword">end</span>
|
<a name="l01802"></a>01802 <span class="keyword"> else if(size_control == `SIZE_5) size <= ( ir[8] == 1'b0 ) ? 2'b01 : 2'b10;</span>
|
<a name="l01802"></a>01802
|
<a name="l01803"></a>01803 <span class="keyword"> else if(size_control == `SIZE_6) size <= ( ir[5:3] != 3'b000 ) ? 2'b00 : 2'b10;</span>
|
<a name="l01803"></a><a class="code" href="classregisters.html#a6fc98500064486297076cc7c8e99e16f">01803</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l01804"></a>01804 <span class="keyword"><span class="vhdlkeyword">end</span></span>
|
<a name="l01804"></a>01804 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a> <= <span class="vhdllogic">3'b000</span>;
|
<a name="l01805"></a>01805 <span class="keyword">*/</span>
|
<a name="l01805"></a>01805 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#ab630b141208b16db686f800d53dc41eb">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#a0c094175d5b6718611708b08af5e6342">`EA_MOD_IR_5_3</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a> <= <span class="vhdlchar">ir</span>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>];
|
<a name="l01806"></a>01806
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<a name="l01806"></a>01806 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#ab630b141208b16db686f800d53dc41eb">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#a45b520ba3dd813510ddca0ebe0a652f4">`EA_MOD_MOVEM_MOD_5_3</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a> <= <span class="vhdlchar">movem_modreg</span>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>];
|
<a name="l01807"></a><a class="code" href="classregisters.html#a098bb8c5f886c173a49d1e015dd37289">01807</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l01807"></a>01807 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#ab630b141208b16db686f800d53dc41eb">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#a46d304e545e3f136f9bc7fe83ffe61df">`EA_MOD_IR_8_6</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a> <= <span class="vhdlchar">ir</span>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>];
|
<a name="l01808"></a>01808 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <a class="code" href="classregisters.html#a69652ae311e16ddcb1bb0dbc90744156">ea_reg</a> <= <span class="vhdllogic">3'b000</span>;
|
<a name="l01808"></a>01808 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#ab630b141208b16db686f800d53dc41eb">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#a2e15ad20aa0f28ef9042982260a21316">`EA_MOD_PREDEC</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a> <= <span class="vhdllogic">3'b100</span>;
|
<a name="l01809"></a>01809 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a87fed6b8d7f55252c49ab2fc43d39d9a">ea_reg_control</a> == <a class="code" href="ao68000_8v.html#ab608c5385657295b902b8ffc21c43d03">`EA_REG_IR_2_0</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a69652ae311e16ddcb1bb0dbc90744156">ea_reg</a> <= <span class="vhdlchar">ir</span>[<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>];
|
<a name="l01809"></a>01809 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#ab630b141208b16db686f800d53dc41eb">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#ae4ecbd320f11539d132c8e6aa3fdcb5c">`EA_MOD_3b111</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a> <= <span class="vhdllogic">3'b111</span>;
|
<a name="l01810"></a>01810 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a87fed6b8d7f55252c49ab2fc43d39d9a">ea_reg_control</a> == <a class="code" href="ao68000_8v.html#a56f29ecaaf69843219c88d8e0f252048">`EA_REG_IR_11_9</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a69652ae311e16ddcb1bb0dbc90744156">ea_reg</a> <= <span class="vhdlchar">ir</span>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>];
|
<a name="l01810"></a>01810 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#ab630b141208b16db686f800d53dc41eb">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#aee18d2c3a30bdec23a7de0889deb0d94">`EA_MOD_DN_PREDEC</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a> <= (<span class="vhdlchar">ir</span>[<span class="vhdllogic">3</span>] == <span class="vhdllogic">1'b0</span>) ? <span class="keyword">/* Dn **/</span> <span class="vhdllogic">3'b000</span> : <span class="keyword">/* -(An) **/</span> <span class="vhdllogic">3'b100</span>;
|
<a name="l01811"></a>01811 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a87fed6b8d7f55252c49ab2fc43d39d9a">ea_reg_control</a> == <a class="code" href="ao68000_8v.html#af2b8ce7c793c79dee8394ad309a1ef71">`EA_REG_MOVEM_REG_2_0</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a69652ae311e16ddcb1bb0dbc90744156">ea_reg</a> <= <span class="vhdlchar">movem_modreg</span>[<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>];
|
<a name="l01811"></a>01811 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#ab630b141208b16db686f800d53dc41eb">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#ac190b9646213ddb87ec06a5858d479b3">`EA_MOD_DN_AN_EXG</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a> <= (<span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">5'b01000</span> || <span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">5'b10001</span>) ? <span class="keyword">/* Dn **/</span> <span class="vhdllogic">3'b000</span> : <span class="keyword">/* An **/</span> <span class="vhdllogic">3'b001</span>;
|
<a name="l01812"></a>01812 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a87fed6b8d7f55252c49ab2fc43d39d9a">ea_reg_control</a> == <a class="code" href="ao68000_8v.html#aa5ef414e1c0f769a38cdd8b3aeef5184">`EA_REG_3b111</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a69652ae311e16ddcb1bb0dbc90744156">ea_reg</a> <= <span class="vhdllogic">3'b111</span>;
|
<a name="l01812"></a>01812 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#ab630b141208b16db686f800d53dc41eb">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#a51a36024571aca1d7d7c7fa928956589">`EA_MOD_POSTINC</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a> <= <span class="vhdllogic">3'b011</span>;
|
<a name="l01813"></a>01813 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a87fed6b8d7f55252c49ab2fc43d39d9a">ea_reg_control</a> == <a class="code" href="ao68000_8v.html#ab4936576a8613273a6487d2b78812c55">`EA_REG_3b100</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a69652ae311e16ddcb1bb0dbc90744156">ea_reg</a> <= <span class="vhdllogic">3'b100</span>;
|
<a name="l01813"></a>01813 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#ab630b141208b16db686f800d53dc41eb">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#a7a6ccf87a21e66605e4672e95a6578e4">`EA_MOD_AN</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a> <= <span class="vhdllogic">3'b001</span>;
|
<a name="l01814"></a>01814 <span class="vhdlkeyword">end</span>
|
<a name="l01814"></a>01814 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#ab630b141208b16db686f800d53dc41eb">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#a8a000a242ea6cc51ac97ec35753faf7b">`EA_MOD_DN</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a> <= <span class="vhdllogic">3'b000</span>;
|
<a name="l01815"></a>01815
|
<a name="l01815"></a>01815 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#ab630b141208b16db686f800d53dc41eb">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#a88ded717145b6f89a3cd3416577225f0">`EA_MOD_INDIRECTOFFSET</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a> <= <span class="vhdllogic">3'b101</span>;
|
<a name="l01816"></a><a class="code" href="classregisters.html#a6fc98500064486297076cc7c8e99e16f">01816</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l01816"></a>01816 <span class="vhdlkeyword">end</span>
|
<a name="l01817"></a>01817 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a> <= <span class="vhdllogic">3'b000</span>;
|
<a name="l01817"></a>01817
|
<a name="l01818"></a>01818 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#ab630b141208b16db686f800d53dc41eb">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#a0c094175d5b6718611708b08af5e6342">`EA_MOD_IR_5_3</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a> <= <span class="vhdlchar">ir</span>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>];
|
<a name="l01818"></a><a class="code" href="classregisters.html#aa536be1ed88148e7c828c0183e8a0757">01818</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l01819"></a>01819 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#ab630b141208b16db686f800d53dc41eb">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#a45b520ba3dd813510ddca0ebe0a652f4">`EA_MOD_MOVEM_MOD_5_3</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a> <= <span class="vhdlchar">movem_modreg</span>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>];
|
<a name="l01819"></a>01819 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <a class="code" href="classregisters.html#a531a4ea89d5bde45780adeeda7d42bb4">ea_type</a> <= <a class="code" href="ao68000_8v.html#a30b69aee8fb5af4ab38fc9f0d92a28d3">`EA_TYPE_IDLE</a><span class="vhdlchar"></span>;
|
<a name="l01820"></a>01820 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#ab630b141208b16db686f800d53dc41eb">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#a46d304e545e3f136f9bc7fe83ffe61df">`EA_MOD_IR_8_6</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a> <= <span class="vhdlchar">ir</span>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>];
|
<a name="l01820"></a>01820 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a6fe315cf4e9805733719db71cf630847">ea_type_control</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a531a4ea89d5bde45780adeeda7d42bb4">ea_type</a> <= <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span>;
|
<a name="l01821"></a>01821 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#ab630b141208b16db686f800d53dc41eb">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#a2e15ad20aa0f28ef9042982260a21316">`EA_MOD_PREDEC</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a> <= <span class="vhdllogic">3'b100</span>;
|
<a name="l01821"></a>01821 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a6fe315cf4e9805733719db71cf630847">ea_type_control</a> == <a class="code" href="ao68000_8v.html#a925f0004ba49b82dbdf7c4ae969ba6ed">`EA_TYPE_CONTROL_POSTINC</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a531a4ea89d5bde45780adeeda7d42bb4">ea_type</a> <= <a class="code" href="ao68000_8v.html#a925f0004ba49b82dbdf7c4ae969ba6ed">`EA_TYPE_CONTROL_POSTINC</a><span class="vhdlchar"></span>;
|
<a name="l01822"></a>01822 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#ab630b141208b16db686f800d53dc41eb">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#ae4ecbd320f11539d132c8e6aa3fdcb5c">`EA_MOD_3b111</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a> <= <span class="vhdllogic">3'b111</span>;
|
<a name="l01822"></a>01822 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a6fe315cf4e9805733719db71cf630847">ea_type_control</a> == <a class="code" href="ao68000_8v.html#a41499eaa1b7aa62f455a07e5435d754a">`EA_TYPE_CONTROLALTER_PREDEC</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a531a4ea89d5bde45780adeeda7d42bb4">ea_type</a> <= <a class="code" href="ao68000_8v.html#a41499eaa1b7aa62f455a07e5435d754a">`EA_TYPE_CONTROLALTER_PREDEC</a><span class="vhdlchar"></span>;
|
<a name="l01823"></a>01823 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#ab630b141208b16db686f800d53dc41eb">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#aee18d2c3a30bdec23a7de0889deb0d94">`EA_MOD_DN_PREDEC</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a> <= (<span class="vhdlchar">ir</span>[<span class="vhdllogic">3</span>] == <span class="vhdllogic">1'b0</span>) ? <span class="keyword">/* Dn **/</span> <span class="vhdllogic">3'b000</span> : <span class="keyword">/* -(An) **/</span> <span class="vhdllogic">3'b100</span>;
|
<a name="l01823"></a>01823 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a6fe315cf4e9805733719db71cf630847">ea_type_control</a> == <a class="code" href="ao68000_8v.html#ae2c794f81236993a23138cbf3f7eda44">`EA_TYPE_CONTROL</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a531a4ea89d5bde45780adeeda7d42bb4">ea_type</a> <= <a class="code" href="ao68000_8v.html#ae2c794f81236993a23138cbf3f7eda44">`EA_TYPE_CONTROL</a><span class="vhdlchar"></span>;
|
<a name="l01824"></a>01824 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#ab630b141208b16db686f800d53dc41eb">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#ac190b9646213ddb87ec06a5858d479b3">`EA_MOD_DN_AN_EXG</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a> <= (<span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">5'b01000</span> || <span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">5'b10001</span>) ? <span class="keyword">/* Dn **/</span> <span class="vhdllogic">3'b000</span> : <span class="keyword">/* An **/</span> <span class="vhdllogic">3'b001</span>;
|
<a name="l01824"></a>01824 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a6fe315cf4e9805733719db71cf630847">ea_type_control</a> == <a class="code" href="ao68000_8v.html#a17a8a468ddfc3bdb178081a368f4dd6c">`EA_TYPE_DATAALTER</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a531a4ea89d5bde45780adeeda7d42bb4">ea_type</a> <= <a class="code" href="ao68000_8v.html#a17a8a468ddfc3bdb178081a368f4dd6c">`EA_TYPE_DATAALTER</a><span class="vhdlchar"></span>;
|
<a name="l01825"></a>01825 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#ab630b141208b16db686f800d53dc41eb">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#a51a36024571aca1d7d7c7fa928956589">`EA_MOD_POSTINC</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a> <= <span class="vhdllogic">3'b011</span>;
|
<a name="l01825"></a>01825 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a6fe315cf4e9805733719db71cf630847">ea_type_control</a> == <a class="code" href="ao68000_8v.html#a8e7bc745d4def25f5a995a6955dbdb4b">`EA_TYPE_DN_AN</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a531a4ea89d5bde45780adeeda7d42bb4">ea_type</a> <= <a class="code" href="ao68000_8v.html#a8e7bc745d4def25f5a995a6955dbdb4b">`EA_TYPE_DN_AN</a><span class="vhdlchar"></span>;
|
<a name="l01826"></a>01826 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#ab630b141208b16db686f800d53dc41eb">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#a7a6ccf87a21e66605e4672e95a6578e4">`EA_MOD_AN</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a> <= <span class="vhdllogic">3'b001</span>;
|
<a name="l01826"></a>01826 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a6fe315cf4e9805733719db71cf630847">ea_type_control</a> == <a class="code" href="ao68000_8v.html#a653530f090b85ba7bcd93912b8834412">`EA_TYPE_MEMORYALTER</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a531a4ea89d5bde45780adeeda7d42bb4">ea_type</a> <= <a class="code" href="ao68000_8v.html#a653530f090b85ba7bcd93912b8834412">`EA_TYPE_MEMORYALTER</a><span class="vhdlchar"></span>;
|
<a name="l01827"></a>01827 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#ab630b141208b16db686f800d53dc41eb">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#a8a000a242ea6cc51ac97ec35753faf7b">`EA_MOD_DN</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a> <= <span class="vhdllogic">3'b000</span>;
|
<a name="l01827"></a>01827 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a6fe315cf4e9805733719db71cf630847">ea_type_control</a> == <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a531a4ea89d5bde45780adeeda7d42bb4">ea_type</a> <= <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>;
|
<a name="l01828"></a>01828 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#ab630b141208b16db686f800d53dc41eb">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#a88ded717145b6f89a3cd3416577225f0">`EA_MOD_INDIRECTOFFSET</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a> <= <span class="vhdllogic">3'b101</span>;
|
<a name="l01828"></a>01828 <span class="vhdlkeyword">end</span>
|
<a name="l01829"></a>01829 <span class="vhdlkeyword">end</span>
|
<a name="l01829"></a>01829
|
<a name="l01830"></a>01830
|
<a name="l01830"></a><a class="code" href="classregisters.html#a8fa9503b229756474eafc4b087aa6511">01830</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l01831"></a><a class="code" href="classregisters.html#aa536be1ed88148e7c828c0183e8a0757">01831</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l01831"></a>01831 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <= <span class="vhdllogic">32'hFFFFFFFF</span>;
|
<a name="l01832"></a>01832 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <a class="code" href="classregisters.html#a531a4ea89d5bde45780adeeda7d42bb4">ea_type</a> <= <a class="code" href="ao68000_8v.html#a30b69aee8fb5af4ab38fc9f0d92a28d3">`EA_TYPE_IDLE</a><span class="vhdlchar"></span>;
|
<a name="l01832"></a>01832 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#a29e287eda5813f253f9f1cd527021533">`OP1_FROM_OP2</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <= <span class="vhdlchar">operand2</span>;
|
<a name="l01833"></a>01833 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a6fe315cf4e9805733719db71cf630847">ea_type_control</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a531a4ea89d5bde45780adeeda7d42bb4">ea_type</a> <= <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span>;
|
<a name="l01833"></a>01833 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#ab601cf0d52e5fe6ae155ab8084b236e1">`OP1_FROM_ADDRESS</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <= <span class="vhdlchar">address</span>;
|
<a name="l01834"></a>01834 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a6fe315cf4e9805733719db71cf630847">ea_type_control</a> == <a class="code" href="ao68000_8v.html#a925f0004ba49b82dbdf7c4ae969ba6ed">`EA_TYPE_CONTROL_POSTINC</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a531a4ea89d5bde45780adeeda7d42bb4">ea_type</a> <= <a class="code" href="ao68000_8v.html#a925f0004ba49b82dbdf7c4ae969ba6ed">`EA_TYPE_CONTROL_POSTINC</a><span class="vhdlchar"></span>;
|
<a name="l01834"></a>01834 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#aec7f41507eab6c659f5d544c942b441e">`OP1_FROM_DATA</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <=
|
<a name="l01835"></a>01835 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a6fe315cf4e9805733719db71cf630847">ea_type_control</a> == <a class="code" href="ao68000_8v.html#a41499eaa1b7aa62f455a07e5435d754a">`EA_TYPE_CONTROLALTER_PREDEC</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a531a4ea89d5bde45780adeeda7d42bb4">ea_type</a> <= <a class="code" href="ao68000_8v.html#a41499eaa1b7aa62f455a07e5435d754a">`EA_TYPE_CONTROLALTER_PREDEC</a><span class="vhdlchar"></span>;
|
<a name="l01835"></a>01835 (<span class="vhdlchar">size</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) ? { {<span class="vhdllogic">24</span>{<a class="code" href="classregisters.html#a015db9817045d85028931bbb036f7b59">data_read</a>[<span class="vhdllogic">7</span>]}}, <a class="code" href="classregisters.html#a015db9817045d85028931bbb036f7b59">data_read</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] } :
|
<a name="l01836"></a>01836 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a6fe315cf4e9805733719db71cf630847">ea_type_control</a> == <a class="code" href="ao68000_8v.html#ae2c794f81236993a23138cbf3f7eda44">`EA_TYPE_CONTROL</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a531a4ea89d5bde45780adeeda7d42bb4">ea_type</a> <= <a class="code" href="ao68000_8v.html#ae2c794f81236993a23138cbf3f7eda44">`EA_TYPE_CONTROL</a><span class="vhdlchar"></span>;
|
<a name="l01836"></a>01836 (<span class="vhdlchar">size</span>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) ? { {<span class="vhdllogic">16</span>{<a class="code" href="classregisters.html#a015db9817045d85028931bbb036f7b59">data_read</a>[<span class="vhdllogic">15</span>]}}, <a class="code" href="classregisters.html#a015db9817045d85028931bbb036f7b59">data_read</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] } :
|
<a name="l01837"></a>01837 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a6fe315cf4e9805733719db71cf630847">ea_type_control</a> == <a class="code" href="ao68000_8v.html#a17a8a468ddfc3bdb178081a368f4dd6c">`EA_TYPE_DATAALTER</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a531a4ea89d5bde45780adeeda7d42bb4">ea_type</a> <= <a class="code" href="ao68000_8v.html#a17a8a468ddfc3bdb178081a368f4dd6c">`EA_TYPE_DATAALTER</a><span class="vhdlchar"></span>;
|
<a name="l01837"></a>01837 <a class="code" href="classregisters.html#a015db9817045d85028931bbb036f7b59">data_read</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
<a name="l01838"></a>01838 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a6fe315cf4e9805733719db71cf630847">ea_type_control</a> == <a class="code" href="ao68000_8v.html#a8e7bc745d4def25f5a995a6955dbdb4b">`EA_TYPE_DN_AN</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a531a4ea89d5bde45780adeeda7d42bb4">ea_type</a> <= <a class="code" href="ao68000_8v.html#a8e7bc745d4def25f5a995a6955dbdb4b">`EA_TYPE_DN_AN</a><span class="vhdlchar"></span>;
|
<a name="l01838"></a>01838 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#abc0874c9141535c9c6a071653810c8fc">`OP1_FROM_IMMEDIATE</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <=
|
<a name="l01839"></a>01839 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a6fe315cf4e9805733719db71cf630847">ea_type_control</a> == <a class="code" href="ao68000_8v.html#a653530f090b85ba7bcd93912b8834412">`EA_TYPE_MEMORYALTER</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a531a4ea89d5bde45780adeeda7d42bb4">ea_type</a> <= <a class="code" href="ao68000_8v.html#a653530f090b85ba7bcd93912b8834412">`EA_TYPE_MEMORYALTER</a><span class="vhdlchar"></span>;
|
<a name="l01839"></a>01839 (<span class="vhdlchar">size</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) ? { {<span class="vhdllogic">24</span>{<a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">71</span>]}}, <a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">71</span>:<span class="vhdllogic">64</span>] } :
|
<a name="l01840"></a>01840 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a6fe315cf4e9805733719db71cf630847">ea_type_control</a> == <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a531a4ea89d5bde45780adeeda7d42bb4">ea_type</a> <= <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>;
|
<a name="l01840"></a>01840 (<span class="vhdlchar">size</span>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) ? { {<span class="vhdllogic">16</span>{<a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">79</span>]}}, <a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">79</span>:<span class="vhdllogic">64</span>] } :
|
<a name="l01841"></a>01841 <span class="vhdlkeyword">end</span>
|
<a name="l01841"></a>01841 <a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">79</span>:<span class="vhdllogic">48</span>];
|
<a name="l01842"></a>01842
|
<a name="l01842"></a>01842 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#a2adbf20e4776f4f5449563560fcfea3e">`OP1_FROM_RESULT</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <= <a class="code" href="classregisters.html#a81ed0f1a7f814e74696bea4db63f1e31">result</a>;
|
<a name="l01843"></a><a class="code" href="classregisters.html#a8fa9503b229756474eafc4b087aa6511">01843</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l01843"></a>01843 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#ac2bd7be96e464a7a06affeb71024f266">`OP1_MOVEQ</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <= { {<span class="vhdllogic">24</span>{<span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>]}}, <span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] };
|
<a name="l01844"></a>01844 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <= <span class="vhdllogic">32'hFFFFFFFF</span>;
|
<a name="l01844"></a>01844 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#aade66d4090f1aea9ed568a4e17ff1eae">`OP1_FROM_PC</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <= <a class="code" href="classregisters.html#a87b4409ca50b4ccad122fad79a9d6665">pc_valid</a>;
|
<a name="l01845"></a>01845 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#a29e287eda5813f253f9f1cd527021533">`OP1_FROM_OP2</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <= <span class="vhdlchar">operand2</span>;
|
<a name="l01845"></a>01845 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#a4db6f8d952dd7d7cfffeb0de4ad4a08b">`OP1_LOAD_ZEROS</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <= <span class="vhdllogic">32'b0</span>;
|
<a name="l01846"></a>01846 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#ab601cf0d52e5fe6ae155ab8084b236e1">`OP1_FROM_ADDRESS</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <= <span class="vhdlchar">address</span>;
|
<a name="l01846"></a>01846 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#ae8489ec12e458975d614347191ba2004">`OP1_LOAD_ONES</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <= <span class="vhdllogic">32'hFFFFFFFF</span>;
|
<a name="l01847"></a>01847 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#aec7f41507eab6c659f5d544c942b441e">`OP1_FROM_DATA</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <=
|
<a name="l01847"></a>01847 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#a9e1d49d77f5b144fff6cc8c0c021e5d2">`OP1_FROM_SR</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <= { <span class="vhdllogic">16'b0</span>, <a class="code" href="classregisters.html#ad583f99f893a13448ecd261e637ad56b">sr</a>[<span class="vhdllogic">15</span>], <span class="vhdllogic">1'b0</span>, <a class="code" href="classregisters.html#ad583f99f893a13448ecd261e637ad56b">sr</a>[<span class="vhdllogic">13</span>], <span class="vhdllogic">2'b0</span>, <a class="code" href="classregisters.html#ad583f99f893a13448ecd261e637ad56b">sr</a>[<span class="vhdllogic">10</span>:<span class="vhdllogic">8</span>], <span class="vhdllogic">3'b0</span>, <a class="code" href="classregisters.html#ad583f99f893a13448ecd261e637ad56b">sr</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">0</span>] };
|
<a name="l01848"></a>01848 (<span class="vhdlchar">size</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) ? { {<span class="vhdllogic">24</span>{<a class="code" href="classregisters.html#a015db9817045d85028931bbb036f7b59">data_read</a>[<span class="vhdllogic">7</span>]}}, <a class="code" href="classregisters.html#a015db9817045d85028931bbb036f7b59">data_read</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] } :
|
<a name="l01848"></a>01848 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#a1a44c33265ec779ad10e437621cda43b">`OP1_FROM_USP</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <= <a class="code" href="classregisters.html#ae8312cd504b37ae6dc199537ddf93bcb">usp</a>;
|
<a name="l01849"></a>01849 (<span class="vhdlchar">size</span>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) ? { {<span class="vhdllogic">16</span>{<a class="code" href="classregisters.html#a015db9817045d85028931bbb036f7b59">data_read</a>[<span class="vhdllogic">15</span>]}}, <a class="code" href="classregisters.html#a015db9817045d85028931bbb036f7b59">data_read</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] } :
|
<a name="l01849"></a>01849 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#a4900ac90de9fd53eaeb1acddf51a9008">`OP1_FROM_AN</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <=
|
<a name="l01850"></a>01850 <a class="code" href="classregisters.html#a015db9817045d85028931bbb036f7b59">data_read</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
<a name="l01850"></a>01850 (<span class="vhdlchar">size</span>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) ? { {<span class="vhdllogic">16</span>{<a class="code" href="classregisters.html#a4076832588fccdd9d5d0cc1b4b8dd0b0">An_output</a>[<span class="vhdllogic">15</span>]}}, <a class="code" href="classregisters.html#a4076832588fccdd9d5d0cc1b4b8dd0b0">An_output</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] } :
|
<a name="l01851"></a>01851 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#abc0874c9141535c9c6a071653810c8fc">`OP1_FROM_IMMEDIATE</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <=
|
<a name="l01851"></a>01851 <a class="code" href="classregisters.html#a4076832588fccdd9d5d0cc1b4b8dd0b0">An_output</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
<a name="l01852"></a>01852 (<span class="vhdlchar">size</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) ? { {<span class="vhdllogic">24</span>{<a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">71</span>]}}, <a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">71</span>:<span class="vhdllogic">64</span>] } :
|
<a name="l01852"></a>01852 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#a3aa722db3503e9370be36b3d409f3e17">`OP1_FROM_DN</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <=
|
<a name="l01853"></a>01853 (<span class="vhdlchar">size</span>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) ? { {<span class="vhdllogic">16</span>{<a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">79</span>]}}, <a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">79</span>:<span class="vhdllogic">64</span>] } :
|
<a name="l01853"></a>01853 (<span class="vhdlchar">size</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) ? { {<span class="vhdllogic">24</span>{<a class="code" href="classregisters.html#a0376be737f05fcad48a8057caa2f1fcf">Dn_output</a>[<span class="vhdllogic">7</span>]}}, <a class="code" href="classregisters.html#a0376be737f05fcad48a8057caa2f1fcf">Dn_output</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] } :
|
<a name="l01854"></a>01854 <a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">79</span>:<span class="vhdllogic">48</span>];
|
<a name="l01854"></a>01854 (<span class="vhdlchar">size</span>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) ? { {<span class="vhdllogic">16</span>{<a class="code" href="classregisters.html#a0376be737f05fcad48a8057caa2f1fcf">Dn_output</a>[<span class="vhdllogic">15</span>]}}, <a class="code" href="classregisters.html#a0376be737f05fcad48a8057caa2f1fcf">Dn_output</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] } :
|
<a name="l01855"></a>01855 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#a2adbf20e4776f4f5449563560fcfea3e">`OP1_FROM_RESULT</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <= <a class="code" href="classregisters.html#a81ed0f1a7f814e74696bea4db63f1e31">result</a>;
|
<a name="l01855"></a>01855 <a class="code" href="classregisters.html#a0376be737f05fcad48a8057caa2f1fcf">Dn_output</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
<a name="l01856"></a>01856 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#ac2bd7be96e464a7a06affeb71024f266">`OP1_MOVEQ</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <= { {<span class="vhdllogic">24</span>{<span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>]}}, <span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] };
|
<a name="l01856"></a>01856 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#a083db35259f035ab10f606d2c7dd82c6">`OP1_FROM_IR</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <= { <span class="vhdllogic">16'b0</span>, <span class="vhdlchar">ir</span>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] };
|
<a name="l01857"></a>01857 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#aade66d4090f1aea9ed568a4e17ff1eae">`OP1_FROM_PC</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <= <a class="code" href="classregisters.html#a87b4409ca50b4ccad122fad79a9d6665">pc_valid</a>;
|
<a name="l01857"></a>01857 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#a707f0ca7fa1a08446ba113ede9d5d8a4">`OP1_FROM_FAULT_ADDRESS</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <= <a class="code" href="classregisters.html#a2975efdebb48903a858f0558c58d31c2">fault_address_state</a>;
|
<a name="l01858"></a>01858 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#a4db6f8d952dd7d7cfffeb0de4ad4a08b">`OP1_LOAD_ZEROS</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <= <span class="vhdllogic">32'b0</span>;
|
<a name="l01858"></a>01858 <span class="vhdlkeyword">end</span>
|
<a name="l01859"></a>01859 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#ae8489ec12e458975d614347191ba2004">`OP1_LOAD_ONES</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <= <span class="vhdllogic">32'hFFFFFFFF</span>;
|
<a name="l01859"></a>01859
|
<a name="l01860"></a>01860 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#a9e1d49d77f5b144fff6cc8c0c021e5d2">`OP1_FROM_SR</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <= { <span class="vhdllogic">16'b0</span>, <a class="code" href="classregisters.html#ad583f99f893a13448ecd261e637ad56b">sr</a>[<span class="vhdllogic">15</span>], <span class="vhdllogic">1'b0</span>, <a class="code" href="classregisters.html#ad583f99f893a13448ecd261e637ad56b">sr</a>[<span class="vhdllogic">13</span>], <span class="vhdllogic">2'b0</span>, <a class="code" href="classregisters.html#ad583f99f893a13448ecd261e637ad56b">sr</a>[<span class="vhdllogic">10</span>:<span class="vhdllogic">8</span>], <span class="vhdllogic">3'b0</span>, <a class="code" href="classregisters.html#ad583f99f893a13448ecd261e637ad56b">sr</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">0</span>] };
|
<a name="l01860"></a><a class="code" href="classregisters.html#ae6143c84411ad159cbe1662f3909e726">01860</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l01861"></a>01861 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#a1a44c33265ec779ad10e437621cda43b">`OP1_FROM_USP</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <= <a class="code" href="classregisters.html#ae8312cd504b37ae6dc199537ddf93bcb">usp</a>;
|
<a name="l01861"></a>01861 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">operand2</span> <= <span class="vhdllogic">32'hFFFFFFFF</span>;
|
<a name="l01862"></a>01862 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#a4900ac90de9fd53eaeb1acddf51a9008">`OP1_FROM_AN</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <=
|
<a name="l01862"></a>01862 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand2_control</span> == <a class="code" href="ao68000_8v.html#a092ca695ecfa2de9e4d4a27bbd89d40f">`OP2_FROM_OP1</a><span class="vhdlchar"></span>) <span class="vhdlchar">operand2</span> <= <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a>;
|
<a name="l01863"></a>01863 (<span class="vhdlchar">size</span>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) ? { {<span class="vhdllogic">16</span>{<a class="code" href="classregisters.html#a4076832588fccdd9d5d0cc1b4b8dd0b0">An_output</a>[<span class="vhdllogic">15</span>]}}, <a class="code" href="classregisters.html#a4076832588fccdd9d5d0cc1b4b8dd0b0">An_output</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] } :
|
<a name="l01863"></a>01863 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand2_control</span> == <a class="code" href="ao68000_8v.html#a5c2c8ed577b6ab91a5ae3861643575e7">`OP2_LOAD_1</a><span class="vhdlchar"></span>) <span class="vhdlchar">operand2</span> <= <span class="vhdllogic">32'd1</span>;
|
<a name="l01864"></a>01864 <a class="code" href="classregisters.html#a4076832588fccdd9d5d0cc1b4b8dd0b0">An_output</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
<a name="l01864"></a>01864 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand2_control</span> == <a class="code" href="ao68000_8v.html#a7c904b70c2347aaee330105f74a69fc1">`OP2_LOAD_COUNT</a><span class="vhdlchar"></span>) <span class="vhdlchar">operand2</span> <=
|
<a name="l01865"></a>01865 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#a3aa722db3503e9370be36b3d409f3e17">`OP1_FROM_DN</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <=
|
<a name="l01865"></a>01865 (<span class="vhdlchar">ir</span>[<span class="vhdllogic">5</span>] == <span class="vhdllogic">1'b0</span>) ? ( (<span class="vhdlchar">ir</span>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">3'b000</span>) ? <span class="vhdllogic">32'b1000</span> : { <span class="vhdllogic">29'b0</span>, <span class="vhdlchar">ir</span>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] } ) :
|
<a name="l01866"></a>01866 (<span class="vhdlchar">size</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) ? { {<span class="vhdllogic">24</span>{<a class="code" href="classregisters.html#a0376be737f05fcad48a8057caa2f1fcf">Dn_output</a>[<span class="vhdllogic">7</span>]}}, <a class="code" href="classregisters.html#a0376be737f05fcad48a8057caa2f1fcf">Dn_output</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] } :
|
<a name="l01866"></a>01866 { <span class="vhdllogic">26'b0</span>, <span class="vhdlchar">operand2</span>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] };
|
<a name="l01867"></a>01867 (<span class="vhdlchar">size</span>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) ? { {<span class="vhdllogic">16</span>{<a class="code" href="classregisters.html#a0376be737f05fcad48a8057caa2f1fcf">Dn_output</a>[<span class="vhdllogic">15</span>]}}, <a class="code" href="classregisters.html#a0376be737f05fcad48a8057caa2f1fcf">Dn_output</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] } :
|
<a name="l01867"></a>01867 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand2_control</span> == <a class="code" href="ao68000_8v.html#aacec01f4da467eb6785c611710c1219d">`OP2_ADDQ_SUBQ</a><span class="vhdlchar"></span>) <span class="vhdlchar">operand2</span> <= (<span class="vhdlchar">ir</span>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">3'b000</span>) ? <span class="vhdllogic">32'b1000</span> : { <span class="vhdllogic">29'b0</span>, <span class="vhdlchar">ir</span>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] };
|
<a name="l01868"></a>01868 <a class="code" href="classregisters.html#a0376be737f05fcad48a8057caa2f1fcf">Dn_output</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
<a name="l01868"></a>01868 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand2_control</span> == <a class="code" href="ao68000_8v.html#ad8cdca7f0cbac16e09b4e1a1e3ab4f11">`OP2_MOVE_OFFSET</a><span class="vhdlchar"></span>) <span class="vhdlchar">operand2</span> <= (<span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">8'b0</span>) ? <span class="vhdlchar">operand2</span>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] : { {<span class="vhdllogic">24</span>{<span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>]}}, <span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] };
|
<a name="l01869"></a>01869 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#a083db35259f035ab10f606d2c7dd82c6">`OP1_FROM_IR</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <= { <span class="vhdllogic">16'b0</span>, <span class="vhdlchar">ir</span>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] };
|
<a name="l01869"></a>01869 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand2_control</span> == <a class="code" href="ao68000_8v.html#a041be53a35bc1a415713d34c839c81c5">`OP2_MOVE_ADDRESS_BUS_INFO</a><span class="vhdlchar"></span>) <span class="vhdlchar">operand2</span> <= { <span class="vhdllogic">16'b0</span>, <span class="vhdllogic">11'b0</span>, <a class="code" href="classregisters.html#a881b6927205941e0691b73906a7cfdd9">rw_state</a>, <span class="vhdlchar">instruction_flag</span>, <a class="code" href="classregisters.html#af336bd0ea96aad806fdb36dcd673a9c2">fc_state</a>};
|
<a name="l01870"></a>01870 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#a707f0ca7fa1a08446ba113ede9d5d8a4">`OP1_FROM_FAULT_ADDRESS</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <= <a class="code" href="classregisters.html#a2975efdebb48903a858f0558c58d31c2">fault_address_state</a>;
|
<a name="l01870"></a>01870 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand2_control</span> == <a class="code" href="ao68000_8v.html#a81d303d3fcf43bd2ed3b99072571f816">`OP2_DECR_BY_1</a><span class="vhdlchar"></span>) <span class="vhdlchar">operand2</span> <= <span class="vhdlchar">operand2</span> - <span class="vhdllogic">32'b1</span>;
|
<a name="l01871"></a>01871 <span class="vhdlkeyword">end</span>
|
<a name="l01871"></a>01871 <span class="vhdlkeyword">end</span>
|
<a name="l01872"></a>01872
|
<a name="l01872"></a>01872
|
<a name="l01873"></a><a class="code" href="classregisters.html#ae6143c84411ad159cbe1662f3909e726">01873</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l01873"></a><a class="code" href="classregisters.html#ae04888e60d745f9f64ca5c52d0969adb">01873</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l01874"></a>01874 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">operand2</span> <= <span class="vhdllogic">32'hFFFFFFFF</span>;
|
<a name="l01874"></a>01874 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">address</span> <= <span class="vhdllogic">32'b0</span>;
|
<a name="l01875"></a>01875 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand2_control</span> == <a class="code" href="ao68000_8v.html#a092ca695ecfa2de9e4d4a27bbd89d40f">`OP2_FROM_OP1</a><span class="vhdlchar"></span>) <span class="vhdlchar">operand2</span> <= <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a>;
|
<a name="l01875"></a>01875 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> == <a class="code" href="ao68000_8v.html#a864e0b06304816dec2d4658503d97495">`ADDRESS_INCR_BY_SIZE</a><span class="vhdlchar"></span>) <span class="vhdlchar">address</span> <= ((<span class="vhdlchar">size</span>[<span class="vhdllogic">0</span>]) && <a class="code" href="classregisters.html#a69652ae311e16ddcb1bb0dbc90744156">ea_reg</a> == <span class="vhdllogic">3'b111</span>) ? <span class="vhdlchar">address</span> + <span class="vhdllogic">32'd2</span> : <span class="vhdlchar">address</span> + {<span class="vhdllogic">29'd0</span>,<span class="vhdlchar">size</span>};
|
<a name="l01876"></a>01876 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand2_control</span> == <a class="code" href="ao68000_8v.html#a5c2c8ed577b6ab91a5ae3861643575e7">`OP2_LOAD_1</a><span class="vhdlchar"></span>) <span class="vhdlchar">operand2</span> <= <span class="vhdllogic">32'd1</span>;
|
<a name="l01876"></a>01876 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> == <a class="code" href="ao68000_8v.html#aa479827c57933eb9ff03788bbe9d6e3a">`ADDRESS_DECR_BY_SIZE</a><span class="vhdlchar"></span>) <span class="vhdlchar">address</span> <= ((<span class="vhdlchar">size</span>[<span class="vhdllogic">0</span>]) && <a class="code" href="classregisters.html#a69652ae311e16ddcb1bb0dbc90744156">ea_reg</a> == <span class="vhdllogic">3'b111</span>) ? <span class="vhdlchar">address</span> - <span class="vhdllogic">32'd2</span> : <span class="vhdlchar">address</span> - {<span class="vhdllogic">29'd0</span>,<span class="vhdlchar">size</span>};
|
<a name="l01877"></a>01877 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand2_control</span> == <a class="code" href="ao68000_8v.html#a7c904b70c2347aaee330105f74a69fc1">`OP2_LOAD_COUNT</a><span class="vhdlchar"></span>) <span class="vhdlchar">operand2</span> <=
|
<a name="l01877"></a>01877 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> == <a class="code" href="ao68000_8v.html#ac4044068e496c3393c6336b72873a958">`ADDRESS_INCR_BY_2</a><span class="vhdlchar"></span>) <span class="vhdlchar">address</span> <= <span class="vhdlchar">address</span> + <span class="vhdllogic">32'd2</span>;
|
<a name="l01878"></a>01878 (<span class="vhdlchar">ir</span>[<span class="vhdllogic">5</span>] == <span class="vhdllogic">1'b0</span>) ? ( (<span class="vhdlchar">ir</span>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">3'b000</span>) ? <span class="vhdllogic">32'b1000</span> : { <span class="vhdllogic">29'b0</span>, <span class="vhdlchar">ir</span>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] } ) :
|
<a name="l01878"></a>01878 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> == <a class="code" href="ao68000_8v.html#afc15ad5da6b4afd71eb879476c603fe3">`ADDRESS_FROM_AN_OUTPUT</a><span class="vhdlchar"></span>) <span class="vhdlchar">address</span> <= <a class="code" href="classregisters.html#a4076832588fccdd9d5d0cc1b4b8dd0b0">An_output</a>;
|
<a name="l01879"></a>01879 { <span class="vhdllogic">26'b0</span>, <span class="vhdlchar">operand2</span>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] };
|
<a name="l01879"></a>01879 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> == <a class="code" href="ao68000_8v.html#ac1143ff5a059fc5609c9419fcd402ae1">`ADDRESS_FROM_BASE_INDEX_OFFSET</a><span class="vhdlchar"></span>) <span class="vhdlchar">address</span> <= <span class="vhdlchar">address</span> + <span class="vhdlchar">index</span> + <span class="vhdlchar">offset</span>;
|
<a name="l01880"></a>01880 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand2_control</span> == <a class="code" href="ao68000_8v.html#aacec01f4da467eb6785c611710c1219d">`OP2_ADDQ_SUBQ</a><span class="vhdlchar"></span>) <span class="vhdlchar">operand2</span> <= (<span class="vhdlchar">ir</span>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">3'b000</span>) ? <span class="vhdllogic">32'b1000</span> : { <span class="vhdllogic">29'b0</span>, <span class="vhdlchar">ir</span>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] };
|
<a name="l01880"></a>01880 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> == <a class="code" href="ao68000_8v.html#aa6ba908e680fe87e46ac1cf014eed463">`ADDRESS_FROM_IMM_16</a><span class="vhdlchar"></span>) <span class="vhdlchar">address</span> <= { {<span class="vhdllogic">16</span>{<a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">79</span>]}}, <a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">79</span>:<span class="vhdllogic">64</span>] };
|
<a name="l01881"></a>01881 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand2_control</span> == <a class="code" href="ao68000_8v.html#ad8cdca7f0cbac16e09b4e1a1e3ab4f11">`OP2_MOVE_OFFSET</a><span class="vhdlchar"></span>) <span class="vhdlchar">operand2</span> <= (<span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">8'b0</span>) ? <span class="vhdlchar">operand2</span>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] : { {<span class="vhdllogic">24</span>{<span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>]}}, <span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] };
|
<a name="l01881"></a>01881 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> == <a class="code" href="ao68000_8v.html#aa688332c940cad3a10561a5c9f74698a">`ADDRESS_FROM_IMM_32</a><span class="vhdlchar"></span>) <span class="vhdlchar">address</span> <= <a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">79</span>:<span class="vhdllogic">48</span>];
|
<a name="l01882"></a>01882 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand2_control</span> == <a class="code" href="ao68000_8v.html#a041be53a35bc1a415713d34c839c81c5">`OP2_MOVE_ADDRESS_BUS_INFO</a><span class="vhdlchar"></span>) <span class="vhdlchar">operand2</span> <= { <span class="vhdllogic">16'b0</span>, <span class="vhdllogic">11'b0</span>, <a class="code" href="classregisters.html#a881b6927205941e0691b73906a7cfdd9">rw_state</a>, <span class="vhdlchar">instruction_flag</span>, <a class="code" href="classregisters.html#af336bd0ea96aad806fdb36dcd673a9c2">fc_state</a>};
|
<a name="l01882"></a>01882 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> == <a class="code" href="ao68000_8v.html#aa7a6ef5c21bbbf8a3c5a0437bdda3c85">`ADDRESS_FROM_PC_INDEX_OFFSET</a><span class="vhdlchar"></span>) <span class="vhdlchar">address</span> <= <a class="code" href="classregisters.html#a87b4409ca50b4ccad122fad79a9d6665">pc_valid</a> + <span class="vhdlchar">index</span> + <span class="vhdlchar">offset</span>;
|
<a name="l01883"></a>01883 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand2_control</span> == <a class="code" href="ao68000_8v.html#a81d303d3fcf43bd2ed3b99072571f816">`OP2_DECR_BY_1</a><span class="vhdlchar"></span>) <span class="vhdlchar">operand2</span> <= <span class="vhdlchar">operand2</span> - <span class="vhdllogic">32'b1</span>;
|
<a name="l01883"></a>01883 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> == <a class="code" href="ao68000_8v.html#a2a30a0ecfa48e96cc5be837e7db71cab">`ADDRESS_FROM_TRAP</a><span class="vhdlchar"></span>) <span class="vhdlchar">address</span> <= {<span class="vhdllogic">22'b0</span>, <span class="vhdlchar">trap</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>], <span class="vhdllogic">2'b0</span>};
|
<a name="l01884"></a>01884 <span class="vhdlkeyword">end</span>
|
<a name="l01884"></a>01884 <span class="vhdlkeyword">end</span>
|
<a name="l01885"></a>01885
|
<a name="l01885"></a>01885
|
<a name="l01886"></a><a class="code" href="classregisters.html#ae04888e60d745f9f64ca5c52d0969adb">01886</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l01886"></a><a class="code" href="classregisters.html#a7943ebd2393533b177f2cc9471614403">01886</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l01887"></a>01887 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">address</span> <= <span class="vhdllogic">32'b0</span>;
|
<a name="l01887"></a>01887 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">address_type</span> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l01888"></a>01888 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> == <a class="code" href="ao68000_8v.html#a864e0b06304816dec2d4658503d97495">`ADDRESS_INCR_BY_SIZE</a><span class="vhdlchar"></span>) <span class="vhdlchar">address</span> <= ((<span class="vhdlchar">size</span>[<span class="vhdllogic">0</span>]) && <a class="code" href="classregisters.html#a69652ae311e16ddcb1bb0dbc90744156">ea_reg</a> == <span class="vhdllogic">3'b111</span>) ? <span class="vhdlchar">address</span> + <span class="vhdllogic">32'd2</span> : <span class="vhdlchar">address</span> + {<span class="vhdllogic">29'd0</span>,<span class="vhdlchar">size</span>};
|
<a name="l01888"></a>01888 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> == <a class="code" href="ao68000_8v.html#aa7a6ef5c21bbbf8a3c5a0437bdda3c85">`ADDRESS_FROM_PC_INDEX_OFFSET</a><span class="vhdlchar"></span>) <span class="vhdlchar">address_type</span> <= <span class="vhdllogic">1'b1</span>;
|
<a name="l01889"></a>01889 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> == <a class="code" href="ao68000_8v.html#aa479827c57933eb9ff03788bbe9d6e3a">`ADDRESS_DECR_BY_SIZE</a><span class="vhdlchar"></span>) <span class="vhdlchar">address</span> <= ((<span class="vhdlchar">size</span>[<span class="vhdllogic">0</span>]) && <a class="code" href="classregisters.html#a69652ae311e16ddcb1bb0dbc90744156">ea_reg</a> == <span class="vhdllogic">3'b111</span>) ? <span class="vhdlchar">address</span> - <span class="vhdllogic">32'd2</span> : <span class="vhdlchar">address</span> - {<span class="vhdllogic">29'd0</span>,<span class="vhdlchar">size</span>};
|
<a name="l01889"></a>01889 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> != <a class="code" href="ao68000_8v.html#a3f7506465d358bddd4692916e422237d">`ADDRESS_IDLE</a><span class="vhdlchar"></span>) <span class="vhdlchar">address_type</span> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l01890"></a>01890 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> == <a class="code" href="ao68000_8v.html#ac4044068e496c3393c6336b72873a958">`ADDRESS_INCR_BY_2</a><span class="vhdlchar"></span>) <span class="vhdlchar">address</span> <= <span class="vhdlchar">address</span> + <span class="vhdllogic">32'd2</span>;
|
<a name="l01890"></a>01890 <span class="vhdlkeyword">end</span>
|
<a name="l01891"></a>01891 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> == <a class="code" href="ao68000_8v.html#afc15ad5da6b4afd71eb879476c603fe3">`ADDRESS_FROM_AN_OUTPUT</a><span class="vhdlchar"></span>) <span class="vhdlchar">address</span> <= <a class="code" href="classregisters.html#a4076832588fccdd9d5d0cc1b4b8dd0b0">An_output</a>;
|
<a name="l01891"></a>01891
|
<a name="l01892"></a>01892 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> == <a class="code" href="ao68000_8v.html#ac1143ff5a059fc5609c9419fcd402ae1">`ADDRESS_FROM_BASE_INDEX_OFFSET</a><span class="vhdlchar"></span>) <span class="vhdlchar">address</span> <= <span class="vhdlchar">address</span> + <span class="vhdlchar">index</span> + <span class="vhdlchar">offset</span>;
|
<a name="l01892"></a><a class="code" href="classregisters.html#a57a4884a23011ba445e6a69044c0b0bc">01892</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l01893"></a>01893 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> == <a class="code" href="ao68000_8v.html#aa6ba908e680fe87e46ac1cf014eed463">`ADDRESS_FROM_IMM_16</a><span class="vhdlchar"></span>) <span class="vhdlchar">address</span> <= { {<span class="vhdllogic">16</span>{<a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">79</span>]}}, <a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">79</span>:<span class="vhdllogic">64</span>] };
|
<a name="l01893"></a>01893 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">movem_modreg</span> <= <span class="vhdllogic">6'b0</span>;
|
<a name="l01894"></a>01894 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> == <a class="code" href="ao68000_8v.html#aa688332c940cad3a10561a5c9f74698a">`ADDRESS_FROM_IMM_32</a><span class="vhdlchar"></span>) <span class="vhdlchar">address</span> <= <a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">79</span>:<span class="vhdllogic">48</span>];
|
<a name="l01894"></a>01894 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">movem_modreg_control</span> == <a class="code" href="ao68000_8v.html#a59e6a074af6fbcf3490ecdb2d277e452">`MOVEM_MODREG_LOAD_0</a><span class="vhdlchar"></span>) <span class="vhdlchar">movem_modreg</span> <= <span class="vhdllogic">6'b0</span>;
|
<a name="l01895"></a>01895 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> == <a class="code" href="ao68000_8v.html#aa7a6ef5c21bbbf8a3c5a0437bdda3c85">`ADDRESS_FROM_PC_INDEX_OFFSET</a><span class="vhdlchar"></span>) <span class="vhdlchar">address</span> <= <a class="code" href="classregisters.html#a87b4409ca50b4ccad122fad79a9d6665">pc_valid</a> + <span class="vhdlchar">index</span> + <span class="vhdlchar">offset</span>;
|
<a name="l01895"></a>01895 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">movem_modreg_control</span> == <a class="code" href="ao68000_8v.html#a96857bc6f8514765cf6add0567891646">`MOVEM_MODREG_LOAD_6b001111</a><span class="vhdlchar"></span>)<span class="vhdlchar">movem_modreg</span> <= <span class="vhdllogic">6'b001111</span>;
|
<a name="l01896"></a>01896 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> == <a class="code" href="ao68000_8v.html#a2a30a0ecfa48e96cc5be837e7db71cab">`ADDRESS_FROM_TRAP</a><span class="vhdlchar"></span>) <span class="vhdlchar">address</span> <= {<span class="vhdllogic">22'b0</span>, <span class="vhdlchar">trap</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>], <span class="vhdllogic">2'b0</span>};
|
<a name="l01896"></a>01896 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">movem_modreg_control</span> == <a class="code" href="ao68000_8v.html#ab865a06c214356bb8906149ad6beebf2">`MOVEM_MODREG_INCR_BY_1</a><span class="vhdlchar"></span>) <span class="vhdlchar">movem_modreg</span> <= <span class="vhdlchar">movem_modreg</span> + <span class="vhdllogic">6'd1</span>;
|
<a name="l01897"></a>01897 <span class="vhdlkeyword">end</span>
|
<a name="l01897"></a>01897 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">movem_modreg_control</span> == <a class="code" href="ao68000_8v.html#afc15f893a792d1af5e5c90f8ed788662">`MOVEM_MODREG_DECR_BY_1</a><span class="vhdlchar"></span>) <span class="vhdlchar">movem_modreg</span> <= <span class="vhdlchar">movem_modreg</span> - <span class="vhdllogic">6'd1</span>;
|
<a name="l01898"></a>01898 <span class="keyword">/*OPTIM</span>
|
<a name="l01898"></a>01898 <span class="vhdlkeyword">end</span>
|
<a name="l01899"></a>01899 <span class="keyword"> else if(address_control == `ADDRESS_INCR_BY_SIZE) address <=</span>
|
<a name="l01899"></a>01899
|
<a name="l01900"></a>01900 <span class="keyword"> (size == 2'b00 && ea_reg != 3'b111) ? address + 32'd1 :</span>
|
<a name="l01900"></a><a class="code" href="classregisters.html#a84ce568fcbe169cc02a3dc5c5bdbced2">01900</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l01901"></a>01901 <span class="keyword"> (size == 2'b01 || (size == 2'b00 && ea_reg == 3'b111)) ? address + 32'd2 :</span>
|
<a name="l01901"></a>01901 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">movem_loop</span> <= <span class="vhdllogic">5'b0</span>;
|
<a name="l01902"></a>01902 <span class="keyword"> (size == 2'b10) ? address + 32'd4 :</span>
|
<a name="l01902"></a>01902 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">movem_loop_control</span> == <a class="code" href="ao68000_8v.html#a8465e4a24e72c1cb6e12015c4ff806c5">`MOVEM_LOOP_LOAD_0</a><span class="vhdlchar"></span>) <span class="vhdlchar">movem_loop</span> <= <span class="vhdllogic">5'b0</span>;
|
<a name="l01903"></a>01903 <span class="keyword"> address;</span>
|
<a name="l01903"></a>01903 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">movem_loop_control</span> == <a class="code" href="ao68000_8v.html#add999e8b65307d6d46547d776999f215">`MOVEM_LOOP_INCR_BY_1</a><span class="vhdlchar"></span>) <span class="vhdlchar">movem_loop</span> <= <span class="vhdlchar">movem_loop</span> + <span class="vhdllogic">5'd1</span>;
|
<a name="l01904"></a>01904 <span class="keyword"> else if(address_control == `ADDRESS_DECR_BY_SIZE) address <=</span>
|
<a name="l01904"></a>01904 <span class="vhdlkeyword">end</span>
|
<a name="l01905"></a>01905 <span class="keyword"> (size == 2'b00 && ea_reg != 3'b111) ? address - 32'd1 :</span>
|
<a name="l01905"></a>01905
|
<a name="l01906"></a>01906 <span class="keyword"> (size == 2'b01 || (size == 2'b00 && ea_reg == 3'b111)) ? address - 32'd2 :</span>
|
<a name="l01906"></a><a class="code" href="classregisters.html#a5ca9e5ee3853a6c58d80397ee08dcdfb">01906</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l01907"></a>01907 <span class="keyword"> (size == 2'b10) ? address - 32'd4 :</span>
|
<a name="l01907"></a>01907 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">movem_reg</span> <= <span class="vhdllogic">16'b0</span>;
|
<a name="l01908"></a>01908 <span class="keyword"> address;</span>
|
<a name="l01908"></a>01908 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">movem_reg_control</span> == <a class="code" href="ao68000_8v.html#aa7d78c26e9e37f761c7a0b178fe13cf8">`MOVEM_REG_FROM_OP1</a><span class="vhdlchar"></span>) <span class="vhdlchar">movem_reg</span> <= <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>];
|
<a name="l01909"></a>01909 <span class="keyword"> else if(address_control == `ADDRESS_INCR_BY_2) address <= address + 32'd2;</span>
|
<a name="l01909"></a>01909 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">movem_reg_control</span> == <a class="code" href="ao68000_8v.html#ac34150d75e16d155befcfcb8a95e45a3">`MOVEM_REG_SHIFT_RIGHT</a><span class="vhdlchar"></span>) <span class="vhdlchar">movem_reg</span> <= { <span class="vhdllogic">1'b0</span>, <span class="vhdlchar">movem_reg</span>[<span class="vhdllogic">15</span>:<span class="vhdllogic">1</span>] };
|
<a name="l01910"></a>01910 <span class="keyword"> else if(address_control == `ADDRESS_FROM_AN_OUTPUT) address <= An_output;</span>
|
<a name="l01910"></a>01910 <span class="vhdlkeyword">end</span>
|
<a name="l01911"></a>01911 <span class="keyword"> else if(address_control == `ADDRESS_FROM_BASE_INDEX_OFFSET) address <= address + index + offset;</span>
|
<a name="l01911"></a>01911
|
<a name="l01912"></a>01912 <span class="keyword"> else if(address_control == `ADDRESS_FROM_IMM_16) address <= { {16{prefetch_ir[79]}}, prefetch_ir[79:64] };</span>
|
<a name="l01912"></a><a class="code" href="classregisters.html#a670e4db98926f8ddddaa84356173ff1a">01912</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l01913"></a>01913 <span class="keyword"> else if(address_control == `ADDRESS_FROM_IMM_32) address <= prefetch_ir[79:48];</span>
|
<a name="l01913"></a>01913 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">ir</span> <= <span class="vhdllogic">16'b0</span>;
|
<a name="l01914"></a>01914 <span class="keyword"> else if(address_control == `ADDRESS_FROM_PC_INDEX_OFFSET) address <= pc_valid + index + offset;</span>
|
<a name="l01914"></a>01914 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">ir_control</span> == <a class="code" href="ao68000_8v.html#a987216cfc97019736d0251dcd5470e68">`IR_LOAD_WHEN_PREFETCH_VALID</a><span class="vhdlchar"></span> && <a class="code" href="classregisters.html#aabb30e872d04701c156a70c4e1e7a3ba">prefetch_ir_valid</a> == <span class="vhdllogic">1'b1</span> && <span class="vhdlchar">stop_flag</span> == <span class="vhdllogic">1'b0</span>)
|
<a name="l01915"></a>01915 <span class="keyword"> else if(address_control == `ADDRESS_FROM_TRAP) address <= {22'b0, trap[7:0], 2'b0};</span>
|
<a name="l01915"></a>01915 <span class="vhdlchar">ir</span> <= <a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">79</span>:<span class="vhdllogic">64</span>];
|
<a name="l01916"></a>01916 <span class="keyword"><span class="vhdlkeyword">end</span></span>
|
<a name="l01916"></a>01916 <span class="vhdlkeyword">end</span>
|
<a name="l01917"></a>01917 <span class="keyword">*/</span>
|
<a name="l01917"></a>01917
|
<a name="l01918"></a>01918
|
<a name="l01918"></a><a class="code" href="classregisters.html#a3a2e5a5ea0bbf7d06bee2afef1124393">01918</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l01919"></a><a class="code" href="classregisters.html#a7943ebd2393533b177f2cc9471614403">01919</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l01919"></a>01919 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">trap</span> <= <span class="vhdllogic">8'd0</span>;
|
<a name="l01920"></a>01920 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">address_type</span> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l01920"></a>01920 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">trap_control</span> == <a class="code" href="ao68000_8v.html#a4267c71337dc6963db47aba754396f48">`TRAP_ILLEGAL_INSTR</a><span class="vhdlchar"></span>) <span class="vhdlchar">trap</span> <= <span class="vhdllogic">8'd4</span>;
|
<a name="l01921"></a>01921 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> == <a class="code" href="ao68000_8v.html#aa7a6ef5c21bbbf8a3c5a0437bdda3c85">`ADDRESS_FROM_PC_INDEX_OFFSET</a><span class="vhdlchar"></span>) <span class="vhdlchar">address_type</span> <= <span class="vhdllogic">1'b1</span>;
|
<a name="l01921"></a>01921 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">trap_control</span> == <a class="code" href="ao68000_8v.html#a111476f2c18a4085c9a5cea3692dc990">`TRAP_DIV_BY_ZERO</a><span class="vhdlchar"></span>) <span class="vhdlchar">trap</span> <= <span class="vhdllogic">8'd5</span>;
|
<a name="l01922"></a>01922 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> != <a class="code" href="ao68000_8v.html#a3f7506465d358bddd4692916e422237d">`ADDRESS_IDLE</a><span class="vhdlchar"></span>) <span class="vhdlchar">address_type</span> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l01922"></a>01922 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">trap_control</span> == <a class="code" href="ao68000_8v.html#a7d97a1e77166d92c1d69452c3e836682">`TRAP_CHK</a><span class="vhdlchar"></span>) <span class="vhdlchar">trap</span> <= <span class="vhdllogic">8'd6</span>;
|
<a name="l01923"></a>01923 <span class="vhdlkeyword">end</span>
|
<a name="l01923"></a>01923 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">trap_control</span> == <a class="code" href="ao68000_8v.html#a66a7d33a63851daa49e101494acd6118">`TRAP_TRAPV</a><span class="vhdlchar"></span>) <span class="vhdlchar">trap</span> <= <span class="vhdllogic">8'd7</span>;
|
<a name="l01924"></a>01924
|
<a name="l01924"></a>01924 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">trap_control</span> == <a class="code" href="ao68000_8v.html#a940b41a2a1e4c585e15f1c2bef5d5c6f">`TRAP_PRIVIL_VIOLAT</a><span class="vhdlchar"></span>) <span class="vhdlchar">trap</span> <= <span class="vhdllogic">8'd8</span>;
|
<a name="l01925"></a><a class="code" href="classregisters.html#a57a4884a23011ba445e6a69044c0b0bc">01925</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l01925"></a>01925 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">trap_control</span> == <a class="code" href="ao68000_8v.html#a84705ced93a01047ec829b7ea942cee0">`TRAP_TRACE</a><span class="vhdlchar"></span>) <span class="vhdlchar">trap</span> <= <span class="vhdllogic">8'd9</span>;
|
<a name="l01926"></a>01926 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">movem_modreg</span> <= <span class="vhdllogic">6'b0</span>;
|
<a name="l01926"></a>01926 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">trap_control</span> == <a class="code" href="ao68000_8v.html#a4d09227bd9de91efc1a40bf676e10c72">`TRAP_TRAP</a><span class="vhdlchar"></span>) <span class="vhdlchar">trap</span> <= { <span class="vhdllogic">4'b0010</span>, <span class="vhdlchar">ir</span>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] };
|
<a name="l01927"></a>01927 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">movem_modreg_control</span> == <a class="code" href="ao68000_8v.html#a59e6a074af6fbcf3490ecdb2d277e452">`MOVEM_MODREG_LOAD_0</a><span class="vhdlchar"></span>) <span class="vhdlchar">movem_modreg</span> <= <span class="vhdllogic">6'b0</span>;
|
<a name="l01927"></a>01927 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">trap_control</span> == <a class="code" href="ao68000_8v.html#a8d6c015903e3a60339a6e8cc196bb440">`TRAP_FROM_DECODER</a><span class="vhdlchar"></span>) <span class="vhdlchar">trap</span> <= <a class="code" href="classregisters.html#a1444e3b474fdf49e5ab8a0283060ceab">decoder_trap</a>;
|
<a name="l01928"></a>01928 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">movem_modreg_control</span> == <a class="code" href="ao68000_8v.html#a96857bc6f8514765cf6add0567891646">`MOVEM_MODREG_LOAD_6b001111</a><span class="vhdlchar"></span>)<span class="vhdlchar">movem_modreg</span> <= <span class="vhdllogic">6'b001111</span>;
|
<a name="l01928"></a>01928 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">trap_control</span> == <a class="code" href="ao68000_8v.html#a57812c3cf3905152a60361ae979a4c2d">`TRAP_FROM_INTERRUPT</a><span class="vhdlchar"></span>) <span class="vhdlchar">trap</span> <= <a class="code" href="classregisters.html#ad7009ed104b0324325f2ebe297edc9b4">interrupt_trap</a>;
|
<a name="l01929"></a>01929 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">movem_modreg_control</span> == <a class="code" href="ao68000_8v.html#ab865a06c214356bb8906149ad6beebf2">`MOVEM_MODREG_INCR_BY_1</a><span class="vhdlchar"></span>) <span class="vhdlchar">movem_modreg</span> <= <span class="vhdlchar">movem_modreg</span> + <span class="vhdllogic">6'd1</span>;
|
<a name="l01929"></a>01929 <span class="vhdlkeyword">end</span>
|
<a name="l01930"></a>01930 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">movem_modreg_control</span> == <a class="code" href="ao68000_8v.html#afc15f893a792d1af5e5c90f8ed788662">`MOVEM_MODREG_DECR_BY_1</a><span class="vhdlchar"></span>) <span class="vhdlchar">movem_modreg</span> <= <span class="vhdlchar">movem_modreg</span> - <span class="vhdllogic">6'd1</span>;
|
<a name="l01930"></a>01930
|
<a name="l01931"></a>01931 <span class="vhdlkeyword">end</span>
|
<a name="l01931"></a><a class="code" href="classregisters.html#a931eb6b9c3c3c002a0eea00a7f10e10f">01931</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l01932"></a>01932
|
<a name="l01932"></a>01932 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">offset</span> <= <span class="vhdllogic">32'd0</span>;
|
<a name="l01933"></a><a class="code" href="classregisters.html#a84ce568fcbe169cc02a3dc5c5bdbced2">01933</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l01933"></a>01933 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">offset_control</span> == <a class="code" href="ao68000_8v.html#ad904ffb95a59f475e446877344adb415">`OFFSET_IMM_8</a><span class="vhdlchar"></span>) <span class="vhdlchar">offset</span> <= { {<span class="vhdllogic">24</span>{<a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">71</span>]}}, <a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">71</span>:<span class="vhdllogic">64</span>] };
|
<a name="l01934"></a>01934 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">movem_loop</span> <= <span class="vhdllogic">5'b0</span>;
|
<a name="l01934"></a>01934 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">offset_control</span> == <a class="code" href="ao68000_8v.html#a87c5da2d7633077683260709d88602e0">`OFFSET_IMM_16</a><span class="vhdlchar"></span>) <span class="vhdlchar">offset</span> <= { {<span class="vhdllogic">16</span>{<a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">79</span>]}}, <a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">79</span>:<span class="vhdllogic">64</span>] };
|
<a name="l01935"></a>01935 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">movem_loop_control</span> == <a class="code" href="ao68000_8v.html#a8465e4a24e72c1cb6e12015c4ff806c5">`MOVEM_LOOP_LOAD_0</a><span class="vhdlchar"></span>) <span class="vhdlchar">movem_loop</span> <= <span class="vhdllogic">5'b0</span>;
|
<a name="l01935"></a>01935 <span class="vhdlkeyword">end</span>
|
<a name="l01936"></a>01936 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">movem_loop_control</span> == <a class="code" href="ao68000_8v.html#add999e8b65307d6d46547d776999f215">`MOVEM_LOOP_INCR_BY_1</a><span class="vhdlchar"></span>) <span class="vhdlchar">movem_loop</span> <= <span class="vhdlchar">movem_loop</span> + <span class="vhdllogic">5'd1</span>;
|
<a name="l01936"></a>01936
|
<a name="l01937"></a>01937 <span class="vhdlkeyword">end</span>
|
<a name="l01937"></a><a class="code" href="classregisters.html#a2a04a4a12e64f1ffb3ec95095716fee7">01937</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l01938"></a>01938
|
<a name="l01938"></a>01938 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">index</span> <= <span class="vhdllogic">32'd0</span>;
|
<a name="l01939"></a><a class="code" href="classregisters.html#a5ca9e5ee3853a6c58d80397ee08dcdfb">01939</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l01939"></a>01939 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">index_control</span> == <a class="code" href="ao68000_8v.html#a1db54bd70d82cea2a77c6d5c823f04db">`INDEX_0</a><span class="vhdlchar"></span>) <span class="vhdlchar">index</span> <= <span class="vhdllogic">32'd0</span>;
|
<a name="l01940"></a>01940 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">movem_reg</span> <= <span class="vhdllogic">16'b0</span>;
|
<a name="l01940"></a>01940 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">index_control</span> == <a class="code" href="ao68000_8v.html#af05405b84ee28262882d3c7ac7a5a80c">`INDEX_LOAD_EXTENDED</a><span class="vhdlchar"></span>) <span class="vhdlchar">index</span> <=
|
<a name="l01941"></a>01941 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">movem_reg_control</span> == <a class="code" href="ao68000_8v.html#aa7d78c26e9e37f761c7a0b178fe13cf8">`MOVEM_REG_FROM_OP1</a><span class="vhdlchar"></span>) <span class="vhdlchar">movem_reg</span> <= <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>];
|
<a name="l01941"></a>01941 (<a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">79</span>] == <span class="vhdllogic">1'b0</span>) ?
|
<a name="l01942"></a>01942 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">movem_reg_control</span> == <a class="code" href="ao68000_8v.html#ac34150d75e16d155befcfcb8a95e45a3">`MOVEM_REG_SHIFT_RIGHT</a><span class="vhdlchar"></span>) <span class="vhdlchar">movem_reg</span> <= { <span class="vhdllogic">1'b0</span>, <span class="vhdlchar">movem_reg</span>[<span class="vhdllogic">15</span>:<span class="vhdllogic">1</span>] };
|
<a name="l01942"></a>01942 ( (<a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">75</span>] == <span class="vhdllogic">1'b0</span>) ?
|
<a name="l01943"></a>01943 <span class="vhdlkeyword">end</span>
|
<a name="l01943"></a>01943 { {<span class="vhdllogic">16</span>{<a class="code" href="classregisters.html#a0376be737f05fcad48a8057caa2f1fcf">Dn_output</a>[<span class="vhdllogic">15</span>]}}, <a class="code" href="classregisters.html#a0376be737f05fcad48a8057caa2f1fcf">Dn_output</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] } : <a class="code" href="classregisters.html#a0376be737f05fcad48a8057caa2f1fcf">Dn_output</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>]
|
<a name="l01944"></a>01944
|
<a name="l01944"></a>01944 ) :
|
<a name="l01945"></a><a class="code" href="classregisters.html#a670e4db98926f8ddddaa84356173ff1a">01945</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l01945"></a>01945 ( (<a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">75</span>] == <span class="vhdllogic">1'b0</span>) ?
|
<a name="l01946"></a>01946 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">ir</span> <= <span class="vhdllogic">16'b0</span>;
|
<a name="l01946"></a>01946 { {<span class="vhdllogic">16</span>{<a class="code" href="classregisters.html#a4076832588fccdd9d5d0cc1b4b8dd0b0">An_output</a>[<span class="vhdllogic">15</span>]}}, <a class="code" href="classregisters.html#a4076832588fccdd9d5d0cc1b4b8dd0b0">An_output</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] } : <a class="code" href="classregisters.html#a4076832588fccdd9d5d0cc1b4b8dd0b0">An_output</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>]
|
<a name="l01947"></a>01947 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">ir_control</span> == <a class="code" href="ao68000_8v.html#a987216cfc97019736d0251dcd5470e68">`IR_LOAD_WHEN_PREFETCH_VALID</a><span class="vhdlchar"></span> && <a class="code" href="classregisters.html#aabb30e872d04701c156a70c4e1e7a3ba">prefetch_ir_valid</a> == <span class="vhdllogic">1'b1</span> && <span class="vhdlchar">stop_flag</span> == <span class="vhdllogic">1'b0</span>)
|
<a name="l01947"></a>01947 );
|
<a name="l01948"></a>01948 <span class="vhdlchar">ir</span> <= <a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">79</span>:<span class="vhdllogic">64</span>];
|
<a name="l01948"></a>01948 <span class="vhdlkeyword">end</span>
|
<a name="l01949"></a>01949 <span class="vhdlkeyword">end</span>
|
<a name="l01949"></a>01949
|
<a name="l01950"></a>01950
|
<a name="l01950"></a><a class="code" href="classregisters.html#af284685eb0240e8fc444c84618b1af67">01950</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l01951"></a><a class="code" href="classregisters.html#a3a2e5a5ea0bbf7d06bee2afef1124393">01951</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l01951"></a>01951 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">stop_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l01952"></a>01952 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">trap</span> <= <span class="vhdllogic">8'd0</span>;
|
<a name="l01952"></a>01952 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">stop_flag_control</span> == <a class="code" href="ao68000_8v.html#a5131e7ee341cd6f2ea5350a89b19a488">`STOP_FLAG_SET</a><span class="vhdlchar"></span>) <span class="vhdlchar">stop_flag</span> <= <span class="vhdllogic">1'b1</span>;
|
<a name="l01953"></a>01953 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">trap_control</span> == <a class="code" href="ao68000_8v.html#a4267c71337dc6963db47aba754396f48">`TRAP_ILLEGAL_INSTR</a><span class="vhdlchar"></span>) <span class="vhdlchar">trap</span> <= <span class="vhdllogic">8'd4</span>;
|
<a name="l01953"></a>01953 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">stop_flag_control</span> == <a class="code" href="ao68000_8v.html#a0e63684fc863d639423c2d9f0f8e6cd9">`STOP_FLAG_CLEAR</a><span class="vhdlchar"></span>) <span class="vhdlchar">stop_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l01954"></a>01954 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">trap_control</span> == <a class="code" href="ao68000_8v.html#a111476f2c18a4085c9a5cea3692dc990">`TRAP_DIV_BY_ZERO</a><span class="vhdlchar"></span>) <span class="vhdlchar">trap</span> <= <span class="vhdllogic">8'd5</span>;
|
<a name="l01954"></a>01954 <span class="vhdlkeyword">end</span>
|
<a name="l01955"></a>01955 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">trap_control</span> == <a class="code" href="ao68000_8v.html#a7d97a1e77166d92c1d69452c3e836682">`TRAP_CHK</a><span class="vhdlchar"></span>) <span class="vhdlchar">trap</span> <= <span class="vhdllogic">8'd6</span>;
|
<a name="l01955"></a>01955
|
<a name="l01956"></a>01956 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">trap_control</span> == <a class="code" href="ao68000_8v.html#a66a7d33a63851daa49e101494acd6118">`TRAP_TRAPV</a><span class="vhdlchar"></span>) <span class="vhdlchar">trap</span> <= <span class="vhdllogic">8'd7</span>;
|
<a name="l01956"></a><a class="code" href="classregisters.html#a12d4c2e0121456bcb2b23e7444c1da06">01956</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l01957"></a>01957 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">trap_control</span> == <a class="code" href="ao68000_8v.html#a940b41a2a1e4c585e15f1c2bef5d5c6f">`TRAP_PRIVIL_VIOLAT</a><span class="vhdlchar"></span>) <span class="vhdlchar">trap</span> <= <span class="vhdllogic">8'd8</span>;
|
<a name="l01957"></a>01957 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">trace_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l01958"></a>01958 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">trap_control</span> == <a class="code" href="ao68000_8v.html#a84705ced93a01047ec829b7ea942cee0">`TRAP_TRACE</a><span class="vhdlchar"></span>) <span class="vhdlchar">trap</span> <= <span class="vhdllogic">8'd9</span>;
|
<a name="l01958"></a>01958 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">trace_flag_control</span> == <a class="code" href="ao68000_8v.html#a3cb5bcdd68537f527007213efe5c2d4f">`TRACE_FLAG_COPY_WHEN_NO_STOP</a><span class="vhdlchar"></span> && <a class="code" href="classregisters.html#aabb30e872d04701c156a70c4e1e7a3ba">prefetch_ir_valid</a> == <span class="vhdllogic">1'b1</span> && <a class="code" href="classregisters.html#a1444e3b474fdf49e5ab8a0283060ceab">decoder_trap</a> == <span class="vhdllogic">8'd0</span> && <span class="vhdlchar">stop_flag</span> == <span class="vhdllogic">1'b0</span>)
|
<a name="l01959"></a>01959 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">trap_control</span> == <a class="code" href="ao68000_8v.html#a4d09227bd9de91efc1a40bf676e10c72">`TRAP_TRAP</a><span class="vhdlchar"></span>) <span class="vhdlchar">trap</span> <= { <span class="vhdllogic">4'b0010</span>, <span class="vhdlchar">ir</span>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] };
|
<a name="l01959"></a>01959 <span class="vhdlchar">trace_flag</span> <= <a class="code" href="classregisters.html#ad583f99f893a13448ecd261e637ad56b">sr</a>[<span class="vhdllogic">15</span>];
|
<a name="l01960"></a>01960 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">trap_control</span> == <a class="code" href="ao68000_8v.html#a8d6c015903e3a60339a6e8cc196bb440">`TRAP_FROM_DECODER</a><span class="vhdlchar"></span>) <span class="vhdlchar">trap</span> <= <a class="code" href="classregisters.html#a1444e3b474fdf49e5ab8a0283060ceab">decoder_trap</a>;
|
<a name="l01960"></a>01960 <span class="vhdlkeyword">end</span>
|
<a name="l01961"></a>01961 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">trap_control</span> == <a class="code" href="ao68000_8v.html#a57812c3cf3905152a60361ae979a4c2d">`TRAP_FROM_INTERRUPT</a><span class="vhdlchar"></span>) <span class="vhdlchar">trap</span> <= <a class="code" href="classregisters.html#ad7009ed104b0324325f2ebe297edc9b4">interrupt_trap</a>;
|
<a name="l01961"></a>01961
|
<a name="l01962"></a>01962 <span class="vhdlkeyword">end</span>
|
<a name="l01962"></a><a class="code" href="classregisters.html#acf180186b03cdc0ad93be0efb7fa2815">01962</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l01963"></a>01963
|
<a name="l01963"></a>01963 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">group_0_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l01964"></a><a class="code" href="classregisters.html#a931eb6b9c3c3c002a0eea00a7f10e10f">01964</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l01964"></a>01964 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">group_0_flag_control</span> == <a class="code" href="ao68000_8v.html#a5333b31d43f3c7de70d3cad313720ef4">`GROUP_0_FLAG_SET</a><span class="vhdlchar"></span>) <span class="vhdlchar">group_0_flag</span> <= <span class="vhdllogic">1'b1</span>;
|
<a name="l01965"></a>01965 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">offset</span> <= <span class="vhdllogic">32'd0</span>;
|
<a name="l01965"></a>01965 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">group_0_flag_control</span> == <a class="code" href="ao68000_8v.html#a28adb393ace594d548dfe7f070fd837b">`GROUP_0_FLAG_CLEAR_WHEN_VALID_PREFETCH</a><span class="vhdlchar"></span> && <a class="code" href="classregisters.html#aabb30e872d04701c156a70c4e1e7a3ba">prefetch_ir_valid</a> == <span class="vhdllogic">1'b1</span> && <span class="vhdlchar">stop_flag</span> == <span class="vhdllogic">1'b0</span>)
|
<a name="l01966"></a>01966 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">offset_control</span> == <a class="code" href="ao68000_8v.html#ad904ffb95a59f475e446877344adb415">`OFFSET_IMM_8</a><span class="vhdlchar"></span>) <span class="vhdlchar">offset</span> <= { {<span class="vhdllogic">24</span>{<a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">71</span>]}}, <a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">71</span>:<span class="vhdllogic">64</span>] };
|
<a name="l01966"></a>01966 <span class="vhdlchar">group_0_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l01967"></a>01967 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">offset_control</span> == <a class="code" href="ao68000_8v.html#a87c5da2d7633077683260709d88602e0">`OFFSET_IMM_16</a><span class="vhdlchar"></span>) <span class="vhdlchar">offset</span> <= { {<span class="vhdllogic">16</span>{<a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">79</span>]}}, <a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">79</span>:<span class="vhdllogic">64</span>] };
|
<a name="l01967"></a>01967 <span class="vhdlkeyword">end</span>
|
<a name="l01968"></a>01968 <span class="vhdlkeyword">end</span>
|
<a name="l01968"></a>01968
|
<a name="l01969"></a>01969
|
<a name="l01969"></a><a class="code" href="classregisters.html#a328ee93f9ab0ed3ebab4dc5936a7c5a0">01969</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l01970"></a><a class="code" href="classregisters.html#a2a04a4a12e64f1ffb3ec95095716fee7">01970</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l01970"></a>01970 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">instruction_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l01971"></a>01971 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">index</span> <= <span class="vhdllogic">32'd0</span>;
|
<a name="l01971"></a>01971 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">instruction_flag_control</span> == <a class="code" href="ao68000_8v.html#a6882447365cc7940c16017ee13305875">`INSTRUCTION_FLAG_SET</a><span class="vhdlchar"></span>) <span class="vhdlchar">instruction_flag</span> <= <span class="vhdllogic">1'b1</span>;
|
<a name="l01972"></a>01972 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">index_control</span> == <a class="code" href="ao68000_8v.html#a1db54bd70d82cea2a77c6d5c823f04db">`INDEX_0</a><span class="vhdlchar"></span>) <span class="vhdlchar">index</span> <= <span class="vhdllogic">32'd0</span>;
|
<a name="l01972"></a>01972 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">instruction_flag_control</span> == <a class="code" href="ao68000_8v.html#adaf70d0e1aaa9fe89fc79971d67bc172">`INSTRUCTION_FLAG_CLEAR_IN_MAIN_LOOP</a><span class="vhdlchar"></span> && <a class="code" href="classregisters.html#aabb30e872d04701c156a70c4e1e7a3ba">prefetch_ir_valid</a> == <span class="vhdllogic">1'b1</span> && <a class="code" href="classregisters.html#a1444e3b474fdf49e5ab8a0283060ceab">decoder_trap</a> == <span class="vhdllogic">8'd0</span> && <span class="vhdlchar">stop_flag</span> == <span class="vhdllogic">1'b0</span>)
|
<a name="l01973"></a>01973 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">index_control</span> == <a class="code" href="ao68000_8v.html#af05405b84ee28262882d3c7ac7a5a80c">`INDEX_LOAD_EXTENDED</a><span class="vhdlchar"></span>) <span class="vhdlchar">index</span> <=
|
<a name="l01973"></a>01973 <span class="vhdlchar">instruction_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l01974"></a>01974 (<a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">79</span>] == <span class="vhdllogic">1'b0</span>) ?
|
<a name="l01974"></a>01974 <span class="vhdlkeyword">end</span>
|
<a name="l01975"></a>01975 ( (<a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">75</span>] == <span class="vhdllogic">1'b0</span>) ?
|
<a name="l01975"></a>01975
|
<a name="l01976"></a>01976 { {<span class="vhdllogic">16</span>{<a class="code" href="classregisters.html#a0376be737f05fcad48a8057caa2f1fcf">Dn_output</a>[<span class="vhdllogic">15</span>]}}, <a class="code" href="classregisters.html#a0376be737f05fcad48a8057caa2f1fcf">Dn_output</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] } : <a class="code" href="classregisters.html#a0376be737f05fcad48a8057caa2f1fcf">Dn_output</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>]
|
<a name="l01976"></a><a class="code" href="classregisters.html#ad172a9061d9bb3653a3996dc4a74e101">01976</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l01977"></a>01977 ) :
|
<a name="l01977"></a>01977 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">read_modify_write_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l01978"></a>01978 ( (<a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">75</span>] == <span class="vhdllogic">1'b0</span>) ?
|
<a name="l01978"></a>01978 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">read_modify_write_flag_control</span> == <a class="code" href="ao68000_8v.html#a2ba2dbb4697aa9a3559b775da0ade761">`READ_MODIFY_WRITE_FLAG_SET</a><span class="vhdlchar"></span>) <span class="vhdlchar">read_modify_write_flag</span> <= <span class="vhdllogic">1'b1</span>;
|
<a name="l01979"></a>01979 { {<span class="vhdllogic">16</span>{<a class="code" href="classregisters.html#a4076832588fccdd9d5d0cc1b4b8dd0b0">An_output</a>[<span class="vhdllogic">15</span>]}}, <a class="code" href="classregisters.html#a4076832588fccdd9d5d0cc1b4b8dd0b0">An_output</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] } : <a class="code" href="classregisters.html#a4076832588fccdd9d5d0cc1b4b8dd0b0">An_output</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>]
|
<a name="l01979"></a>01979 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">read_modify_write_flag_control</span> == <a class="code" href="ao68000_8v.html#ace5de6cd5ad33427e8efd5ec8191c297">`READ_MODIFY_WRITE_FLAG_CLEAR</a><span class="vhdlchar"></span>) <span class="vhdlchar">read_modify_write_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l01980"></a>01980 );
|
<a name="l01980"></a>01980 <span class="vhdlkeyword">end</span>
|
<a name="l01981"></a>01981 <span class="vhdlkeyword">end</span>
|
<a name="l01981"></a>01981
|
<a name="l01982"></a>01982
|
<a name="l01982"></a><a class="code" href="classregisters.html#a34326a20d0a44ce95c7da4da53005097">01982</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l01983"></a><a class="code" href="classregisters.html#af284685eb0240e8fc444c84618b1af67">01983</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l01983"></a>01983 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">do_reset_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l01984"></a>01984 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">stop_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l01984"></a>01984 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_reset_flag_control</span> == <a class="code" href="ao68000_8v.html#a682472d63f131aa31c38abd6f2d577ab">`DO_RESET_FLAG_SET</a><span class="vhdlchar"></span>) <span class="vhdlchar">do_reset_flag</span> <= <span class="vhdllogic">1'b1</span>;
|
<a name="l01985"></a>01985 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">stop_flag_control</span> == <a class="code" href="ao68000_8v.html#a5131e7ee341cd6f2ea5350a89b19a488">`STOP_FLAG_SET</a><span class="vhdlchar"></span>) <span class="vhdlchar">stop_flag</span> <= <span class="vhdllogic">1'b1</span>;
|
<a name="l01985"></a>01985 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_reset_flag_control</span> == <a class="code" href="ao68000_8v.html#afd7c962bcd95f3629d247e7790f9cf95">`DO_RESET_FLAG_CLEAR</a><span class="vhdlchar"></span>) <span class="vhdlchar">do_reset_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l01986"></a>01986 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">stop_flag_control</span> == <a class="code" href="ao68000_8v.html#a0e63684fc863d639423c2d9f0f8e6cd9">`STOP_FLAG_CLEAR</a><span class="vhdlchar"></span>) <span class="vhdlchar">stop_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l01986"></a>01986 <span class="vhdlkeyword">end</span>
|
<a name="l01987"></a>01987 <span class="vhdlkeyword">end</span>
|
<a name="l01987"></a>01987
|
<a name="l01988"></a>01988
|
<a name="l01988"></a><a class="code" href="classregisters.html#ad881b4aebf8b3df42129f9731b6f6098">01988</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
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<a name="l01989"></a><a class="code" href="classregisters.html#a12d4c2e0121456bcb2b23e7444c1da06">01989</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l01989"></a>01989 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">do_interrupt_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l01990"></a>01990 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">trace_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l01990"></a>01990 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_interrupt_flag_control</span> == <a class="code" href="ao68000_8v.html#acc420165ae00aa63b4d40c220dc1ed79">`DO_INTERRUPT_FLAG_SET_IF_ACTIVE</a><span class="vhdlchar"></span>) <span class="vhdlchar">do_interrupt_flag</span> <= (<a class="code" href="classregisters.html#aaa89ede670fdc60f2b18c637c50f0dff">interrupt_mask</a> != <span class="vhdllogic">3'b000</span>) ? <span class="vhdllogic">1'b1</span> : <span class="vhdllogic">1'b0</span>;
|
<a name="l01991"></a>01991 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">trace_flag_control</span> == <a class="code" href="ao68000_8v.html#a3cb5bcdd68537f527007213efe5c2d4f">`TRACE_FLAG_COPY_WHEN_NO_STOP</a><span class="vhdlchar"></span> && <a class="code" href="classregisters.html#aabb30e872d04701c156a70c4e1e7a3ba">prefetch_ir_valid</a> == <span class="vhdllogic">1'b1</span> && <a class="code" href="classregisters.html#a1444e3b474fdf49e5ab8a0283060ceab">decoder_trap</a> == <span class="vhdllogic">8'd0</span> && <span class="vhdlchar">stop_flag</span> == <span class="vhdllogic">1'b0</span>)
|
<a name="l01991"></a>01991 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_interrupt_flag_control</span> == <a class="code" href="ao68000_8v.html#abe668eeea71491f898b31b9c66a4db96">`DO_INTERRUPT_FLAG_CLEAR</a><span class="vhdlchar"></span>) <span class="vhdlchar">do_interrupt_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l01992"></a>01992 <span class="vhdlchar">trace_flag</span> <= <a class="code" href="classregisters.html#ad583f99f893a13448ecd261e637ad56b">sr</a>[<span class="vhdllogic">15</span>];
|
<a name="l01992"></a>01992 <span class="vhdlkeyword">end</span>
|
<a name="l01993"></a>01993 <span class="vhdlkeyword">end</span>
|
<a name="l01993"></a>01993
|
<a name="l01994"></a>01994
|
<a name="l01994"></a><a class="code" href="classregisters.html#aa69b93f001339d4b8ae1295a5cb215ec">01994</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l01995"></a><a class="code" href="classregisters.html#acf180186b03cdc0ad93be0efb7fa2815">01995</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l01995"></a>01995 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">do_read_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l01996"></a>01996 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">group_0_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l01996"></a>01996 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_read_flag_control</span> == <a class="code" href="ao68000_8v.html#a210a4746c070617bd4272cf091ce4977">`DO_READ_FLAG_SET</a><span class="vhdlchar"></span>) <span class="vhdlchar">do_read_flag</span> <= <span class="vhdllogic">1'b1</span>;
|
<a name="l01997"></a>01997 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">group_0_flag_control</span> == <a class="code" href="ao68000_8v.html#a5333b31d43f3c7de70d3cad313720ef4">`GROUP_0_FLAG_SET</a><span class="vhdlchar"></span>) <span class="vhdlchar">group_0_flag</span> <= <span class="vhdllogic">1'b1</span>;
|
<a name="l01997"></a>01997 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_read_flag_control</span> == <a class="code" href="ao68000_8v.html#a3186ce27b4c9202d124c4bee6b07e2fd">`DO_READ_FLAG_CLEAR</a><span class="vhdlchar"></span>) <span class="vhdlchar">do_read_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l01998"></a>01998 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">group_0_flag_control</span> == <a class="code" href="ao68000_8v.html#a28adb393ace594d548dfe7f070fd837b">`GROUP_0_FLAG_CLEAR_WHEN_VALID_PREFETCH</a><span class="vhdlchar"></span> && <a class="code" href="classregisters.html#aabb30e872d04701c156a70c4e1e7a3ba">prefetch_ir_valid</a> == <span class="vhdllogic">1'b1</span> && <span class="vhdlchar">stop_flag</span> == <span class="vhdllogic">1'b0</span>)
|
<a name="l01998"></a>01998 <span class="vhdlkeyword">end</span>
|
<a name="l01999"></a>01999 <span class="vhdlchar">group_0_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l01999"></a>01999
|
<a name="l02000"></a>02000 <span class="vhdlkeyword">end</span>
|
<a name="l02000"></a><a class="code" href="classregisters.html#a63d22bb9298a179653d09d6b21e6c68b">02000</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l02001"></a>02001
|
<a name="l02001"></a>02001 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">do_write_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l02002"></a><a class="code" href="classregisters.html#a328ee93f9ab0ed3ebab4dc5936a7c5a0">02002</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l02002"></a>02002 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_write_flag_control</span> == <a class="code" href="ao68000_8v.html#a97fc325edc48a555daf24f1757c5e7bf">`DO_WRITE_FLAG_SET</a><span class="vhdlchar"></span>) <span class="vhdlchar">do_write_flag</span> <= <span class="vhdllogic">1'b1</span>;
|
<a name="l02003"></a>02003 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">instruction_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l02003"></a>02003 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_write_flag_control</span> == <a class="code" href="ao68000_8v.html#ad6f9aea669c0c0233f4155f29afc4d1d">`DO_WRITE_FLAG_CLEAR</a><span class="vhdlchar"></span>) <span class="vhdlchar">do_write_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l02004"></a>02004 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">instruction_flag_control</span> == <a class="code" href="ao68000_8v.html#a6882447365cc7940c16017ee13305875">`INSTRUCTION_FLAG_SET</a><span class="vhdlchar"></span>) <span class="vhdlchar">instruction_flag</span> <= <span class="vhdllogic">1'b1</span>;
|
<a name="l02004"></a>02004 <span class="vhdlkeyword">end</span>
|
<a name="l02005"></a>02005 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">instruction_flag_control</span> == <a class="code" href="ao68000_8v.html#adaf70d0e1aaa9fe89fc79971d67bc172">`INSTRUCTION_FLAG_CLEAR_IN_MAIN_LOOP</a><span class="vhdlchar"></span> && <a class="code" href="classregisters.html#aabb30e872d04701c156a70c4e1e7a3ba">prefetch_ir_valid</a> == <span class="vhdllogic">1'b1</span> && <a class="code" href="classregisters.html#a1444e3b474fdf49e5ab8a0283060ceab">decoder_trap</a> == <span class="vhdllogic">8'd0</span> && <span class="vhdlchar">stop_flag</span> == <span class="vhdllogic">1'b0</span>)
|
<a name="l02005"></a>02005
|
<a name="l02006"></a>02006 <span class="vhdlchar">instruction_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l02006"></a><a class="code" href="classregisters.html#a66ffba6d56dd08fe7b968605c3b68465">02006</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l02007"></a>02007 <span class="vhdlkeyword">end</span>
|
<a name="l02007"></a>02007 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">do_blocked_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l02008"></a>02008
|
<a name="l02008"></a>02008 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_blocked_flag_control</span> == <a class="code" href="ao68000_8v.html#ac69029fe984c3090537ed247a8106344">`DO_BLOCKED_FLAG_SET</a><span class="vhdlchar"></span>) <span class="vhdlchar">do_blocked_flag</span> <= <span class="vhdllogic">1'b1</span>;
|
<a name="l02009"></a><a class="code" href="classregisters.html#ad172a9061d9bb3653a3996dc4a74e101">02009</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l02009"></a>02009 <span class="vhdlkeyword">end</span>
|
<a name="l02010"></a>02010 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">read_modify_write_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l02010"></a>02010
|
<a name="l02011"></a>02011 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">read_modify_write_flag_control</span> == <a class="code" href="ao68000_8v.html#a2ba2dbb4697aa9a3559b775da0ade761">`READ_MODIFY_WRITE_FLAG_SET</a><span class="vhdlchar"></span>) <span class="vhdlchar">read_modify_write_flag</span> <= <span class="vhdllogic">1'b1</span>;
|
<a name="l02011"></a><a class="code" href="classregisters.html#ab3c53c1dc1763e2d051eaa736e429d58">02011</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l02012"></a>02012 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">read_modify_write_flag_control</span> == <a class="code" href="ao68000_8v.html#ace5de6cd5ad33427e8efd5ec8191c297">`READ_MODIFY_WRITE_FLAG_CLEAR</a><span class="vhdlchar"></span>) <span class="vhdlchar">read_modify_write_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l02012"></a>02012 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">data_write</span> <= <span class="vhdllogic">32'd0</span>;
|
<a name="l02013"></a>02013 <span class="vhdlkeyword">end</span>
|
<a name="l02013"></a>02013 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">data_write_control</span> == <a class="code" href="ao68000_8v.html#ab576808298f9e1938241b8843e55c54e">`DATA_WRITE_FROM_RESULT</a><span class="vhdlchar"></span>) <span class="vhdlchar">data_write</span> <= <a class="code" href="classregisters.html#a81ed0f1a7f814e74696bea4db63f1e31">result</a>;
|
<a name="l02014"></a>02014
|
<a name="l02014"></a>02014 <span class="vhdlkeyword">end</span>
|
<a name="l02015"></a><a class="code" href="classregisters.html#a34326a20d0a44ce95c7da4da53005097">02015</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l02015"></a>02015
|
<a name="l02016"></a>02016 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">do_reset_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l02016"></a>02016 <span class="vhdlkeyword">assign</span> <span class="vhdlchar">An_address</span> =
|
<a name="l02017"></a>02017 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_reset_flag_control</span> == <a class="code" href="ao68000_8v.html#a682472d63f131aa31c38abd6f2d577ab">`DO_RESET_FLAG_SET</a><span class="vhdlchar"></span>) <span class="vhdlchar">do_reset_flag</span> <= <span class="vhdllogic">1'b1</span>;
|
<a name="l02017"></a>02017 (<span class="vhdlchar">An_address_control</span> == <a class="code" href="ao68000_8v.html#a50986c5b3afb053fcb3841dce7a93115">`AN_ADDRESS_FROM_EXTENDED</a><span class="vhdlchar"></span>) ? { <a class="code" href="classregisters.html#ad583f99f893a13448ecd261e637ad56b">sr</a>[<span class="vhdllogic">13</span>], <a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">78</span>:<span class="vhdllogic">76</span>] } :
|
<a name="l02018"></a>02018 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_reset_flag_control</span> == <a class="code" href="ao68000_8v.html#afd7c962bcd95f3629d247e7790f9cf95">`DO_RESET_FLAG_CLEAR</a><span class="vhdlchar"></span>) <span class="vhdlchar">do_reset_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l02018"></a>02018 (<span class="vhdlchar">An_address_control</span> == <a class="code" href="ao68000_8v.html#ad5d4b9f48266549b9e8e5ac0c3ad239a">`AN_ADDRESS_USP</a><span class="vhdlchar"></span>) ? <span class="vhdllogic">4'b0111</span> :
|
<a name="l02019"></a>02019 <span class="vhdlkeyword">end</span>
|
<a name="l02019"></a>02019 (<span class="vhdlchar">An_address_control</span> == <a class="code" href="ao68000_8v.html#a0dff5098fabf2afeac419c2e3c69b452">`AN_ADDRESS_SSP</a><span class="vhdlchar"></span>) ? <span class="vhdllogic">4'b1111</span> :
|
<a name="l02020"></a>02020
|
<a name="l02020"></a>02020 { <a class="code" href="classregisters.html#ad583f99f893a13448ecd261e637ad56b">sr</a>[<span class="vhdllogic">13</span>], <a class="code" href="classregisters.html#a69652ae311e16ddcb1bb0dbc90744156">ea_reg</a> };
|
<a name="l02021"></a><a class="code" href="classregisters.html#ad881b4aebf8b3df42129f9731b6f6098">02021</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l02021"></a>02021
|
<a name="l02022"></a>02022 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">do_interrupt_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l02022"></a>02022 <span class="vhdlkeyword">assign</span> <span class="vhdlchar">An_input</span> =
|
<a name="l02023"></a>02023 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_interrupt_flag_control</span> == <a class="code" href="ao68000_8v.html#acc420165ae00aa63b4d40c220dc1ed79">`DO_INTERRUPT_FLAG_SET_IF_ACTIVE</a><span class="vhdlchar"></span>) <span class="vhdlchar">do_interrupt_flag</span> <= (<a class="code" href="classregisters.html#aaa89ede670fdc60f2b18c637c50f0dff">interrupt_mask</a> != <span class="vhdllogic">3'b000</span>) ? <span class="vhdllogic">1'b1</span> : <span class="vhdllogic">1'b0</span>;
|
<a name="l02023"></a>02023 (<span class="vhdlchar">An_input_control</span> == <a class="code" href="ao68000_8v.html#a67d98f6de465730c1bc9792aab02784c">`AN_INPUT_FROM_ADDRESS</a><span class="vhdlchar"></span>) ? <span class="vhdlchar">address</span> :
|
<a name="l02024"></a>02024 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_interrupt_flag_control</span> == <a class="code" href="ao68000_8v.html#abe668eeea71491f898b31b9c66a4db96">`DO_INTERRUPT_FLAG_CLEAR</a><span class="vhdlchar"></span>) <span class="vhdlchar">do_interrupt_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l02024"></a>02024 (<span class="vhdlchar">An_input_control</span> == <a class="code" href="ao68000_8v.html#a90bc8bad52abb88cc05948307f41ffcf">`AN_INPUT_FROM_PREFETCH_IR</a><span class="vhdlchar"></span>) ? <a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">79</span>:<span class="vhdllogic">48</span>] :
|
<a name="l02025"></a>02025 <span class="vhdlkeyword">end</span>
|
<a name="l02025"></a>02025 <a class="code" href="classregisters.html#a81ed0f1a7f814e74696bea4db63f1e31">result</a>;
|
<a name="l02026"></a>02026
|
<a name="l02026"></a>02026
|
<a name="l02027"></a><a class="code" href="classregisters.html#aa69b93f001339d4b8ae1295a5cb215ec">02027</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l02027"></a>02027 <span class="vhdlkeyword">assign</span> <span class="vhdlchar">Dn_address</span> = (<span class="vhdlchar">Dn_address_control</span> == <a class="code" href="ao68000_8v.html#aad74420658cfe8412a03c3dd6654ceb1">`DN_ADDRESS_FROM_EXTENDED</a><span class="vhdlchar"></span>) ? <a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">78</span>:<span class="vhdllogic">76</span>] : <a class="code" href="classregisters.html#a69652ae311e16ddcb1bb0dbc90744156">ea_reg</a>;
|
<a name="l02028"></a>02028 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">do_read_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l02028"></a>02028
|
<a name="l02029"></a>02029 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_read_flag_control</span> == <a class="code" href="ao68000_8v.html#a210a4746c070617bd4272cf091ce4977">`DO_READ_FLAG_SET</a><span class="vhdlchar"></span>) <span class="vhdlchar">do_read_flag</span> <= <span class="vhdllogic">1'b1</span>;
|
<a name="l02029"></a>02029 <span class="vhdlkeyword">endmodule</span>
|
<a name="l02030"></a>02030 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_read_flag_control</span> == <a class="code" href="ao68000_8v.html#a3186ce27b4c9202d124c4bee6b07e2fd">`DO_READ_FLAG_CLEAR</a><span class="vhdlchar"></span>) <span class="vhdlchar">do_read_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l02030"></a>02030
|
<a name="l02031"></a>02031 <span class="vhdlkeyword">end</span>
|
<a name="l02031"></a>02031 <span class="keyword">/***********************************************************************************************************************</span>
|
<a name="l02032"></a>02032
|
<a name="l02032"></a>02032 <span class="keyword"> Memory registers</span>
|
<a name="l02033"></a><a class="code" href="classregisters.html#a63d22bb9298a179653d09d6b21e6c68b">02033</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l02033"></a>02033 <span class="keyword"> ***********************************************************************************************************************/</span>
|
<a name="l02034"></a>02034 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">do_write_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l02034"></a>02034
|
<a name="l02035"></a>02035 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_write_flag_control</span> == <a class="code" href="ao68000_8v.html#a97fc325edc48a555daf24f1757c5e7bf">`DO_WRITE_FLAG_SET</a><span class="vhdlchar"></span>) <span class="vhdlchar">do_write_flag</span> <= <span class="vhdllogic">1'b1</span>;
|
<a name="l02035"></a>02035
|
<a name="l02036"></a>02036 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_write_flag_control</span> == <a class="code" href="ao68000_8v.html#ad6f9aea669c0c0233f4155f29afc4d1d">`DO_WRITE_FLAG_CLEAR</a><span class="vhdlchar"></span>) <span class="vhdlchar">do_write_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l02044"></a><a class="code" href="classmemory__registers.html">02044</a> <span class="vhdlkeyword">module</span> <a class="code" href="classmemory__registers.html">memory_registers</a>(
|
<a name="l02037"></a>02037 <span class="vhdlkeyword">end</span>
|
<a name="l02045"></a><a class="code" href="classmemory__registers.html#a06690d046213efc68334643946af2b16">02045</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmemory__registers.html#a06690d046213efc68334643946af2b16">clock</a>,
|
<a name="l02038"></a>02038
|
<a name="l02046"></a><a class="code" href="classmemory__registers.html#a52bffc13966ddfc557c3c3a2cece1d97">02046</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmemory__registers.html#a52bffc13966ddfc557c3c3a2cece1d97">reset_n</a>,
|
<a name="l02039"></a><a class="code" href="classregisters.html#a66ffba6d56dd08fe7b968605c3b68465">02039</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l02047"></a>02047
|
<a name="l02040"></a>02040 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">do_blocked_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l02048"></a>02048 <span class="keyword">// 0000,0001,0010,0011,0100,0101,0110: A0-A6, 0111: USP, 1111: SSP</span>
|
<a name="l02041"></a>02041 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_blocked_flag_control</span> == <a class="code" href="ao68000_8v.html#ac69029fe984c3090537ed247a8106344">`DO_BLOCKED_FLAG_SET</a><span class="vhdlchar"></span>) <span class="vhdlchar">do_blocked_flag</span> <= <span class="vhdllogic">1'b1</span>;
|
<a name="l02049"></a><a class="code" href="classmemory__registers.html#a8a67810353708d3652f619623692a545">02049</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmemory__registers.html#a8a67810353708d3652f619623692a545">An_address</a>,
|
<a name="l02042"></a>02042 <span class="vhdlkeyword">end</span>
|
<a name="l02050"></a><a class="code" href="classmemory__registers.html#a8e3deabb065d3e6aaaf647a83e7c84e9">02050</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmemory__registers.html#a8e3deabb065d3e6aaaf647a83e7c84e9">An_input</a>,
|
<a name="l02043"></a>02043
|
<a name="l02051"></a><a class="code" href="classmemory__registers.html#af97dfc643a2fa9ae191cb68acb23ea91">02051</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmemory__registers.html#af97dfc643a2fa9ae191cb68acb23ea91">An_write_enable</a>,
|
<a name="l02044"></a><a class="code" href="classregisters.html#ab3c53c1dc1763e2d051eaa736e429d58">02044</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l02052"></a><a class="code" href="classmemory__registers.html#a806c8f12e4600aa02e87d61e072eb6e4">02052</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmemory__registers.html#a806c8f12e4600aa02e87d61e072eb6e4">An_output</a>,
|
<a name="l02045"></a>02045 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">data_write</span> <= <span class="vhdllogic">32'd0</span>;
|
<a name="l02053"></a>02053
|
<a name="l02046"></a>02046 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">data_write_control</span> == <a class="code" href="ao68000_8v.html#ab576808298f9e1938241b8843e55c54e">`DATA_WRITE_FROM_RESULT</a><span class="vhdlchar"></span>) <span class="vhdlchar">data_write</span> <= <a class="code" href="classregisters.html#a81ed0f1a7f814e74696bea4db63f1e31">result</a>;
|
<a name="l02054"></a><a class="code" href="classmemory__registers.html#a736b71ba5d8851ef8e883408751c9380">02054</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmemory__registers.html#a736b71ba5d8851ef8e883408751c9380">usp</a>,
|
<a name="l02047"></a>02047 <span class="vhdlkeyword">end</span>
|
<a name="l02055"></a>02055
|
<a name="l02048"></a>02048
|
<a name="l02056"></a><a class="code" href="classmemory__registers.html#a3faa61795c758b3d444c082be9ac5758">02056</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmemory__registers.html#a3faa61795c758b3d444c082be9ac5758">Dn_address</a>,
|
<a name="l02049"></a>02049 <span class="vhdlkeyword">assign</span> <span class="vhdlchar">An_address</span> =
|
<a name="l02057"></a><a class="code" href="classmemory__registers.html#a87f20385b6a12cc8249588a492930b31">02057</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmemory__registers.html#a87f20385b6a12cc8249588a492930b31">Dn_input</a>,
|
<a name="l02050"></a>02050 (<span class="vhdlchar">An_address_control</span> == <a class="code" href="ao68000_8v.html#a50986c5b3afb053fcb3841dce7a93115">`AN_ADDRESS_FROM_EXTENDED</a><span class="vhdlchar"></span>) ? { <a class="code" href="classregisters.html#ad583f99f893a13448ecd261e637ad56b">sr</a>[<span class="vhdllogic">13</span>], <a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">78</span>:<span class="vhdllogic">76</span>] } :
|
<a name="l02058"></a><a class="code" href="classmemory__registers.html#a04d4474459a5b178f532443990dc10ed">02058</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmemory__registers.html#a04d4474459a5b178f532443990dc10ed">Dn_write_enable</a>,
|
<a name="l02051"></a>02051 (<span class="vhdlchar">An_address_control</span> == <a class="code" href="ao68000_8v.html#ad5d4b9f48266549b9e8e5ac0c3ad239a">`AN_ADDRESS_USP</a><span class="vhdlchar"></span>) ? <span class="vhdllogic">4'b0111</span> :
|
<a name="l02059"></a>02059 <span class="keyword">// 001: byte, 010: word, 100: long</span>
|
<a name="l02052"></a>02052 (<span class="vhdlchar">An_address_control</span> == <a class="code" href="ao68000_8v.html#a0dff5098fabf2afeac419c2e3c69b452">`AN_ADDRESS_SSP</a><span class="vhdlchar"></span>) ? <span class="vhdllogic">4'b1111</span> :
|
<a name="l02060"></a><a class="code" href="classmemory__registers.html#aa007104c0e9ef230ac07ad5b242ca8b5">02060</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmemory__registers.html#aa007104c0e9ef230ac07ad5b242ca8b5">Dn_size</a>,
|
<a name="l02053"></a>02053 { <a class="code" href="classregisters.html#ad583f99f893a13448ecd261e637ad56b">sr</a>[<span class="vhdllogic">13</span>], <a class="code" href="classregisters.html#a69652ae311e16ddcb1bb0dbc90744156">ea_reg</a> };
|
<a name="l02061"></a><a class="code" href="classmemory__registers.html#a2c906a8760a85b5370b8c7f56dc4e6f3">02061</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmemory__registers.html#a2c906a8760a85b5370b8c7f56dc4e6f3">Dn_output</a>,
|
<a name="l02054"></a>02054
|
<a name="l02062"></a>02062
|
<a name="l02055"></a>02055 <span class="vhdlkeyword">assign</span> <span class="vhdlchar">An_input</span> =
|
<a name="l02063"></a><a class="code" href="classmemory__registers.html#ac8716768ab1d64ea847be358444da7ee">02063</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmemory__registers.html#ac8716768ab1d64ea847be358444da7ee">micro_pc</a>,
|
<a name="l02056"></a>02056 (<span class="vhdlchar">An_input_control</span> == <a class="code" href="ao68000_8v.html#a67d98f6de465730c1bc9792aab02784c">`AN_INPUT_FROM_ADDRESS</a><span class="vhdlchar"></span>) ? <span class="vhdlchar">address</span> :
|
<a name="l02064"></a><a class="code" href="classmemory__registers.html#ad13be4dbb1d8afc5ea1f9b5e8bb80e3c">02064</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">87</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmemory__registers.html#ad13be4dbb1d8afc5ea1f9b5e8bb80e3c">micro_data</a>
|
<a name="l02057"></a>02057 (<span class="vhdlchar">An_input_control</span> == <a class="code" href="ao68000_8v.html#a90bc8bad52abb88cc05948307f41ffcf">`AN_INPUT_FROM_PREFETCH_IR</a><span class="vhdlchar"></span>) ? <a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">79</span>:<span class="vhdllogic">48</span>] :
|
<a name="l02065"></a>02065 );
|
<a name="l02058"></a>02058 <a class="code" href="classregisters.html#a81ed0f1a7f814e74696bea4db63f1e31">result</a>;
|
<a name="l02066"></a>02066
|
<a name="l02059"></a>02059
|
<a name="l02067"></a><a class="code" href="classmemory__registers.html#a2d55f5fd1b27c45d04af9b19559c2ae9">02067</a> <span class="vhdlkeyword">wire</span> <a class="code" href="classmemory__registers.html#a2d55f5fd1b27c45d04af9b19559c2ae9">An_ram_write_enable</a> = (<a class="code" href="classmemory__registers.html#a8a67810353708d3652f619623692a545">An_address</a> == <span class="vhdllogic">4'b0111</span>) ? <span class="vhdllogic">1'b0</span> : <a class="code" href="classmemory__registers.html#af97dfc643a2fa9ae191cb68acb23ea91">An_write_enable</a>;
|
<a name="l02060"></a>02060 <span class="vhdlkeyword">assign</span> <span class="vhdlchar">Dn_address</span> = (<span class="vhdlchar">Dn_address_control</span> == <a class="code" href="ao68000_8v.html#aad74420658cfe8412a03c3dd6654ceb1">`DN_ADDRESS_FROM_EXTENDED</a><span class="vhdlchar"></span>) ? <a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">78</span>:<span class="vhdllogic">76</span>] : <a class="code" href="classregisters.html#a69652ae311e16ddcb1bb0dbc90744156">ea_reg</a>;
|
|
<a name="l02061"></a>02061
|
|
<a name="l02062"></a>02062 <span class="vhdlkeyword">endmodule</span>
|
|
<a name="l02063"></a>02063
|
|
<a name="l02064"></a>02064 <span class="keyword">/***********************************************************************************************************************</span>
|
|
<a name="l02065"></a>02065 <span class="keyword"> Memory registers</span>
|
|
<a name="l02066"></a>02066 <span class="keyword"> ***********************************************************************************************************************/</span>
|
|
<a name="l02067"></a>02067
|
|
<a name="l02068"></a>02068
|
<a name="l02068"></a>02068
|
<a name="l02077"></a><a class="code" href="classmemory__registers.html">02077</a> <span class="vhdlkeyword">module</span> <a class="code" href="classmemory__registers.html">memory_registers</a>(
|
<a name="l02069"></a><a class="code" href="classmemory__registers.html#a49af6a7e50d837d339f79765aa2b9ee7">02069</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmemory__registers.html#a49af6a7e50d837d339f79765aa2b9ee7">An_ram_output</a>;
|
<a name="l02078"></a><a class="code" href="classmemory__registers.html#a06690d046213efc68334643946af2b16">02078</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmemory__registers.html#a06690d046213efc68334643946af2b16">clock</a>,
|
<a name="l02070"></a>02070 <span class="vhdlkeyword">assign</span> <a class="code" href="classmemory__registers.html#a806c8f12e4600aa02e87d61e072eb6e4">An_output</a> = (<a class="code" href="classmemory__registers.html#a8a67810353708d3652f619623692a545">An_address</a> == <span class="vhdllogic">4'b0111</span>) ? <a class="code" href="classmemory__registers.html#a736b71ba5d8851ef8e883408751c9380">usp</a> : <a class="code" href="classmemory__registers.html#a49af6a7e50d837d339f79765aa2b9ee7">An_ram_output</a>;
|
<a name="l02079"></a><a class="code" href="classmemory__registers.html#a52bffc13966ddfc557c3c3a2cece1d97">02079</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmemory__registers.html#a52bffc13966ddfc557c3c3a2cece1d97">reset_n</a>,
|
<a name="l02071"></a>02071
|
<a name="l02080"></a>02080
|
<a name="l02072"></a><a class="code" href="classmemory__registers.html#a6d1775137e4a2f6a96e0cf49b76dc524">02072</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmemory__registers.html#a6d1775137e4a2f6a96e0cf49b76dc524">dn_byteena</a> = (<a class="code" href="classmemory__registers.html#aa007104c0e9ef230ac07ad5b242ca8b5">Dn_size</a>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) ? <span class="vhdllogic">4'b0001</span> :
|
<a name="l02081"></a>02081 <span class="keyword">// 0000,0001,0010,0011,0100,0101,0110: A0-A6, 0111: USP, 1111: SSP</span>
|
<a name="l02073"></a>02073 (<a class="code" href="classmemory__registers.html#aa007104c0e9ef230ac07ad5b242ca8b5">Dn_size</a>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) ? <span class="vhdllogic">4'b0011</span> :
|
<a name="l02082"></a><a class="code" href="classmemory__registers.html#a8a67810353708d3652f619623692a545">02082</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmemory__registers.html#a8a67810353708d3652f619623692a545">An_address</a>,
|
<a name="l02074"></a>02074 (<a class="code" href="classmemory__registers.html#aa007104c0e9ef230ac07ad5b242ca8b5">Dn_size</a>[<span class="vhdllogic">2</span>] == <span class="vhdllogic">1'b1</span>) ? <span class="vhdllogic">4'b1111</span> :
|
<a name="l02083"></a><a class="code" href="classmemory__registers.html#a8e3deabb065d3e6aaaf647a83e7c84e9">02083</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmemory__registers.html#a8e3deabb065d3e6aaaf647a83e7c84e9">An_input</a>,
|
<a name="l02075"></a>02075 <span class="vhdllogic">4'b0000</span>;
|
<a name="l02084"></a><a class="code" href="classmemory__registers.html#af97dfc643a2fa9ae191cb68acb23ea91">02084</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmemory__registers.html#af97dfc643a2fa9ae191cb68acb23ea91">An_write_enable</a>,
|
<a name="l02076"></a>02076
|
<a name="l02085"></a><a class="code" href="classmemory__registers.html#a806c8f12e4600aa02e87d61e072eb6e4">02085</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmemory__registers.html#a806c8f12e4600aa02e87d61e072eb6e4">An_output</a>,
|
<a name="l02077"></a><a class="code" href="classmemory__registers.html#a09281e3224878c570c81844785844fe0">02077</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classmemory__registers.html#a06690d046213efc68334643946af2b16">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classmemory__registers.html#a52bffc13966ddfc557c3c3a2cece1d97">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l02086"></a>02086
|
<a name="l02078"></a>02078 <span class="vhdlkeyword">if</span>(<a class="code" href="classmemory__registers.html#a52bffc13966ddfc557c3c3a2cece1d97">reset_n</a> == <span class="vhdllogic">1'b0</span>) <a class="code" href="classmemory__registers.html#a736b71ba5d8851ef8e883408751c9380">usp</a> <= <span class="vhdllogic">32'd0</span>;
|
<a name="l02087"></a><a class="code" href="classmemory__registers.html#a736b71ba5d8851ef8e883408751c9380">02087</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmemory__registers.html#a736b71ba5d8851ef8e883408751c9380">usp</a>,
|
<a name="l02079"></a>02079 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classmemory__registers.html#a8a67810353708d3652f619623692a545">An_address</a> == <span class="vhdllogic">4'b0111</span> && <a class="code" href="classmemory__registers.html#af97dfc643a2fa9ae191cb68acb23ea91">An_write_enable</a>) <a class="code" href="classmemory__registers.html#a736b71ba5d8851ef8e883408751c9380">usp</a> <= <a class="code" href="classmemory__registers.html#a8e3deabb065d3e6aaaf647a83e7c84e9">An_input</a>;
|
<a name="l02088"></a>02088
|
<a name="l02080"></a>02080 <span class="vhdlkeyword">end</span>
|
<a name="l02089"></a><a class="code" href="classmemory__registers.html#a3faa61795c758b3d444c082be9ac5758">02089</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmemory__registers.html#a3faa61795c758b3d444c082be9ac5758">Dn_address</a>,
|
<a name="l02081"></a>02081
|
<a name="l02090"></a><a class="code" href="classmemory__registers.html#a87f20385b6a12cc8249588a492930b31">02090</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmemory__registers.html#a87f20385b6a12cc8249588a492930b31">Dn_input</a>,
|
<a name="l02082"></a>02082 <span class="keyword">// Register set An implemented as RAM.</span>
|
<a name="l02091"></a><a class="code" href="classmemory__registers.html#a04d4474459a5b178f532443990dc10ed">02091</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmemory__registers.html#a04d4474459a5b178f532443990dc10ed">Dn_write_enable</a>,
|
<a name="l02083"></a><a class="code" href="classmemory__registers.html#a892186b1bfe856b1ddaf1d8b3a448f50">02083</a> <a class="code" href="classmemory__registers.html#a892186b1bfe856b1ddaf1d8b3a448f50">altsyncram</a> <span class="vhdlchar">an_ram_inst</span>(
|
<a name="l02092"></a>02092 <span class="keyword">// 001: byte, 010: word, 100: long</span>
|
<a name="l02084"></a>02084 .<span class="vhdlchar">clock0</span> (<a class="code" href="classmemory__registers.html#a06690d046213efc68334643946af2b16">clock</a>),
|
<a name="l02093"></a><a class="code" href="classmemory__registers.html#aa007104c0e9ef230ac07ad5b242ca8b5">02093</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmemory__registers.html#aa007104c0e9ef230ac07ad5b242ca8b5">Dn_size</a>,
|
<a name="l02085"></a>02085
|
<a name="l02094"></a><a class="code" href="classmemory__registers.html#a2c906a8760a85b5370b8c7f56dc4e6f3">02094</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmemory__registers.html#a2c906a8760a85b5370b8c7f56dc4e6f3">Dn_output</a>,
|
<a name="l02086"></a>02086 .<span class="vhdlchar">address_a</span> (<a class="code" href="classmemory__registers.html#a8a67810353708d3652f619623692a545">An_address</a>[<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>]),
|
<a name="l02095"></a>02095
|
<a name="l02087"></a>02087 .<span class="vhdlchar">byteena_a</span> (<span class="vhdllogic">4'b1111</span>),
|
<a name="l02096"></a><a class="code" href="classmemory__registers.html#ac8716768ab1d64ea847be358444da7ee">02096</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmemory__registers.html#ac8716768ab1d64ea847be358444da7ee">micro_pc</a>,
|
<a name="l02088"></a>02088 .<span class="vhdlchar">wren_a</span> (<a class="code" href="classmemory__registers.html#a2d55f5fd1b27c45d04af9b19559c2ae9">An_ram_write_enable</a>),
|
<a name="l02097"></a><a class="code" href="classmemory__registers.html#ad13be4dbb1d8afc5ea1f9b5e8bb80e3c">02097</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">87</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmemory__registers.html#ad13be4dbb1d8afc5ea1f9b5e8bb80e3c">micro_data</a>
|
<a name="l02089"></a>02089 .<span class="vhdlchar">data_a</span> (<a class="code" href="classmemory__registers.html#a8e3deabb065d3e6aaaf647a83e7c84e9">An_input</a>),
|
<a name="l02098"></a>02098 );
|
<a name="l02090"></a>02090 .<span class="vhdlchar">q_a</span> (<a class="code" href="classmemory__registers.html#a49af6a7e50d837d339f79765aa2b9ee7">An_ram_output</a>)
|
<a name="l02099"></a>02099
|
<a name="l02091"></a>02091 );
|
<a name="l02100"></a><a class="code" href="classmemory__registers.html#a2d55f5fd1b27c45d04af9b19559c2ae9">02100</a> <span class="vhdlkeyword">wire</span> <a class="code" href="classmemory__registers.html#a2d55f5fd1b27c45d04af9b19559c2ae9">An_ram_write_enable</a> = (<a class="code" href="classmemory__registers.html#a8a67810353708d3652f619623692a545">An_address</a> == <span class="vhdllogic">4'b0111</span>) ? <span class="vhdllogic">1'b0</span> : <a class="code" href="classmemory__registers.html#af97dfc643a2fa9ae191cb68acb23ea91">An_write_enable</a>;
|
<a name="l02092"></a>02092 <span class="vhdlkeyword">defparam</span>
|
|
<a name="l02093"></a>02093 <span class="vhdlchar">an_ram_inst</span>.<span class="vhdlchar">operation_mode</span> = <span class="keyword">"SINGLE_PORT"</span>,
|
|
<a name="l02094"></a>02094 <span class="vhdlchar">an_ram_inst</span>.<span class="vhdlchar">width_a</span> = <span class="vhdllogic">32</span>,
|
|
<a name="l02095"></a>02095 <span class="vhdlchar">an_ram_inst</span>.<span class="vhdlchar">widthad_a</span> = <span class="vhdllogic">3</span>,
|
|
<a name="l02096"></a>02096 <span class="vhdlchar">an_ram_inst</span>.<span class="vhdlchar">width_byteena_a</span> = <span class="vhdllogic">4</span>;
|
|
<a name="l02097"></a>02097
|
|
<a name="l02098"></a>02098 <span class="keyword">// Register set Dn implemented as RAM.</span>
|
|
<a name="l02099"></a><a class="code" href="classmemory__registers.html#a5b0f1fb5a259a06899ac6ac3b52835e0">02099</a> <a class="code" href="classmemory__registers.html#a892186b1bfe856b1ddaf1d8b3a448f50">altsyncram</a> <span class="vhdlchar">dn_ram_inst</span>(
|
|
<a name="l02100"></a>02100 .<span class="vhdlchar">clock0</span> (<a class="code" href="classmemory__registers.html#a06690d046213efc68334643946af2b16">clock</a>),
|
<a name="l02101"></a>02101
|
<a name="l02101"></a>02101
|
<a name="l02102"></a><a class="code" href="classmemory__registers.html#a49af6a7e50d837d339f79765aa2b9ee7">02102</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmemory__registers.html#a49af6a7e50d837d339f79765aa2b9ee7">An_ram_output</a>;
|
<a name="l02102"></a>02102 .<span class="vhdlchar">address_a</span> (<a class="code" href="classmemory__registers.html#a3faa61795c758b3d444c082be9ac5758">Dn_address</a>),
|
<a name="l02103"></a>02103 <span class="vhdlkeyword">assign</span> <a class="code" href="classmemory__registers.html#a806c8f12e4600aa02e87d61e072eb6e4">An_output</a> = (<a class="code" href="classmemory__registers.html#a8a67810353708d3652f619623692a545">An_address</a> == <span class="vhdllogic">4'b0111</span>) ? <a class="code" href="classmemory__registers.html#a736b71ba5d8851ef8e883408751c9380">usp</a> : <a class="code" href="classmemory__registers.html#a49af6a7e50d837d339f79765aa2b9ee7">An_ram_output</a>;
|
<a name="l02103"></a>02103 .<span class="vhdlchar">byteena_a</span> (<a class="code" href="classmemory__registers.html#a6d1775137e4a2f6a96e0cf49b76dc524">dn_byteena</a>),
|
<a name="l02104"></a>02104
|
<a name="l02104"></a>02104 .<span class="vhdlchar">wren_a</span> (<a class="code" href="classmemory__registers.html#a04d4474459a5b178f532443990dc10ed">Dn_write_enable</a>),
|
<a name="l02105"></a><a class="code" href="classmemory__registers.html#a6d1775137e4a2f6a96e0cf49b76dc524">02105</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmemory__registers.html#a6d1775137e4a2f6a96e0cf49b76dc524">dn_byteena</a> = (<a class="code" href="classmemory__registers.html#aa007104c0e9ef230ac07ad5b242ca8b5">Dn_size</a>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) ? <span class="vhdllogic">4'b0001</span> :
|
<a name="l02105"></a>02105 .<span class="vhdlchar">data_a</span> (<a class="code" href="classmemory__registers.html#a87f20385b6a12cc8249588a492930b31">Dn_input</a>),
|
<a name="l02106"></a>02106 (<a class="code" href="classmemory__registers.html#aa007104c0e9ef230ac07ad5b242ca8b5">Dn_size</a>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) ? <span class="vhdllogic">4'b0011</span> :
|
<a name="l02106"></a>02106 .<span class="vhdlchar">q_a</span> (<a class="code" href="classmemory__registers.html#a2c906a8760a85b5370b8c7f56dc4e6f3">Dn_output</a>)
|
<a name="l02107"></a>02107 (<a class="code" href="classmemory__registers.html#aa007104c0e9ef230ac07ad5b242ca8b5">Dn_size</a>[<span class="vhdllogic">2</span>] == <span class="vhdllogic">1'b1</span>) ? <span class="vhdllogic">4'b1111</span> :
|
<a name="l02107"></a>02107 );
|
<a name="l02108"></a>02108 <span class="vhdllogic">4'b0000</span>;
|
<a name="l02108"></a>02108 <span class="vhdlkeyword">defparam</span>
|
<a name="l02109"></a>02109
|
<a name="l02109"></a>02109 <span class="vhdlchar">dn_ram_inst</span>.<span class="vhdlchar">operation_mode</span> = <span class="keyword">"SINGLE_PORT"</span>,
|
<a name="l02110"></a><a class="code" href="classmemory__registers.html#a09281e3224878c570c81844785844fe0">02110</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classmemory__registers.html#a06690d046213efc68334643946af2b16">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classmemory__registers.html#a52bffc13966ddfc557c3c3a2cece1d97">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l02110"></a>02110 <span class="vhdlchar">dn_ram_inst</span>.<span class="vhdlchar">width_a</span> = <span class="vhdllogic">32</span>,
|
<a name="l02111"></a>02111 <span class="vhdlkeyword">if</span>(<a class="code" href="classmemory__registers.html#a52bffc13966ddfc557c3c3a2cece1d97">reset_n</a> == <span class="vhdllogic">1'b0</span>) <a class="code" href="classmemory__registers.html#a736b71ba5d8851ef8e883408751c9380">usp</a> <= <span class="vhdllogic">32'd0</span>;
|
<a name="l02111"></a>02111 <span class="vhdlchar">dn_ram_inst</span>.<span class="vhdlchar">widthad_a</span> = <span class="vhdllogic">3</span>,
|
<a name="l02112"></a>02112 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classmemory__registers.html#a8a67810353708d3652f619623692a545">An_address</a> == <span class="vhdllogic">4'b0111</span> && <a class="code" href="classmemory__registers.html#af97dfc643a2fa9ae191cb68acb23ea91">An_write_enable</a>) <a class="code" href="classmemory__registers.html#a736b71ba5d8851ef8e883408751c9380">usp</a> <= <a class="code" href="classmemory__registers.html#a8e3deabb065d3e6aaaf647a83e7c84e9">An_input</a>;
|
<a name="l02112"></a>02112 <span class="vhdlchar">dn_ram_inst</span>.<span class="vhdlchar">width_byteena_a</span> = <span class="vhdllogic">4</span>;
|
<a name="l02113"></a>02113 <span class="vhdlkeyword">end</span>
|
<a name="l02113"></a>02113
|
<a name="l02114"></a>02114
|
<a name="l02114"></a>02114 <span class="keyword">// Microcode ROM</span>
|
<a name="l02115"></a>02115 <span class="keyword">// Register set An implemented as RAM.</span>
|
<a name="l02115"></a><a class="code" href="classmemory__registers.html#afc54073a43b749eb1f1376c4b31cd1e3">02115</a> <a class="code" href="classmemory__registers.html#a892186b1bfe856b1ddaf1d8b3a448f50">altsyncram</a> <span class="vhdlchar">micro_rom_inst</span>(
|
<a name="l02116"></a><a class="code" href="classmemory__registers.html#a892186b1bfe856b1ddaf1d8b3a448f50">02116</a> <a class="code" href="classmemory__registers.html#a892186b1bfe856b1ddaf1d8b3a448f50">altsyncram</a> <span class="vhdlchar">an_ram_inst</span>(
|
<a name="l02116"></a>02116 .<span class="vhdlchar">clock0</span> (<a class="code" href="classmemory__registers.html#a06690d046213efc68334643946af2b16">clock</a>),
|
<a name="l02117"></a>02117 .<span class="vhdlchar">clock0</span> (<a class="code" href="classmemory__registers.html#a06690d046213efc68334643946af2b16">clock</a>),
|
<a name="l02117"></a>02117
|
<a name="l02118"></a>02118
|
<a name="l02118"></a>02118 .<span class="vhdlchar">address_a</span> (<a class="code" href="classmemory__registers.html#ac8716768ab1d64ea847be358444da7ee">micro_pc</a>),
|
<a name="l02119"></a>02119 .<span class="vhdlchar">address_a</span> (<a class="code" href="classmemory__registers.html#a8a67810353708d3652f619623692a545">An_address</a>[<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>]),
|
<a name="l02119"></a>02119 .<span class="vhdlchar">q_a</span> (<a class="code" href="classmemory__registers.html#ad13be4dbb1d8afc5ea1f9b5e8bb80e3c">micro_data</a>)
|
<a name="l02120"></a>02120 .<span class="vhdlchar">byteena_a</span> (<span class="vhdllogic">4'b1111</span>),
|
<a name="l02120"></a>02120 );
|
<a name="l02121"></a>02121 .<span class="vhdlchar">wren_a</span> (<a class="code" href="classmemory__registers.html#a2d55f5fd1b27c45d04af9b19559c2ae9">An_ram_write_enable</a>),
|
<a name="l02121"></a>02121 <span class="vhdlkeyword">defparam</span>
|
<a name="l02122"></a>02122 .<span class="vhdlchar">data_a</span> (<a class="code" href="classmemory__registers.html#a8e3deabb065d3e6aaaf647a83e7c84e9">An_input</a>),
|
<a name="l02122"></a>02122 <span class="vhdlchar">micro_rom_inst</span>.<span class="vhdlchar">operation_mode</span> = <span class="keyword">"ROM"</span>,
|
<a name="l02123"></a>02123 .<span class="vhdlchar">q_a</span> (<a class="code" href="classmemory__registers.html#a49af6a7e50d837d339f79765aa2b9ee7">An_ram_output</a>)
|
<a name="l02123"></a>02123 <span class="vhdlchar">micro_rom_inst</span>.<span class="vhdlchar">width_a</span> = <span class="vhdllogic">88</span>,
|
<a name="l02124"></a>02124 );
|
<a name="l02124"></a>02124 <span class="vhdlchar">micro_rom_inst</span>.<span class="vhdlchar">widthad_a</span> = <span class="vhdllogic">9</span>,
|
<a name="l02125"></a>02125 <span class="vhdlkeyword">defparam</span>
|
<a name="l02125"></a>02125 <span class="vhdlchar">micro_rom_inst</span>.<span class="vhdlchar">init_file</span> = <span class="keyword">"ao68000_microcode.mif"</span>;
|
<a name="l02126"></a>02126 <span class="vhdlchar">an_ram_inst</span>.<span class="vhdlchar">operation_mode</span> = <span class="keyword">"SINGLE_PORT"</span>,
|
<a name="l02126"></a>02126
|
<a name="l02127"></a>02127 <span class="vhdlchar">an_ram_inst</span>.<span class="vhdlchar">width_a</span> = <span class="vhdllogic">32</span>,
|
<a name="l02127"></a>02127 <span class="vhdlkeyword">endmodule</span>
|
<a name="l02128"></a>02128 <span class="vhdlchar">an_ram_inst</span>.<span class="vhdlchar">widthad_a</span> = <span class="vhdllogic">3</span>,
|
<a name="l02128"></a>02128
|
<a name="l02129"></a>02129 <span class="vhdlchar">an_ram_inst</span>.<span class="vhdlchar">width_byteena_a</span> = <span class="vhdllogic">4</span>;
|
<a name="l02129"></a>02129 <span class="keyword">/***********************************************************************************************************************</span>
|
<a name="l02130"></a>02130
|
<a name="l02130"></a>02130 <span class="keyword"> Instruction decoder</span>
|
<a name="l02131"></a>02131 <span class="keyword">// Register set Dn implemented as RAM.</span>
|
<a name="l02131"></a>02131 <span class="keyword"> ***********************************************************************************************************************/</span>
|
<a name="l02132"></a><a class="code" href="classmemory__registers.html#a5b0f1fb5a259a06899ac6ac3b52835e0">02132</a> <a class="code" href="classmemory__registers.html#a892186b1bfe856b1ddaf1d8b3a448f50">altsyncram</a> <span class="vhdlchar">dn_ram_inst</span>(
|
<a name="l02132"></a>02132
|
<a name="l02133"></a>02133 .<span class="vhdlchar">clock0</span> (<a class="code" href="classmemory__registers.html#a06690d046213efc68334643946af2b16">clock</a>),
|
<a name="l02133"></a>02133
|
<a name="l02134"></a>02134
|
<a name="l02143"></a><a class="code" href="classdecoder.html">02143</a> <span class="vhdlkeyword">module</span> <a class="code" href="classdecoder.html">decoder</a>(
|
<a name="l02135"></a>02135 .<span class="vhdlchar">address_a</span> (<a class="code" href="classmemory__registers.html#a3faa61795c758b3d444c082be9ac5758">Dn_address</a>),
|
<a name="l02144"></a><a class="code" href="classdecoder.html#a07ea698e43905b149515da25bf07d981">02144</a> <span class="vhdlkeyword">input</span> <a class="code" href="classdecoder.html#a07ea698e43905b149515da25bf07d981">clock</a>,
|
<a name="l02136"></a>02136 .<span class="vhdlchar">byteena_a</span> (<a class="code" href="classmemory__registers.html#a6d1775137e4a2f6a96e0cf49b76dc524">dn_byteena</a>),
|
<a name="l02145"></a><a class="code" href="classdecoder.html#abe8ffab56eaa2b729b293fab145b88da">02145</a> <span class="vhdlkeyword">input</span> <a class="code" href="classdecoder.html#abe8ffab56eaa2b729b293fab145b88da">reset_n</a>,
|
<a name="l02137"></a>02137 .<span class="vhdlchar">wren_a</span> (<a class="code" href="classmemory__registers.html#a04d4474459a5b178f532443990dc10ed">Dn_write_enable</a>),
|
|
<a name="l02138"></a>02138 .<span class="vhdlchar">data_a</span> (<a class="code" href="classmemory__registers.html#a87f20385b6a12cc8249588a492930b31">Dn_input</a>),
|
|
<a name="l02139"></a>02139 .<span class="vhdlchar">q_a</span> (<a class="code" href="classmemory__registers.html#a2c906a8760a85b5370b8c7f56dc4e6f3">Dn_output</a>)
|
|
<a name="l02140"></a>02140 );
|
|
<a name="l02141"></a>02141 <span class="vhdlkeyword">defparam</span>
|
|
<a name="l02142"></a>02142 <span class="vhdlchar">dn_ram_inst</span>.<span class="vhdlchar">operation_mode</span> = <span class="keyword">"SINGLE_PORT"</span>,
|
|
<a name="l02143"></a>02143 <span class="vhdlchar">dn_ram_inst</span>.<span class="vhdlchar">width_a</span> = <span class="vhdllogic">32</span>,
|
|
<a name="l02144"></a>02144 <span class="vhdlchar">dn_ram_inst</span>.<span class="vhdlchar">widthad_a</span> = <span class="vhdllogic">3</span>,
|
|
<a name="l02145"></a>02145 <span class="vhdlchar">dn_ram_inst</span>.<span class="vhdlchar">width_byteena_a</span> = <span class="vhdllogic">4</span>;
|
|
<a name="l02146"></a>02146
|
<a name="l02146"></a>02146
|
<a name="l02147"></a>02147 <span class="keyword">// Microcode ROM</span>
|
<a name="l02147"></a><a class="code" href="classdecoder.html#ab1195d70746a685dab833ac1e4943013">02147</a> <span class="vhdlkeyword">input</span> <a class="code" href="classdecoder.html#ab1195d70746a685dab833ac1e4943013">supervisor</a>,
|
<a name="l02148"></a><a class="code" href="classmemory__registers.html#afc54073a43b749eb1f1376c4b31cd1e3">02148</a> <a class="code" href="classmemory__registers.html#a892186b1bfe856b1ddaf1d8b3a448f50">altsyncram</a> <span class="vhdlchar">micro_rom_inst</span>(
|
<a name="l02148"></a><a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">02148</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>,
|
<a name="l02149"></a>02149 .<span class="vhdlchar">clock0</span> (<a class="code" href="classmemory__registers.html#a06690d046213efc68334643946af2b16">clock</a>),
|
<a name="l02149"></a>02149
|
<a name="l02150"></a>02150
|
<a name="l02150"></a>02150 <span class="keyword">// zero: no trap</span>
|
<a name="l02151"></a>02151 .<span class="vhdlchar">address_a</span> (<a class="code" href="classmemory__registers.html#ac8716768ab1d64ea847be358444da7ee">micro_pc</a>),
|
<a name="l02151"></a><a class="code" href="classdecoder.html#a3d51c77a26f72054bae55e07c4a7f50e">02151</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdecoder.html#a3d51c77a26f72054bae55e07c4a7f50e">decoder_trap</a>,
|
<a name="l02152"></a>02152 .<span class="vhdlchar">q_a</span> (<a class="code" href="classmemory__registers.html#ad13be4dbb1d8afc5ea1f9b5e8bb80e3c">micro_data</a>)
|
<a name="l02152"></a><a class="code" href="classdecoder.html#a17efa6a9faa1bd8ea90966c7127c4aad">02152</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdecoder.html#a17efa6a9faa1bd8ea90966c7127c4aad">decoder_micropc</a>,
|
<a name="l02153"></a>02153 );
|
<a name="l02153"></a>02153
|
<a name="l02154"></a>02154 <span class="vhdlkeyword">defparam</span>
|
<a name="l02154"></a><a class="code" href="classdecoder.html#a8f1fa508fbad7ecd8f15a47ac97be0dc">02154</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdecoder.html#a8f1fa508fbad7ecd8f15a47ac97be0dc">save_ea</a>,
|
<a name="l02155"></a>02155 <span class="vhdlchar">micro_rom_inst</span>.<span class="vhdlchar">operation_mode</span> = <span class="keyword">"ROM"</span>,
|
<a name="l02155"></a><a class="code" href="classdecoder.html#a0a10ac646012973ca8a578403894590e">02155</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdecoder.html#a0a10ac646012973ca8a578403894590e">perform_ea_write</a>,
|
<a name="l02156"></a>02156 <span class="vhdlchar">micro_rom_inst</span>.<span class="vhdlchar">width_a</span> = <span class="vhdllogic">88</span>,
|
<a name="l02156"></a><a class="code" href="classdecoder.html#a0081e82b20c0976ecb13d48dcc0f7554">02156</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdecoder.html#a0081e82b20c0976ecb13d48dcc0f7554">perform_ea_read</a>,
|
<a name="l02157"></a>02157 <span class="vhdlchar">micro_rom_inst</span>.<span class="vhdlchar">widthad_a</span> = <span class="vhdllogic">9</span>,
|
<a name="l02157"></a><a class="code" href="classdecoder.html#a37c251ae6bb47dd4f8a844cfc8f0757b">02157</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdecoder.html#a37c251ae6bb47dd4f8a844cfc8f0757b">load_ea</a>,
|
<a name="l02158"></a>02158 <span class="vhdlchar">micro_rom_inst</span>.<span class="vhdlchar">init_file</span> = <span class="keyword">"ao68000_microcode.mif"</span>;
|
<a name="l02158"></a>02158
|
<a name="l02159"></a>02159
|
<a name="l02159"></a><a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">02159</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a>,
|
<a name="l02160"></a>02160 <span class="vhdlkeyword">endmodule</span>
|
<a name="l02160"></a><a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">02160</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a>,
|
<a name="l02161"></a>02161
|
<a name="l02161"></a><a class="code" href="classdecoder.html#ab7e5c6aab518d6f4ffb374d0d70774ed">02161</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdecoder.html#ab7e5c6aab518d6f4ffb374d0d70774ed">ea_reg</a>
|
<a name="l02162"></a>02162 <span class="keyword">/***********************************************************************************************************************</span>
|
<a name="l02162"></a>02162 );
|
<a name="l02163"></a>02163 <span class="keyword"> Instruction decoder</span>
|
<a name="l02163"></a>02163
|
<a name="l02164"></a>02164 <span class="keyword"> ***********************************************************************************************************************/</span>
|
<a name="l02164"></a><a class="code" href="classdecoder.html#a269c8223e03f340fbe89513326d22891">02164</a> <span class="vhdlkeyword">parameter</span> [<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>]
|
<a name="l02165"></a>02165
|
<a name="l02165"></a>02165 <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a> = <span class="vhdllogic">8'd0</span>,
|
<a name="l02166"></a>02166
|
<a name="l02166"></a>02166 <a class="code" href="classdecoder.html#ae700aab6efd1c75556aeb4237f1d8c33">ILLEGAL_INSTRUCTION_TRAP</a> = <span class="vhdllogic">8'd4</span>,
|
<a name="l02176"></a><a class="code" href="classdecoder.html">02176</a> <span class="vhdlkeyword">module</span> <a class="code" href="classdecoder.html">decoder</a>(
|
<a name="l02167"></a>02167 <a class="code" href="classdecoder.html#a6313ac7ffe9e5484093212a53689d4f0">PRIVILEGE_VIOLATION_TRAP</a> = <span class="vhdllogic">8'd8</span>,
|
<a name="l02177"></a><a class="code" href="classdecoder.html#a07ea698e43905b149515da25bf07d981">02177</a> <span class="vhdlkeyword">input</span> <a class="code" href="classdecoder.html#a07ea698e43905b149515da25bf07d981">clock</a>,
|
<a name="l02168"></a>02168 <a class="code" href="classdecoder.html#a40d58c5cecf313424f9df4928b33d9f4">ILLEGAL_1010_INSTRUCTION_TRAP</a> = <span class="vhdllogic">8'd10</span>,
|
<a name="l02178"></a><a class="code" href="classdecoder.html#abe8ffab56eaa2b729b293fab145b88da">02178</a> <span class="vhdlkeyword">input</span> <a class="code" href="classdecoder.html#abe8ffab56eaa2b729b293fab145b88da">reset_n</a>,
|
<a name="l02169"></a>02169 <a class="code" href="classdecoder.html#a269c8223e03f340fbe89513326d22891">ILLEGAL_1111_INSTRUCTION_TRAP</a> = <span class="vhdllogic">8'd11</span>;
|
<a name="l02179"></a>02179
|
<a name="l02170"></a>02170
|
<a name="l02180"></a><a class="code" href="classdecoder.html#ab1195d70746a685dab833ac1e4943013">02180</a> <span class="vhdlkeyword">input</span> <a class="code" href="classdecoder.html#ab1195d70746a685dab833ac1e4943013">supervisor</a>,
|
<a name="l02171"></a><a class="code" href="classdecoder.html#aa6cefc0d2e58f3efccca7b784c2c9551">02171</a> <span class="vhdlkeyword">parameter</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>]
|
<a name="l02181"></a><a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">02181</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>,
|
<a name="l02172"></a>02172 <a class="code" href="classdecoder.html#aa6cefc0d2e58f3efccca7b784c2c9551">UNUSED_MICROPC</a> = <span class="vhdllogic">9'd0</span>;
|
<a name="l02182"></a>02182
|
<a name="l02173"></a>02173
|
<a name="l02183"></a>02183 <span class="keyword">// zero: no trap</span>
|
<a name="l02174"></a>02174 <span class="vhdlkeyword">assign</span> { <a class="code" href="classdecoder.html#a3d51c77a26f72054bae55e07c4a7f50e">decoder_trap</a>, <a class="code" href="classdecoder.html#a17efa6a9faa1bd8ea90966c7127c4aad">decoder_micropc</a> } =
|
<a name="l02184"></a><a class="code" href="classdecoder.html#a3d51c77a26f72054bae55e07c4a7f50e">02184</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdecoder.html#a3d51c77a26f72054bae55e07c4a7f50e">decoder_trap</a>,
|
<a name="l02175"></a>02175 (<a class="code" href="classdecoder.html#abe8ffab56eaa2b729b293fab145b88da">reset_n</a> == <span class="vhdllogic">1'b0</span>) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="classdecoder.html#aa6cefc0d2e58f3efccca7b784c2c9551">UNUSED_MICROPC</a> } :
|
<a name="l02185"></a><a class="code" href="classdecoder.html#a17efa6a9faa1bd8ea90966c7127c4aad">02185</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdecoder.html#a17efa6a9faa1bd8ea90966c7127c4aad">decoder_micropc</a>,
|
<a name="l02176"></a>02176
|
<a name="l02186"></a>02186
|
<a name="l02177"></a>02177 <span class="keyword">// Privilege violation and illegal instruction</span>
|
<a name="l02187"></a><a class="code" href="classdecoder.html#a8f1fa508fbad7ecd8f15a47ac97be0dc">02187</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdecoder.html#a8f1fa508fbad7ecd8f15a47ac97be0dc">save_ea</a>,
|
<a name="l02178"></a>02178
|
<a name="l02188"></a><a class="code" href="classdecoder.html#a0a10ac646012973ca8a578403894590e">02188</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdecoder.html#a0a10ac646012973ca8a578403894590e">perform_ea_write</a>,
|
<a name="l02179"></a>02179 <span class="keyword">// ANDI to SR,EORI to SR,ORI to SR,RESET,STOP,RTE,MOVE TO SR,MOVE USP TO USP,MOVE USP TO An privileged instructions</span>
|
<a name="l02189"></a><a class="code" href="classdecoder.html#a0081e82b20c0976ecb13d48dcc0f7554">02189</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdecoder.html#a0081e82b20c0976ecb13d48dcc0f7554">perform_ea_read</a>,
|
<a name="l02180"></a>02180 ( ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_0010_01_111_100</span> ||
|
<a name="l02190"></a><a class="code" href="classdecoder.html#a37c251ae6bb47dd4f8a844cfc8f0757b">02190</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdecoder.html#a37c251ae6bb47dd4f8a844cfc8f0757b">load_ea</a>,
|
<a name="l02181"></a>02181 <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_1010_01_111_100</span> ||
|
<a name="l02191"></a>02191
|
<a name="l02182"></a>02182 <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_0000_01_111_100</span> ||
|
<a name="l02192"></a><a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">02192</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a>,
|
<a name="l02183"></a>02183 <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0100_1110_0111_0000</span> ||
|
<a name="l02193"></a><a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">02193</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a>,
|
<a name="l02184"></a>02184 <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0100_1110_0111_0010</span> ||
|
<a name="l02194"></a><a class="code" href="classdecoder.html#ab7e5c6aab518d6f4ffb374d0d70774ed">02194</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdecoder.html#ab7e5c6aab518d6f4ffb374d0d70774ed">ea_reg</a>
|
<a name="l02185"></a>02185 <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0100_1110_0111_0011</span> ||
|
<a name="l02195"></a>02195 );
|
<a name="l02186"></a>02186 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">10'b0100_0110_11</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] != <span class="vhdllogic">6'b111_101</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] != <span class="vhdllogic">6'b111_110</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] != <span class="vhdllogic">6'b111_111</span>) ||
|
<a name="l02196"></a>02196
|
<a name="l02187"></a>02187 <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">13'b0100_1110_0110_0</span> ||
|
<a name="l02197"></a><a class="code" href="classdecoder.html#a269c8223e03f340fbe89513326d22891">02197</a> <span class="vhdlkeyword">parameter</span> [<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>]
|
<a name="l02188"></a>02188 <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">13'b0100_1110_0110_1</span> ) && <a class="code" href="classdecoder.html#ab1195d70746a685dab833ac1e4943013">supervisor</a> == <span class="vhdllogic">1'b0</span> ) ? { <a class="code" href="classdecoder.html#a6313ac7ffe9e5484093212a53689d4f0">PRIVILEGE_VIOLATION_TRAP</a>, <a class="code" href="classdecoder.html#aa6cefc0d2e58f3efccca7b784c2c9551">UNUSED_MICROPC</a> } :
|
<a name="l02198"></a>02198 <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a> = <span class="vhdllogic">8'd0</span>,
|
<a name="l02189"></a>02189 <span class="keyword">// ILLEGAL, illegal instruction</span>
|
<a name="l02199"></a>02199 <a class="code" href="classdecoder.html#ae700aab6efd1c75556aeb4237f1d8c33">ILLEGAL_INSTRUCTION_TRAP</a> = <span class="vhdllogic">8'd4</span>,
|
<a name="l02190"></a>02190 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0100_1010_11_111100</span> ) ? { <a class="code" href="classdecoder.html#ae700aab6efd1c75556aeb4237f1d8c33">ILLEGAL_INSTRUCTION_TRAP</a>, <a class="code" href="classdecoder.html#aa6cefc0d2e58f3efccca7b784c2c9551">UNUSED_MICROPC</a> } :
|
<a name="l02200"></a>02200 <a class="code" href="classdecoder.html#a6313ac7ffe9e5484093212a53689d4f0">PRIVILEGE_VIOLATION_TRAP</a> = <span class="vhdllogic">8'd8</span>,
|
<a name="l02191"></a>02191 <span class="keyword">// 1010 illegal instruction</span>
|
<a name="l02201"></a>02201 <a class="code" href="classdecoder.html#a40d58c5cecf313424f9df4928b33d9f4">ILLEGAL_1010_INSTRUCTION_TRAP</a> = <span class="vhdllogic">8'd10</span>,
|
<a name="l02192"></a>02192 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1010</span> ) ? { <a class="code" href="classdecoder.html#a40d58c5cecf313424f9df4928b33d9f4">ILLEGAL_1010_INSTRUCTION_TRAP</a>, <a class="code" href="classdecoder.html#aa6cefc0d2e58f3efccca7b784c2c9551">UNUSED_MICROPC</a> } :
|
<a name="l02202"></a>02202 <a class="code" href="classdecoder.html#a269c8223e03f340fbe89513326d22891">ILLEGAL_1111_INSTRUCTION_TRAP</a> = <span class="vhdllogic">8'd11</span>;
|
<a name="l02193"></a>02193 <span class="keyword">// 1111 illegal instruction</span>
|
<a name="l02203"></a>02203
|
<a name="l02194"></a>02194 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1111</span> ) ? { <a class="code" href="classdecoder.html#a269c8223e03f340fbe89513326d22891">ILLEGAL_1111_INSTRUCTION_TRAP</a>, <a class="code" href="classdecoder.html#aa6cefc0d2e58f3efccca7b784c2c9551">UNUSED_MICROPC</a> } :
|
<a name="l02204"></a><a class="code" href="classdecoder.html#aa6cefc0d2e58f3efccca7b784c2c9551">02204</a> <span class="vhdlkeyword">parameter</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>]
|
<a name="l02195"></a>02195
|
<a name="l02205"></a>02205 <a class="code" href="classdecoder.html#aa6cefc0d2e58f3efccca7b784c2c9551">UNUSED_MICROPC</a> = <span class="vhdllogic">9'd0</span>;
|
<a name="l02196"></a>02196 <span class="keyword">// instruction decoding</span>
|
<a name="l02206"></a>02206
|
<a name="l02197"></a>02197
|
<a name="l02207"></a>02207 <span class="vhdlkeyword">assign</span> { <a class="code" href="classdecoder.html#a3d51c77a26f72054bae55e07c4a7f50e">decoder_trap</a>, <a class="code" href="classdecoder.html#a17efa6a9faa1bd8ea90966c7127c4aad">decoder_micropc</a> } =
|
<a name="l02198"></a>02198 <span class="keyword">// ANDI,EORI,ORI,ADDI,SUBI</span>
|
<a name="l02208"></a>02208 (<a class="code" href="classdecoder.html#abe8ffab56eaa2b729b293fab145b88da">reset_n</a> == <span class="vhdllogic">1'b0</span>) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="classdecoder.html#aa6cefc0d2e58f3efccca7b784c2c9551">UNUSED_MICROPC</a> } :
|
<a name="l02199"></a>02199 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] != <span class="vhdllogic">3'b100</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] != <span class="vhdllogic">3'b110</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] != <span class="vhdllogic">3'b111</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b0</span> &&
|
<a name="l02209"></a>02209
|
<a name="l02200"></a>02200 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b00</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b01</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b10</span>) && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> &&
|
<a name="l02210"></a>02210 <span class="keyword">// Privilege violation and illegal instruction</span>
|
<a name="l02201"></a>02201 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> || (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span>)) &&
|
<a name="l02211"></a>02211
|
<a name="l02202"></a>02202 <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] != <span class="vhdllogic">16'b0000_000_0_00_111100</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] != <span class="vhdllogic">16'b0000_000_0_01_111100</span> &&
|
<a name="l02212"></a>02212 <span class="keyword">// ANDI to SR,EORI to SR,ORI to SR,RESET,STOP,RTE,MOVE TO SR,MOVE USP TO USP,MOVE USP TO An privileged instructions</span>
|
<a name="l02203"></a>02203 <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] != <span class="vhdllogic">16'b0000_001_0_00_111100</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] != <span class="vhdllogic">16'b0000_001_0_01_111100</span> &&
|
<a name="l02213"></a>02213 ( ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_0010_01_111_100</span> ||
|
<a name="l02204"></a>02204 <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] != <span class="vhdllogic">16'b0000_101_0_00_111100</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] != <span class="vhdllogic">16'b0000_101_0_01_111100</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a1508cd79053f2766a7bd8b7932ffdf0c">`MICROPC_ANDI_EORI_ORI_ADDI_SUBI</a><span class="vhdlchar"></span> } :
|
<a name="l02214"></a>02214 <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_1010_01_111_100</span> ||
|
<a name="l02205"></a>02205 <span class="keyword">// ORI to CCR,ORI to SR,ANDI to CCR,ANDI to SR,EORI to CCR,EORI to SR</span>
|
<a name="l02215"></a>02215 <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_0000_01_111_100</span> ||
|
<a name="l02206"></a>02206 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_000_0_00_111100</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_000_0_01_111100</span> ||
|
<a name="l02216"></a>02216 <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0100_1110_0111_0000</span> ||
|
<a name="l02207"></a>02207 <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_001_0_00_111100</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_001_0_01_111100</span> ||
|
<a name="l02217"></a>02217 <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0100_1110_0111_0010</span> ||
|
<a name="l02208"></a>02208 <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_101_0_00_111100</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_101_0_01_111100</span> ) ?
|
<a name="l02218"></a>02218 <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0100_1110_0111_0011</span> ||
|
<a name="l02209"></a>02209 { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#af7581a9c9f99af85388e542ad881d71f">`MICROPC_ORI_to_CCR_ORI_to_SR_ANDI_to_CCR_ANDI_to_SR_EORI_to_CCR_EORI_to_SR</a><span class="vhdlchar"></span> } :
|
<a name="l02219"></a>02219 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">10'b0100_0110_11</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] != <span class="vhdllogic">6'b111_101</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] != <span class="vhdllogic">6'b111_110</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] != <span class="vhdllogic">6'b111_111</span>) ||
|
<a name="l02210"></a>02210 <span class="keyword">// BTST register</span>
|
<a name="l02220"></a>02220 <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">13'b0100_1110_0110_0</span> ||
|
<a name="l02211"></a>02211 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b100</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> &&
|
<a name="l02221"></a>02221 <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">13'b0100_1110_0110_1</span> ) && <a class="code" href="classdecoder.html#ab1195d70746a685dab833ac1e4943013">supervisor</a> == <span class="vhdllogic">1'b0</span> ) ? { <a class="code" href="classdecoder.html#a6313ac7ffe9e5484093212a53689d4f0">PRIVILEGE_VIOLATION_TRAP</a>, <a class="code" href="classdecoder.html#aa6cefc0d2e58f3efccca7b784c2c9551">UNUSED_MICROPC</a> } :
|
<a name="l02212"></a>02212 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> ||
|
<a name="l02222"></a>02222 <span class="keyword">// ILLEGAL, illegal instruction</span>
|
<a name="l02213"></a>02213 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_011</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_100</span>))
|
<a name="l02223"></a>02223 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0100_1010_11_111100</span> ) ? { <a class="code" href="classdecoder.html#ae700aab6efd1c75556aeb4237f1d8c33">ILLEGAL_INSTRUCTION_TRAP</a>, <a class="code" href="classdecoder.html#aa6cefc0d2e58f3efccca7b784c2c9551">UNUSED_MICROPC</a> } :
|
<a name="l02214"></a>02214 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#aa2684e7883f516fe90229d1a02585c7c">`MICROPC_BTST_register</a><span class="vhdlchar"></span> } :
|
<a name="l02224"></a>02224 <span class="keyword">// 1010 illegal instruction</span>
|
<a name="l02215"></a>02215 <span class="keyword">// MOVEP memory to register</span>
|
<a name="l02225"></a>02225 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1010</span> ) ? { <a class="code" href="classdecoder.html#a40d58c5cecf313424f9df4928b33d9f4">ILLEGAL_1010_INSTRUCTION_TRAP</a>, <a class="code" href="classdecoder.html#aa6cefc0d2e58f3efccca7b784c2c9551">UNUSED_MICROPC</a> } :
|
<a name="l02216"></a>02216 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b1</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b001</span> && ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b00</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b01</span> ) ) ?
|
<a name="l02226"></a>02226 <span class="keyword">// 1111 illegal instruction</span>
|
<a name="l02217"></a>02217 { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a6827fab6e4b333e82a1de52cf6020b7a">`MICROPC_MOVEP_memory_to_register</a><span class="vhdlchar"></span> } :
|
<a name="l02227"></a>02227 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1111</span> ) ? { <a class="code" href="classdecoder.html#a269c8223e03f340fbe89513326d22891">ILLEGAL_1111_INSTRUCTION_TRAP</a>, <a class="code" href="classdecoder.html#aa6cefc0d2e58f3efccca7b784c2c9551">UNUSED_MICROPC</a> } :
|
<a name="l02218"></a>02218 <span class="keyword">// MOVEP register to memory</span>
|
<a name="l02228"></a>02228
|
<a name="l02219"></a>02219 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b1</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b001</span> && ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b10</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> ) ) ?
|
<a name="l02229"></a>02229 <span class="keyword">// instruction decoding</span>
|
<a name="l02220"></a>02220 { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a2516dd6bb3a4f804a752557b483e077b">`MICROPC_MOVEP_register_to_memory</a><span class="vhdlchar"></span> } :
|
<a name="l02230"></a>02230
|
<a name="l02221"></a>02221 <span class="keyword">// BCHG,BCLR,BSET register</span>
|
<a name="l02231"></a>02231 <span class="keyword">// ANDI,EORI,ORI,ADDI,SUBI</span>
|
<a name="l02222"></a>02222 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b1</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">3'b100</span> &&
|
<a name="l02232"></a>02232 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] != <span class="vhdllogic">3'b100</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] != <span class="vhdllogic">3'b110</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] != <span class="vhdllogic">3'b111</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b0</span> &&
|
<a name="l02223"></a>02223 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> || (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span>))
|
<a name="l02233"></a>02233 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b00</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b01</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b10</span>) && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> &&
|
<a name="l02224"></a>02224 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a5aff7e16fcd8e2f83c6a684fb62506b3">`MICROPC_BCHG_BCLR_BSET_register</a><span class="vhdlchar"></span> } :
|
<a name="l02234"></a>02234 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> || (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span>)) &&
|
<a name="l02225"></a>02225 <span class="keyword">// BTST immediate</span>
|
<a name="l02235"></a>02235 <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] != <span class="vhdllogic">16'b0000_000_0_00_111100</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] != <span class="vhdllogic">16'b0000_000_0_01_111100</span> &&
|
<a name="l02226"></a>02226 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b1000</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b00</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> &&
|
<a name="l02236"></a>02236 <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] != <span class="vhdllogic">16'b0000_001_0_00_111100</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] != <span class="vhdllogic">16'b0000_001_0_01_111100</span> &&
|
<a name="l02227"></a>02227 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> ||
|
<a name="l02237"></a>02237 <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] != <span class="vhdllogic">16'b0000_101_0_00_111100</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] != <span class="vhdllogic">16'b0000_101_0_01_111100</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a1508cd79053f2766a7bd8b7932ffdf0c">`MICROPC_ANDI_EORI_ORI_ADDI_SUBI</a><span class="vhdlchar"></span> } :
|
<a name="l02228"></a>02228 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_011</span>))
|
<a name="l02238"></a>02238 <span class="keyword">// ORI to CCR,ORI to SR,ANDI to CCR,ANDI to SR,EORI to CCR,EORI to SR</span>
|
<a name="l02229"></a>02229 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a5ec24a82d3f383ac90da0ad8cc7bb0e3">`MICROPC_BTST_immediate</a><span class="vhdlchar"></span> } :
|
<a name="l02239"></a>02239 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_000_0_00_111100</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_000_0_01_111100</span> ||
|
<a name="l02230"></a>02230 <span class="keyword">// BCHG,BCLR,BSET immediate</span>
|
<a name="l02240"></a>02240 <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_001_0_00_111100</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_001_0_01_111100</span> ||
|
<a name="l02231"></a>02231 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b1000</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b00</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> &&
|
<a name="l02241"></a>02241 <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_101_0_00_111100</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_101_0_01_111100</span> ) ?
|
<a name="l02232"></a>02232 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> || (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span>))
|
<a name="l02242"></a>02242 { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#af7581a9c9f99af85388e542ad881d71f">`MICROPC_ORI_to_CCR_ORI_to_SR_ANDI_to_CCR_ANDI_to_SR_EORI_to_CCR_EORI_to_SR</a><span class="vhdlchar"></span> } :
|
<a name="l02233"></a>02233 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a89a5e8fafa2da702e7c00cb6fe7c2066">`MICROPC_BCHG_BCLR_BSET_immediate</a><span class="vhdlchar"></span> } :
|
<a name="l02243"></a>02243 <span class="keyword">// BTST register</span>
|
<a name="l02234"></a>02234 <span class="keyword">// CMPI</span>
|
<a name="l02244"></a>02244 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b100</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> &&
|
<a name="l02235"></a>02235 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b0</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">3'b110</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> &&
|
<a name="l02245"></a>02245 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> ||
|
<a name="l02236"></a>02236 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> || (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span>))
|
<a name="l02246"></a>02246 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_011</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_100</span>))
|
<a name="l02237"></a>02237 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a5027ce5e621b327a8116e4ca0af34e90">`MICROPC_CMPI</a><span class="vhdlchar"></span> } :
|
<a name="l02247"></a>02247 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#aa2684e7883f516fe90229d1a02585c7c">`MICROPC_BTST_register</a><span class="vhdlchar"></span> } :
|
<a name="l02238"></a>02238 <span class="keyword">// MOVE</span>
|
<a name="l02248"></a>02248 <span class="keyword">// MOVEP memory to register</span>
|
<a name="l02239"></a>02239 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">14</span>] == <span class="vhdllogic">2'b00</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">12</span>] != <span class="vhdllogic">2'b00</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">3'b001</span> &&
|
<a name="l02249"></a>02249 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b1</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b001</span> && ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b00</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b01</span> ) ) ?
|
<a name="l02240"></a>02240 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">3'b111</span> || (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">6'b000_111</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">6'b001_111</span>)) &&
|
<a name="l02250"></a>02250 { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a6827fab6e4b333e82a1de52cf6020b7a">`MICROPC_MOVEP_memory_to_register</a><span class="vhdlchar"></span> } :
|
<a name="l02241"></a>02241 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">12</span>] != <span class="vhdllogic">2'b01</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span>) &&
|
<a name="l02251"></a>02251 <span class="keyword">// MOVEP register to memory</span>
|
<a name="l02242"></a>02242 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> ||
|
<a name="l02252"></a>02252 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b1</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b001</span> && ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b10</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> ) ) ?
|
<a name="l02243"></a>02243 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_011</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_100</span>))
|
<a name="l02253"></a>02253 { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a2516dd6bb3a4f804a752557b483e077b">`MICROPC_MOVEP_register_to_memory</a><span class="vhdlchar"></span> } :
|
<a name="l02244"></a>02244 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#afadd69027964ef6d7c9f923ed2714bbe">`MICROPC_MOVE</a><span class="vhdlchar"></span> } :
|
<a name="l02254"></a>02254 <span class="keyword">// BCHG,BCLR,BSET register</span>
|
<a name="l02245"></a>02245 <span class="keyword">// MOVEA</span>
|
<a name="l02255"></a>02255 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b1</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">3'b100</span> &&
|
<a name="l02246"></a>02246 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">14</span>] == <span class="vhdllogic">2'b00</span> && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">2'b11</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">2'b10</span>) && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b001</span> &&
|
<a name="l02256"></a>02256 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> || (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span>))
|
<a name="l02247"></a>02247 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> ||
|
<a name="l02257"></a>02257 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a5aff7e16fcd8e2f83c6a684fb62506b3">`MICROPC_BCHG_BCLR_BSET_register</a><span class="vhdlchar"></span> } :
|
<a name="l02248"></a>02248 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_011</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_100</span>))
|
<a name="l02258"></a>02258 <span class="keyword">// BTST immediate</span>
|
<a name="l02249"></a>02249 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a38b3d0769f31c2931ccc92e00af94884">`MICROPC_MOVEA</a><span class="vhdlchar"></span> } :
|
<a name="l02259"></a>02259 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b1000</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b00</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> &&
|
<a name="l02250"></a>02250 <span class="keyword">// NEGX,CLR,NEG,NOT,NBCD</span>
|
<a name="l02260"></a>02260 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> ||
|
<a name="l02251"></a>02251 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0100</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span>) &&
|
<a name="l02261"></a>02261 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_011</span>))
|
<a name="l02252"></a>02252 ( (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span>) || (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0010</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span>) ||
|
<a name="l02262"></a>02262 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a5ec24a82d3f383ac90da0ad8cc7bb0e3">`MICROPC_BTST_immediate</a><span class="vhdlchar"></span> } :
|
<a name="l02253"></a>02253 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0100</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span>) || (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0110</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span>) ||
|
<a name="l02263"></a>02263 <span class="keyword">// BCHG,BCLR,BSET immediate</span>
|
<a name="l02254"></a>02254 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">6'b1000_00</span>)
|
<a name="l02264"></a>02264 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b1000</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b00</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> &&
|
<a name="l02255"></a>02255 )
|
<a name="l02265"></a>02265 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> || (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span>))
|
<a name="l02256"></a>02256 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a6f040be4f69b57ba9603d5eae6085425">`MICROPC_NEGX_CLR_NEG_NOT_NBCD</a><span class="vhdlchar"></span> } :
|
<a name="l02266"></a>02266 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a89a5e8fafa2da702e7c00cb6fe7c2066">`MICROPC_BCHG_BCLR_BSET_immediate</a><span class="vhdlchar"></span> } :
|
<a name="l02257"></a>02257 <span class="keyword">// MOVE FROM SR</span>
|
<a name="l02267"></a>02267 <span class="keyword">// CMPI</span>
|
<a name="l02258"></a>02258 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">10'b0100_0000_11</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span>)
|
<a name="l02268"></a>02268 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b0</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">3'b110</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> &&
|
<a name="l02259"></a>02259 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a9527c313aa58c219b35f23dcfcd52a3a">`MICROPC_MOVE_FROM_SR</a><span class="vhdlchar"></span> } :
|
<a name="l02269"></a>02269 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> || (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span>))
|
<a name="l02260"></a>02260 <span class="keyword">// CHK</span>
|
<a name="l02270"></a>02270 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a5027ce5e621b327a8116e4ca0af34e90">`MICROPC_CMPI</a><span class="vhdlchar"></span> } :
|
<a name="l02261"></a>02261 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0100</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b110</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> &&
|
<a name="l02271"></a>02271 <span class="keyword">// MOVE</span>
|
<a name="l02262"></a>02262 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> ||
|
<a name="l02272"></a>02272 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">14</span>] == <span class="vhdllogic">2'b00</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">12</span>] != <span class="vhdllogic">2'b00</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">3'b001</span> &&
|
<a name="l02263"></a>02263 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_011</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_100</span>))
|
<a name="l02273"></a>02273 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">3'b111</span> || (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">6'b000_111</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">6'b001_111</span>)) &&
|
<a name="l02264"></a>02264 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a09d3064b3da754163f244a861ce4c758">`MICROPC_CHK</a><span class="vhdlchar"></span> } :
|
<a name="l02274"></a>02274 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">12</span>] != <span class="vhdllogic">2'b01</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span>) &&
|
<a name="l02265"></a>02265 <span class="keyword">// LEA</span>
|
<a name="l02275"></a>02275 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> ||
|
<a name="l02266"></a>02266 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0100</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b111</span> && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b101</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b110</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b111</span>) &&
|
<a name="l02276"></a>02276 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_011</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_100</span>))
|
<a name="l02267"></a>02267 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> ||
|
<a name="l02277"></a>02277 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#afadd69027964ef6d7c9f923ed2714bbe">`MICROPC_MOVE</a><span class="vhdlchar"></span> } :
|
<a name="l02268"></a>02268 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_011</span>))
|
<a name="l02278"></a>02278 <span class="keyword">// MOVEA</span>
|
<a name="l02269"></a>02269 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#aced982dae609932df5af323a07349a2b">`MICROPC_LEA</a><span class="vhdlchar"></span> } :
|
<a name="l02279"></a>02279 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">14</span>] == <span class="vhdllogic">2'b00</span> && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">2'b11</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">2'b10</span>) && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b001</span> &&
|
<a name="l02270"></a>02270 <span class="keyword">// MOVE TO CCR, MOVE TO SR</span>
|
<a name="l02280"></a>02280 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> ||
|
<a name="l02271"></a>02271 ( (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">10'b0100_0100_11</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">10'b0100_0110_11</span>) && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> &&
|
<a name="l02281"></a>02281 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_011</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_100</span>))
|
<a name="l02272"></a>02272 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> ||
|
<a name="l02282"></a>02282 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a38b3d0769f31c2931ccc92e00af94884">`MICROPC_MOVEA</a><span class="vhdlchar"></span> } :
|
<a name="l02273"></a>02273 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_011</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_100</span>))
|
<a name="l02283"></a>02283 <span class="keyword">// NEGX,CLR,NEG,NOT,NBCD</span>
|
<a name="l02274"></a>02274 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a258ae200cc2cbeccddff03ba18b66a27">`MICROPC_MOVE_TO_CCR_MOVE_TO_SR</a><span class="vhdlchar"></span> } :
|
<a name="l02284"></a>02284 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0100</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span>) &&
|
<a name="l02275"></a>02275 <span class="keyword">// SWAP,EXT</span>
|
<a name="l02285"></a>02285 ( (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span>) || (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0010</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span>) ||
|
<a name="l02276"></a>02276 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0100</span> && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">9'b1000_01_000</span> || (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">7</span>] == <span class="vhdllogic">5'b1000_1</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b000</span>) ) ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a65ca31e571d56e8b7e92ecadd58c94e1">`MICROPC_SWAP_EXT</a><span class="vhdlchar"></span> } :
|
<a name="l02286"></a>02286 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0100</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span>) || (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0110</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span>) ||
|
<a name="l02277"></a>02277 <span class="keyword">// PEA</span>
|
<a name="l02287"></a>02287 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">6'b1000_00</span>)
|
<a name="l02278"></a>02278 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">10'b0100_1000_01</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b000</span> && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b101</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b110</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b111</span>) &&
|
<a name="l02288"></a>02288 )
|
<a name="l02279"></a>02279 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> ||
|
<a name="l02289"></a>02289 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a6f040be4f69b57ba9603d5eae6085425">`MICROPC_NEGX_CLR_NEG_NOT_NBCD</a><span class="vhdlchar"></span> } :
|
<a name="l02280"></a>02280 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_011</span>))
|
<a name="l02290"></a>02290 <span class="keyword">// MOVE FROM SR</span>
|
<a name="l02281"></a>02281 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a2ce22f23bd95ba0ee7690a059448a357">`MICROPC_PEA</a><span class="vhdlchar"></span> } :
|
<a name="l02291"></a>02291 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">10'b0100_0000_11</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span>)
|
<a name="l02282"></a>02282 <span class="keyword">// MOVEM register to memory, predecrement</span>
|
<a name="l02292"></a>02292 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a9527c313aa58c219b35f23dcfcd52a3a">`MICROPC_MOVE_FROM_SR</a><span class="vhdlchar"></span> } :
|
<a name="l02283"></a>02283 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">7</span>] == <span class="vhdllogic">9'b0100_1000_1</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b100</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#affd3d4c8fd7cf2cbd78ecd99397f768b">`MICROPC_MOVEM_register_to_memory_predecrement</a><span class="vhdlchar"></span> } :
|
<a name="l02293"></a>02293 <span class="keyword">// CHK</span>
|
<a name="l02284"></a>02284 <span class="keyword">// MOVEM register to memory, control</span>
|
<a name="l02294"></a>02294 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0100</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b110</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> &&
|
<a name="l02285"></a>02285 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">7</span>] == <span class="vhdllogic">9'b0100_1000_1</span> && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b101</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b110</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b111</span>) &&
|
<a name="l02295"></a>02295 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> ||
|
<a name="l02286"></a>02286 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span>)
|
<a name="l02296"></a>02296 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_011</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_100</span>))
|
<a name="l02287"></a>02287 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a775df2459596100b0e801ad20c24322b">`MICROPC_MOVEM_register_to_memory_control</a><span class="vhdlchar"></span> } :
|
<a name="l02297"></a>02297 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a09d3064b3da754163f244a861ce4c758">`MICROPC_CHK</a><span class="vhdlchar"></span> } :
|
<a name="l02288"></a>02288 <span class="keyword">// TST</span>
|
<a name="l02298"></a>02298 <span class="keyword">// LEA</span>
|
<a name="l02289"></a>02289 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">8'b0100_1010</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> &&
|
<a name="l02299"></a>02299 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0100</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b111</span> && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b101</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b110</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b111</span>) &&
|
<a name="l02290"></a>02290 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> || (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span>))
|
<a name="l02300"></a>02300 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> ||
|
<a name="l02291"></a>02291 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a0c416458c758702471d503b0dbeab5d8">`MICROPC_TST</a><span class="vhdlchar"></span> } :
|
<a name="l02301"></a>02301 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_011</span>))
|
<a name="l02292"></a>02292 <span class="keyword">// TAS</span>
|
<a name="l02302"></a>02302 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#aced982dae609932df5af323a07349a2b">`MICROPC_LEA</a><span class="vhdlchar"></span> } :
|
<a name="l02293"></a>02293 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">10'b0100_1010_11</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> &&
|
<a name="l02303"></a>02303 <span class="keyword">// MOVE TO CCR, MOVE TO SR</span>
|
<a name="l02294"></a>02294 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> || (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span>))
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<a name="l02304"></a>02304 ( (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">10'b0100_0100_11</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">10'b0100_0110_11</span>) && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> &&
|
<a name="l02295"></a>02295 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a9d9308b3732ecf15f57a22600ac300b8">`MICROPC_TAS</a><span class="vhdlchar"></span> } :
|
<a name="l02305"></a>02305 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> ||
|
<a name="l02296"></a>02296 <span class="keyword">// MOVEM memory to register</span>
|
<a name="l02306"></a>02306 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_011</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_100</span>))
|
<a name="l02297"></a>02297 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">7</span>] == <span class="vhdllogic">9'b0100_1100_1</span> && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b011</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b101</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b110</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b111</span>) &&
|
<a name="l02307"></a>02307 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a258ae200cc2cbeccddff03ba18b66a27">`MICROPC_MOVE_TO_CCR_MOVE_TO_SR</a><span class="vhdlchar"></span> } :
|
<a name="l02298"></a>02298 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> ||
|
<a name="l02308"></a>02308 <span class="keyword">// SWAP,EXT</span>
|
<a name="l02299"></a>02299 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_011</span>))
|
<a name="l02309"></a>02309 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0100</span> && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">9'b1000_01_000</span> || (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">7</span>] == <span class="vhdllogic">5'b1000_1</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b000</span>) ) ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a65ca31e571d56e8b7e92ecadd58c94e1">`MICROPC_SWAP_EXT</a><span class="vhdlchar"></span> } :
|
<a name="l02300"></a>02300 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#ac2e6ac139e91da76695b3f953c994a0d">`MICROPC_MOVEM_memory_to_register</a><span class="vhdlchar"></span> } :
|
<a name="l02310"></a>02310 <span class="keyword">// PEA</span>
|
<a name="l02301"></a>02301 <span class="keyword">// TRAP</span>
|
<a name="l02311"></a>02311 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">10'b0100_1000_01</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b000</span> && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b101</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b110</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b111</span>) &&
|
<a name="l02302"></a>02302 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">12'b0100_1110_0100</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#aa106c5a18e8252dc2ced5ec2f77650d9">`MICROPC_TRAP</a><span class="vhdlchar"></span> } :
|
<a name="l02312"></a>02312 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> ||
|
<a name="l02303"></a>02303 <span class="keyword">// LINK</span>
|
<a name="l02313"></a>02313 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_011</span>))
|
<a name="l02304"></a>02304 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">13'b0100_1110_0101_0</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#af1b92ab55a321f316faf654b5d284caf">`MICROPC_LINK</a><span class="vhdlchar"></span> } :
|
<a name="l02314"></a>02314 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a2ce22f23bd95ba0ee7690a059448a357">`MICROPC_PEA</a><span class="vhdlchar"></span> } :
|
<a name="l02305"></a>02305 <span class="keyword">// UNLK</span>
|
<a name="l02315"></a>02315 <span class="keyword">// MOVEM register to memory, predecrement</span>
|
<a name="l02306"></a>02306 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">13'b0100_1110_0101_1</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a52c9810463f7dc671e021a7217259c04">`MICROPC_ULNK</a><span class="vhdlchar"></span> } :
|
<a name="l02316"></a>02316 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">7</span>] == <span class="vhdllogic">9'b0100_1000_1</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b100</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#affd3d4c8fd7cf2cbd78ecd99397f768b">`MICROPC_MOVEM_register_to_memory_predecrement</a><span class="vhdlchar"></span> } :
|
<a name="l02307"></a>02307 <span class="keyword">// MOVE USP to USP</span>
|
<a name="l02317"></a>02317 <span class="keyword">// MOVEM register to memory, control</span>
|
<a name="l02308"></a>02308 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">13'b0100_1110_0110_0</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a999737a0b112cb8f4691dfc97278bc7e">`MICROPC_MOVE_USP_to_USP</a><span class="vhdlchar"></span> } :
|
<a name="l02318"></a>02318 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">7</span>] == <span class="vhdllogic">9'b0100_1000_1</span> && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b101</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b110</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b111</span>) &&
|
<a name="l02309"></a>02309 <span class="keyword">// MOVE USP to An</span>
|
<a name="l02319"></a>02319 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span>)
|
<a name="l02310"></a>02310 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">13'b0100_1110_0110_1</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a506e512a7df02654649a4275b676b5f7">`MICROPC_MOVE_USP_to_An</a><span class="vhdlchar"></span> } :
|
<a name="l02320"></a>02320 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a775df2459596100b0e801ad20c24322b">`MICROPC_MOVEM_register_to_memory_control</a><span class="vhdlchar"></span> } :
|
<a name="l02311"></a>02311 <span class="keyword">// RESET</span>
|
<a name="l02321"></a>02321 <span class="keyword">// TST</span>
|
<a name="l02312"></a>02312 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0100_1110_0111_0000</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a7ac5bfe9a8556912db6217142a3bb772">`MICROPC_RESET</a><span class="vhdlchar"></span> } :
|
<a name="l02322"></a>02322 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">8'b0100_1010</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> &&
|
<a name="l02313"></a>02313 <span class="keyword">// NOP</span>
|
<a name="l02323"></a>02323 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> || (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span>))
|
<a name="l02314"></a>02314 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0100_1110_0111_0001</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a836e1069d2a67eabcd01a92fcc2672f0">`MICROPC_NOP</a><span class="vhdlchar"></span> } :
|
<a name="l02324"></a>02324 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a0c416458c758702471d503b0dbeab5d8">`MICROPC_TST</a><span class="vhdlchar"></span> } :
|
<a name="l02315"></a>02315 <span class="keyword">// STOP</span>
|
<a name="l02325"></a>02325 <span class="keyword">// TAS</span>
|
<a name="l02316"></a>02316 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0100_1110_0111_0010</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#aa23e89f5c79e7df7ff8ecf19a41ae572">`MICROPC_STOP</a><span class="vhdlchar"></span> } :
|
<a name="l02326"></a>02326 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">10'b0100_1010_11</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> &&
|
<a name="l02317"></a>02317 <span class="keyword">// RTE,RTR</span>
|
<a name="l02327"></a>02327 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> || (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span>))
|
<a name="l02318"></a>02318 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0100_1110_0111_0011</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0100_1110_0111_0111</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a76b52a43dac42903243a54b46c4bd839">`MICROPC_RTE_RTR</a><span class="vhdlchar"></span> } :
|
<a name="l02328"></a>02328 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a9d9308b3732ecf15f57a22600ac300b8">`MICROPC_TAS</a><span class="vhdlchar"></span> } :
|
<a name="l02319"></a>02319 <span class="keyword">// RTS</span>
|
<a name="l02329"></a>02329 <span class="keyword">// MOVEM memory to register</span>
|
<a name="l02320"></a>02320 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0100_1110_0111_0101</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a70b05c3577437ee3a51c6b63859242c5">`MICROPC_RTS</a><span class="vhdlchar"></span> } :
|
<a name="l02330"></a>02330 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">7</span>] == <span class="vhdllogic">9'b0100_1100_1</span> && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b011</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b101</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b110</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b111</span>) &&
|
<a name="l02321"></a>02321 <span class="keyword">// TRAPV</span>
|
<a name="l02331"></a>02331 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> ||
|
<a name="l02322"></a>02322 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0100_1110_0111_0110</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a5038c753fc668ac678fe18251202305e">`MICROPC_TRAPV</a><span class="vhdlchar"></span> } :
|
<a name="l02332"></a>02332 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_011</span>))
|
<a name="l02323"></a>02323 <span class="keyword">// JSR</span>
|
<a name="l02333"></a>02333 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#ac2e6ac139e91da76695b3f953c994a0d">`MICROPC_MOVEM_memory_to_register</a><span class="vhdlchar"></span> } :
|
<a name="l02324"></a>02324 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">10'b0100_1110_10</span> && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b101</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b110</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b111</span>) &&
|
<a name="l02334"></a>02334 <span class="keyword">// TRAP</span>
|
<a name="l02325"></a>02325 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> ||
|
<a name="l02335"></a>02335 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">12'b0100_1110_0100</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#aa106c5a18e8252dc2ced5ec2f77650d9">`MICROPC_TRAP</a><span class="vhdlchar"></span> } :
|
<a name="l02326"></a>02326 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_011</span>))
|
<a name="l02336"></a>02336 <span class="keyword">// LINK</span>
|
<a name="l02327"></a>02327 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a4a79b8f0394c470bd67ba6442fa12395">`MICROPC_JSR</a><span class="vhdlchar"></span> } :
|
<a name="l02337"></a>02337 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">13'b0100_1110_0101_0</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#af1b92ab55a321f316faf654b5d284caf">`MICROPC_LINK</a><span class="vhdlchar"></span> } :
|
<a name="l02328"></a>02328 <span class="keyword">// JMP</span>
|
<a name="l02338"></a>02338 <span class="keyword">// UNLK</span>
|
<a name="l02329"></a>02329 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">10'b0100_1110_11</span> && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b101</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b110</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b111</span>) &&
|
<a name="l02339"></a>02339 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">13'b0100_1110_0101_1</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a52c9810463f7dc671e021a7217259c04">`MICROPC_ULNK</a><span class="vhdlchar"></span> } :
|
<a name="l02330"></a>02330 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> ||
|
<a name="l02340"></a>02340 <span class="keyword">// MOVE USP to USP</span>
|
<a name="l02331"></a>02331 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_011</span>))
|
<a name="l02341"></a>02341 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">13'b0100_1110_0110_0</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a999737a0b112cb8f4691dfc97278bc7e">`MICROPC_MOVE_USP_to_USP</a><span class="vhdlchar"></span> } :
|
<a name="l02332"></a>02332 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a088577482bc02135d9aa7a58c1d0ed05">`MICROPC_JMP</a><span class="vhdlchar"></span> } :
|
<a name="l02342"></a>02342 <span class="keyword">// MOVE USP to An</span>
|
<a name="l02333"></a>02333 <span class="keyword">// ADDQ,SUBQ not An</span>
|
<a name="l02343"></a>02343 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">13'b0100_1110_0110_1</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a506e512a7df02654649a4275b676b5f7">`MICROPC_MOVE_USP_to_An</a><span class="vhdlchar"></span> } :
|
<a name="l02334"></a>02334 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0101</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> &&
|
<a name="l02344"></a>02344 <span class="keyword">// RESET</span>
|
<a name="l02335"></a>02335 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> || (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span>))
|
<a name="l02345"></a>02345 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0100_1110_0111_0000</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a7ac5bfe9a8556912db6217142a3bb772">`MICROPC_RESET</a><span class="vhdlchar"></span> } :
|
<a name="l02336"></a>02336 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#af6f7102b5f4972ae11cad584ed87de14">`MICROPC_ADDQ_SUBQ_not_An</a><span class="vhdlchar"></span> } :
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<a name="l02346"></a>02346 <span class="keyword">// NOP</span>
|
<a name="l02337"></a>02337 <span class="keyword">// ADDQ,SUBQ An</span>
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<a name="l02347"></a>02347 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0100_1110_0111_0001</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a836e1069d2a67eabcd01a92fcc2672f0">`MICROPC_NOP</a><span class="vhdlchar"></span> } :
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<a name="l02338"></a>02338 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0101</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b00</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b001</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#ae9cec5ce342a7d51efda687c24f35ab1">`MICROPC_ADDQ_SUBQ_An</a><span class="vhdlchar"></span> } :
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<a name="l02348"></a>02348 <span class="keyword">// STOP</span>
|
<a name="l02339"></a>02339 <span class="keyword">// Scc</span>
|
<a name="l02349"></a>02349 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0100_1110_0111_0010</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#aa23e89f5c79e7df7ff8ecf19a41ae572">`MICROPC_STOP</a><span class="vhdlchar"></span> } :
|
<a name="l02340"></a>02340 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0101</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> &&
|
<a name="l02350"></a>02350 <span class="keyword">// RTE,RTR</span>
|
<a name="l02341"></a>02341 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> || (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span>))
|
<a name="l02351"></a>02351 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0100_1110_0111_0011</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0100_1110_0111_0111</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a76b52a43dac42903243a54b46c4bd839">`MICROPC_RTE_RTR</a><span class="vhdlchar"></span> } :
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<a name="l02342"></a>02342 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#ac09a1b9ae5783634cc9228354105fc94">`MICROPC_Scc</a><span class="vhdlchar"></span> } :
|
<a name="l02352"></a>02352 <span class="keyword">// RTS</span>
|
<a name="l02343"></a>02343 <span class="keyword">// DBcc</span>
|
<a name="l02353"></a>02353 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0100_1110_0111_0101</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a70b05c3577437ee3a51c6b63859242c5">`MICROPC_RTS</a><span class="vhdlchar"></span> } :
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<a name="l02344"></a>02344 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0101</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b001</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a3d6a33ee86f4d37516a8afb60957b7ee">`MICROPC_DBcc</a><span class="vhdlchar"></span> } :
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<a name="l02354"></a>02354 <span class="keyword">// TRAPV</span>
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<a name="l02345"></a>02345 <span class="keyword">// BSR</span>
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<a name="l02355"></a>02355 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0100_1110_0111_0110</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a5038c753fc668ac678fe18251202305e">`MICROPC_TRAPV</a><span class="vhdlchar"></span> } :
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<a name="l02346"></a>02346 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0110</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0001</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#afefae415ee468c051f367b74183a122b">`MICROPC_BSR</a><span class="vhdlchar"></span> } :
|
<a name="l02356"></a>02356 <span class="keyword">// JSR</span>
|
<a name="l02347"></a>02347 <span class="keyword">// Bcc,BRA</span>
|
<a name="l02357"></a>02357 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">10'b0100_1110_10</span> && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b101</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b110</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b111</span>) &&
|
<a name="l02348"></a>02348 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0110</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] != <span class="vhdllogic">4'b0001</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#ae56342916e5e608a0fdd3a01a11688b0">`MICROPC_Bcc_BRA</a><span class="vhdlchar"></span> } :
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<a name="l02358"></a>02358 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> ||
|
<a name="l02349"></a>02349 <span class="keyword">// MOVEQ</span>
|
<a name="l02359"></a>02359 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_011</span>))
|
<a name="l02350"></a>02350 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0111</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b0</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a06f670a9b840bc7dda392686b0b53b41">`MICROPC_MOVEQ</a><span class="vhdlchar"></span> } :
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<a name="l02360"></a>02360 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a4a79b8f0394c470bd67ba6442fa12395">`MICROPC_JSR</a><span class="vhdlchar"></span> } :
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<a name="l02351"></a>02351 <span class="keyword">// CMP</span>
|
<a name="l02361"></a>02361 <span class="keyword">// JMP</span>
|
<a name="l02352"></a>02352 ( (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1011</span>) && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b010</span>) &&
|
<a name="l02362"></a>02362 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">10'b0100_1110_11</span> && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b101</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b110</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b111</span>) &&
|
<a name="l02353"></a>02353 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">3'b000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span>) &&
|
<a name="l02363"></a>02363 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> ||
|
<a name="l02354"></a>02354 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> ||
|
<a name="l02364"></a>02364 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_011</span>))
|
<a name="l02355"></a>02355 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_011</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_100</span>))
|
<a name="l02365"></a>02365 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a088577482bc02135d9aa7a58c1d0ed05">`MICROPC_JMP</a><span class="vhdlchar"></span> } :
|
<a name="l02356"></a>02356 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a2d30784cb012710f55727108a9b62cf1">`MICROPC_CMP</a><span class="vhdlchar"></span> } :
|
<a name="l02366"></a>02366 <span class="keyword">// ADDQ,SUBQ not An</span>
|
<a name="l02357"></a>02357 <span class="keyword">// CMPA</span>
|
<a name="l02367"></a>02367 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0101</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> &&
|
<a name="l02358"></a>02358 ( (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1011</span>) && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b011</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b111</span>) &&
|
<a name="l02368"></a>02368 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> || (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span>))
|
<a name="l02359"></a>02359 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> ||
|
<a name="l02369"></a>02369 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#af6f7102b5f4972ae11cad584ed87de14">`MICROPC_ADDQ_SUBQ_not_An</a><span class="vhdlchar"></span> } :
|
<a name="l02360"></a>02360 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_011</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_100</span>))
|
<a name="l02370"></a>02370 <span class="keyword">// ADDQ,SUBQ An</span>
|
<a name="l02361"></a>02361 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a853a2713ed61bd3e53e70297f62b654d">`MICROPC_CMPA</a><span class="vhdlchar"></span> } :
|
<a name="l02371"></a>02371 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0101</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b00</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b001</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#ae9cec5ce342a7d51efda687c24f35ab1">`MICROPC_ADDQ_SUBQ_An</a><span class="vhdlchar"></span> } :
|
<a name="l02362"></a>02362 <span class="keyword">// CMPM</span>
|
<a name="l02372"></a>02372 <span class="keyword">// Scc</span>
|
<a name="l02363"></a>02363 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1011</span> && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b100</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b101</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b110</span>) && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b001</span>) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a118f99a150352cf71a51d13156218674">`MICROPC_CMPM</a><span class="vhdlchar"></span> } :
|
<a name="l02373"></a>02373 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0101</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> &&
|
<a name="l02364"></a>02364 <span class="keyword">// EOR</span>
|
<a name="l02374"></a>02374 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> || (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span>))
|
<a name="l02365"></a>02365 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1011</span> && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b100</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b101</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b110</span>) && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> &&
|
<a name="l02375"></a>02375 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#ac09a1b9ae5783634cc9228354105fc94">`MICROPC_Scc</a><span class="vhdlchar"></span> } :
|
<a name="l02366"></a>02366 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> || (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span>))
|
<a name="l02376"></a>02376 <span class="keyword">// DBcc</span>
|
<a name="l02367"></a>02367 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#adaa788877b96a4c0cf1c9500aefc505a">`MICROPC_EOR</a><span class="vhdlchar"></span> } :
|
<a name="l02377"></a>02377 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0101</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b001</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a3d6a33ee86f4d37516a8afb60957b7ee">`MICROPC_DBcc</a><span class="vhdlchar"></span> } :
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<a name="l02368"></a>02368 <span class="keyword">// ADD to mem,SUB to mem,AND to mem,OR to mem</span>
|
<a name="l02378"></a>02378 <span class="keyword">// BSR</span>
|
<a name="l02369"></a>02369 ( (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1101</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1100</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1000</span>) &&
|
<a name="l02379"></a>02379 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0110</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0001</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#afefae415ee468c051f367b74183a122b">`MICROPC_BSR</a><span class="vhdlchar"></span> } :
|
<a name="l02370"></a>02370 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">5'b10001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">5'b10010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">5'b10011</span> ||
|
<a name="l02380"></a>02380 <span class="keyword">// Bcc,BRA</span>
|
<a name="l02371"></a>02371 <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">5'b10101</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">5'b10110</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">5'b10111</span> ||
|
<a name="l02381"></a>02381 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0110</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] != <span class="vhdllogic">4'b0001</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#ae56342916e5e608a0fdd3a01a11688b0">`MICROPC_Bcc_BRA</a><span class="vhdlchar"></span> } :
|
<a name="l02372"></a>02372 <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">5'b11001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">5'b11010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">5'b11011</span>) &&
|
<a name="l02382"></a>02382 <span class="keyword">// MOVEQ</span>
|
<a name="l02373"></a>02373 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> || (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span>))
|
<a name="l02383"></a>02383 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0111</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b0</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a06f670a9b840bc7dda392686b0b53b41">`MICROPC_MOVEQ</a><span class="vhdlchar"></span> } :
|
<a name="l02374"></a>02374 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#aa3942210285e132e0151143eca9103b4">`MICROPC_ADD_to_mem_SUB_to_mem_AND_to_mem_OR_to_mem</a><span class="vhdlchar"></span> } :
|
<a name="l02384"></a>02384 <span class="keyword">// CMP</span>
|
<a name="l02375"></a>02375 <span class="keyword">// ADD to Dn,SUB to Dn,AND to Dn,OR to Dn</span>
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<a name="l02385"></a>02385 ( (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1011</span>) && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b010</span>) &&
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<a name="l02376"></a>02376 ( (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1101</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1100</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1000</span>) &&
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<a name="l02386"></a>02386 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">3'b000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span>) &&
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<a name="l02377"></a>02377 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b010</span>) &&
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<a name="l02387"></a>02387 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> ||
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<a name="l02378"></a>02378 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">12</span>] != <span class="vhdllogic">1'b1</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">3'b000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span>) && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">12</span>] == <span class="vhdllogic">1'b1</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span>) &&
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<a name="l02388"></a>02388 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_011</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_100</span>))
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<a name="l02379"></a>02379 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> ||
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<a name="l02389"></a>02389 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a2d30784cb012710f55727108a9b62cf1">`MICROPC_CMP</a><span class="vhdlchar"></span> } :
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<a name="l02380"></a>02380 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_011</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_100</span>))
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<a name="l02390"></a>02390 <span class="keyword">// CMPA</span>
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<a name="l02381"></a>02381 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#acdb63549759af21684d2fd6e3dad8eb7">`MICROPC_ADD_to_Dn_SUB_to_Dn_AND_to_Dn_OR_to_Dn</a><span class="vhdlchar"></span> } :
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<a name="l02391"></a>02391 ( (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1011</span>) && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b011</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b111</span>) &&
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<a name="l02382"></a>02382 <span class="keyword">// ADDA,SUBA</span>
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<a name="l02392"></a>02392 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> ||
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<a name="l02383"></a>02383 ( (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1101</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1001</span>) && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b011</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b111</span>) &&
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<a name="l02393"></a>02393 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_011</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_100</span>))
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<a name="l02384"></a>02384 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> ||
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<a name="l02394"></a>02394 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a853a2713ed61bd3e53e70297f62b654d">`MICROPC_CMPA</a><span class="vhdlchar"></span> } :
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<a name="l02385"></a>02385 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_011</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_100</span>))
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<a name="l02395"></a>02395 <span class="keyword">// CMPM</span>
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<a name="l02386"></a>02386 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a02c5cdffb720a762c8790dbc86ab1a18">`MICROPC_ADDA_SUBA</a><span class="vhdlchar"></span> } :
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<a name="l02396"></a>02396 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1011</span> && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b100</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b101</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b110</span>) && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b001</span>) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a118f99a150352cf71a51d13156218674">`MICROPC_CMPM</a><span class="vhdlchar"></span> } :
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<a name="l02387"></a>02387 <span class="keyword">// ABCD,SBCD,ADDX,SUBX</span>
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<a name="l02397"></a>02397 <span class="keyword">// EOR</span>
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<a name="l02388"></a>02388 ( ((<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1100</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1000</span>) && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">5'b10000</span>) ||
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<a name="l02398"></a>02398 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1011</span> && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b100</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b101</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b110</span>) && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> &&
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<a name="l02389"></a>02389 ((<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1101</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1001</span>) && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">5'b10000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">5'b10100</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">5'b11000</span>) ) ) ?
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<a name="l02399"></a>02399 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> || (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span>))
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<a name="l02390"></a>02390 { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a52a25a790c5779d1d9c5d4b807f6e9e6">`MICROPC_ABCD_SBCD_ADDX_SUBX</a><span class="vhdlchar"></span> } :
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<a name="l02400"></a>02400 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#adaa788877b96a4c0cf1c9500aefc505a">`MICROPC_EOR</a><span class="vhdlchar"></span> } :
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<a name="l02391"></a>02391 <span class="keyword">// EXG</span>
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<a name="l02401"></a>02401 <span class="keyword">// ADD to mem,SUB to mem,AND to mem,OR to mem</span>
|
<a name="l02392"></a>02392 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1100</span> && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">6'b101000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">6'b101001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">6'b110001</span>) ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a5a514be119075b3c3ab64dfa849f3d9c">`MICROPC_EXG</a><span class="vhdlchar"></span> } :
|
<a name="l02402"></a>02402 ( (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1101</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1100</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1000</span>) &&
|
<a name="l02393"></a>02393 <span class="keyword">// MULS,MULU,DIVS,DIVU</span>
|
<a name="l02403"></a>02403 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">5'b10001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">5'b10010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">5'b10011</span> ||
|
<a name="l02394"></a>02394 ( (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1100</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1000</span>) && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> &&
|
<a name="l02404"></a>02404 <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">5'b10101</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">5'b10110</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">5'b10111</span> ||
|
<a name="l02395"></a>02395 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> ||
|
<a name="l02405"></a>02405 <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">5'b11001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">5'b11010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">5'b11011</span>) &&
|
<a name="l02396"></a>02396 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_011</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_100</span>))
|
<a name="l02406"></a>02406 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> || (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span>))
|
<a name="l02397"></a>02397 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#abff7613e058d71dedd233ff63a37a724">`MICROPC_MULS_MULU_DIVS_DIVU</a><span class="vhdlchar"></span> } :
|
<a name="l02407"></a>02407 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#aa3942210285e132e0151143eca9103b4">`MICROPC_ADD_to_mem_SUB_to_mem_AND_to_mem_OR_to_mem</a><span class="vhdlchar"></span> } :
|
<a name="l02398"></a>02398 <span class="keyword">// ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR all memory</span>
|
<a name="l02408"></a>02408 <span class="keyword">// ADD to Dn,SUB to Dn,AND to Dn,OR to Dn</span>
|
<a name="l02399"></a>02399 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1110</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>] == <span class="vhdllogic">1'b0</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b000</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> &&
|
<a name="l02409"></a>02409 ( (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1101</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1100</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1000</span>) &&
|
<a name="l02400"></a>02400 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> || (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span>))
|
<a name="l02410"></a>02410 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b010</span>) &&
|
<a name="l02401"></a>02401 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a28f22a27673dd123f2ae53ac00c27c47">`MICROPC_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR_all_memory</a><span class="vhdlchar"></span> } :
|
<a name="l02411"></a>02411 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">12</span>] != <span class="vhdllogic">1'b1</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">3'b000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span>) && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">12</span>] == <span class="vhdllogic">1'b1</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span>) &&
|
<a name="l02402"></a>02402 <span class="keyword">// ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR all immediate/register</span>
|
<a name="l02412"></a>02412 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> ||
|
<a name="l02403"></a>02403 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1110</span> && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b00</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b01</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b10</span>) ) ?
|
<a name="l02413"></a>02413 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_011</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_100</span>))
|
<a name="l02404"></a>02404 { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a8a505b33f1c42b903dcb264862dda090">`MICROPC_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR_all_immediate_register</a><span class="vhdlchar"></span> } :
|
<a name="l02414"></a>02414 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#acdb63549759af21684d2fd6e3dad8eb7">`MICROPC_ADD_to_Dn_SUB_to_Dn_AND_to_Dn_OR_to_Dn</a><span class="vhdlchar"></span> } :
|
<a name="l02405"></a>02405
|
<a name="l02415"></a>02415 <span class="keyword">// ADDA,SUBA</span>
|
<a name="l02406"></a>02406 <span class="keyword">// else</span>
|
<a name="l02416"></a>02416 ( (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1101</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1001</span>) && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b011</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b111</span>) &&
|
<a name="l02407"></a>02407
|
<a name="l02417"></a>02417 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> ||
|
<a name="l02408"></a>02408 { <a class="code" href="classdecoder.html#ae700aab6efd1c75556aeb4237f1d8c33">ILLEGAL_INSTRUCTION_TRAP</a>, <a class="code" href="classdecoder.html#aa6cefc0d2e58f3efccca7b784c2c9551">UNUSED_MICROPC</a> }
|
<a name="l02418"></a>02418 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_011</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_100</span>))
|
<a name="l02409"></a>02409 ;
|
<a name="l02419"></a>02419 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a02c5cdffb720a762c8790dbc86ab1a18">`MICROPC_ADDA_SUBA</a><span class="vhdlchar"></span> } :
|
<a name="l02410"></a>02410
|
<a name="l02420"></a>02420 <span class="keyword">// ABCD,SBCD,ADDX,SUBX</span>
|
<a name="l02411"></a>02411 <span class="keyword">// load ea</span>
|
<a name="l02421"></a>02421 ( ((<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1100</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1000</span>) && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">5'b10000</span>) ||
|
<a name="l02412"></a>02412 <span class="vhdlkeyword">assign</span> <a class="code" href="classdecoder.html#a37c251ae6bb47dd4f8a844cfc8f0757b">load_ea</a> =
|
<a name="l02422"></a>02422 ((<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1101</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1001</span>) && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">5'b10000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">5'b10100</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">5'b11000</span>) ) ) ?
|
<a name="l02413"></a>02413 (
|
<a name="l02423"></a>02423 { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a52a25a790c5779d1d9c5d4b807f6e9e6">`MICROPC_ABCD_SBCD_ADDX_SUBX</a><span class="vhdlchar"></span> } :
|
<a name="l02414"></a>02414 (<a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> && (<a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b000</span> || <a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b001</span> || (<a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b111</span> && <a class="code" href="classdecoder.html#ab7e5c6aab518d6f4ffb374d0d70774ed">ea_reg</a> == <span class="vhdllogic">3'b100</span>))) ||
|
<a name="l02424"></a>02424 <span class="keyword">// EXG</span>
|
<a name="l02415"></a>02415 (<a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a17a8a468ddfc3bdb178081a368f4dd6c">`EA_TYPE_DATAALTER</a><span class="vhdlchar"></span> && <a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b000</span>) ||
|
<a name="l02425"></a>02425 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1100</span> && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">6'b101000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">6'b101001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">6'b110001</span>) ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a5a514be119075b3c3ab64dfa849f3d9c">`MICROPC_EXG</a><span class="vhdlchar"></span> } :
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<a name="l02416"></a>02416 (<a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a8e7bc745d4def25f5a995a6955dbdb4b">`EA_TYPE_DN_AN</a><span class="vhdlchar"></span> && (<a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b000</span> || <a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b001</span>)) ||
|
<a name="l02426"></a>02426 <span class="keyword">// MULS,MULU,DIVS,DIVU</span>
|
<a name="l02417"></a>02417 (<a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span> && (<a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b000</span> || (<a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b111</span> && <a class="code" href="classdecoder.html#ab7e5c6aab518d6f4ffb374d0d70774ed">ea_reg</a> == <span class="vhdllogic">3'b100</span>)))
|
<a name="l02427"></a>02427 ( (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1100</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1000</span>) && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> &&
|
<a name="l02418"></a>02418 ) ? <span class="vhdllogic">9'd0</span> <span class="keyword">// no ea needed</span>
|
<a name="l02428"></a>02428 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> ||
|
<a name="l02419"></a>02419 :
|
<a name="l02429"></a>02429 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_011</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_100</span>))
|
<a name="l02420"></a>02420 (<a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b010</span> && (
|
<a name="l02430"></a>02430 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#abff7613e058d71dedd233ff63a37a724">`MICROPC_MULS_MULU_DIVS_DIVU</a><span class="vhdlchar"></span> } :
|
<a name="l02421"></a>02421 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a925f0004ba49b82dbdf7c4ae969ba6ed">`EA_TYPE_CONTROL_POSTINC</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a41499eaa1b7aa62f455a07e5435d754a">`EA_TYPE_CONTROLALTER_PREDEC</a><span class="vhdlchar"></span> ||
|
<a name="l02431"></a>02431 <span class="keyword">// ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR all memory</span>
|
<a name="l02422"></a>02422 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#ae2c794f81236993a23138cbf3f7eda44">`EA_TYPE_CONTROL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a17a8a468ddfc3bdb178081a368f4dd6c">`EA_TYPE_DATAALTER</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a653530f090b85ba7bcd93912b8834412">`EA_TYPE_MEMORYALTER</a><span class="vhdlchar"></span> ||
|
<a name="l02432"></a>02432 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1110</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>] == <span class="vhdllogic">1'b0</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b000</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> &&
|
<a name="l02423"></a>02423 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>
|
<a name="l02433"></a>02433 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> || (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span>))
|
<a name="l02424"></a>02424 )) ? <a class="code" href="ao68000_8v.html#a52c9fefea5280f08cf24bac6373252ac">`MICROPC_LOAD_EA_An</a><span class="vhdlchar"></span> <span class="keyword">// (An)</span>
|
<a name="l02434"></a>02434 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a28f22a27673dd123f2ae53ac00c27c47">`MICROPC_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR_all_memory</a><span class="vhdlchar"></span> } :
|
<a name="l02425"></a>02425 :
|
<a name="l02435"></a>02435 <span class="keyword">// ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR all immediate/register</span>
|
<a name="l02426"></a>02426 (<a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b011</span> && (
|
<a name="l02436"></a>02436 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1110</span> && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b00</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b01</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b10</span>) ) ?
|
<a name="l02427"></a>02427 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a925f0004ba49b82dbdf7c4ae969ba6ed">`EA_TYPE_CONTROL_POSTINC</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a653530f090b85ba7bcd93912b8834412">`EA_TYPE_MEMORYALTER</a><span class="vhdlchar"></span> ||
|
<a name="l02437"></a>02437 { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a8a505b33f1c42b903dcb264862dda090">`MICROPC_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR_all_immediate_register</a><span class="vhdlchar"></span> } :
|
<a name="l02428"></a>02428 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a17a8a468ddfc3bdb178081a368f4dd6c">`EA_TYPE_DATAALTER</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>
|
<a name="l02438"></a>02438
|
<a name="l02429"></a>02429 )) ? <a class="code" href="ao68000_8v.html#aafdd46a7740d48b02e781d3136f7ce1d">`MICROPC_LOAD_EA_An_plus</a><span class="vhdlchar"></span> <span class="keyword">// (An)+</span>
|
<a name="l02439"></a>02439 <span class="keyword">// else</span>
|
<a name="l02430"></a>02430 :
|
<a name="l02440"></a>02440
|
<a name="l02431"></a>02431 (<a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b100</span> && (
|
<a name="l02441"></a>02441 { <a class="code" href="classdecoder.html#ae700aab6efd1c75556aeb4237f1d8c33">ILLEGAL_INSTRUCTION_TRAP</a>, <a class="code" href="classdecoder.html#aa6cefc0d2e58f3efccca7b784c2c9551">UNUSED_MICROPC</a> }
|
<a name="l02432"></a>02432 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a41499eaa1b7aa62f455a07e5435d754a">`EA_TYPE_CONTROLALTER_PREDEC</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a17a8a468ddfc3bdb178081a368f4dd6c">`EA_TYPE_DATAALTER</a><span class="vhdlchar"></span> ||
|
<a name="l02442"></a>02442 ;
|
<a name="l02433"></a>02433 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a653530f090b85ba7bcd93912b8834412">`EA_TYPE_MEMORYALTER</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>
|
<a name="l02443"></a>02443
|
<a name="l02434"></a>02434 )) ? <a class="code" href="ao68000_8v.html#a9b094e5044be3be8167a5b80bd274433">`MICROPC_LOAD_EA_minus_An</a><span class="vhdlchar"></span> <span class="keyword">// -(An)</span>
|
<a name="l02444"></a>02444 <span class="keyword">// load ea</span>
|
<a name="l02435"></a>02435 :
|
<a name="l02445"></a>02445 <span class="vhdlkeyword">assign</span> <a class="code" href="classdecoder.html#a37c251ae6bb47dd4f8a844cfc8f0757b">load_ea</a> =
|
<a name="l02436"></a>02436 (<a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b101</span> && (
|
<a name="l02446"></a>02446 (
|
<a name="l02437"></a>02437 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a925f0004ba49b82dbdf7c4ae969ba6ed">`EA_TYPE_CONTROL_POSTINC</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a41499eaa1b7aa62f455a07e5435d754a">`EA_TYPE_CONTROLALTER_PREDEC</a><span class="vhdlchar"></span> ||
|
<a name="l02447"></a>02447 (<a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> && (<a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b000</span> || <a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b001</span> || (<a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b111</span> && <a class="code" href="classdecoder.html#ab7e5c6aab518d6f4ffb374d0d70774ed">ea_reg</a> == <span class="vhdllogic">3'b100</span>))) ||
|
<a name="l02438"></a>02438 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#ae2c794f81236993a23138cbf3f7eda44">`EA_TYPE_CONTROL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a17a8a468ddfc3bdb178081a368f4dd6c">`EA_TYPE_DATAALTER</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a653530f090b85ba7bcd93912b8834412">`EA_TYPE_MEMORYALTER</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>
|
<a name="l02448"></a>02448 (<a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a17a8a468ddfc3bdb178081a368f4dd6c">`EA_TYPE_DATAALTER</a><span class="vhdlchar"></span> && <a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b000</span>) ||
|
<a name="l02439"></a>02439 )) ? <a class="code" href="ao68000_8v.html#a6e06b607b9a1a157e3753943d2b015e1">`MICROPC_LOAD_EA_d16_An</a><span class="vhdlchar"></span> <span class="keyword">// (d16, An)</span>
|
<a name="l02449"></a>02449 (<a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a8e7bc745d4def25f5a995a6955dbdb4b">`EA_TYPE_DN_AN</a><span class="vhdlchar"></span> && (<a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b000</span> || <a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b001</span>)) ||
|
<a name="l02440"></a>02440 :
|
<a name="l02450"></a>02450 (<a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span> && (<a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b000</span> || (<a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b111</span> && <a class="code" href="classdecoder.html#ab7e5c6aab518d6f4ffb374d0d70774ed">ea_reg</a> == <span class="vhdllogic">3'b100</span>)))
|
<a name="l02441"></a>02441 (<a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b110</span> && (
|
<a name="l02451"></a>02451 ) ? <span class="vhdllogic">9'd0</span> <span class="keyword">// no ea needed</span>
|
<a name="l02442"></a>02442 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a925f0004ba49b82dbdf7c4ae969ba6ed">`EA_TYPE_CONTROL_POSTINC</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a41499eaa1b7aa62f455a07e5435d754a">`EA_TYPE_CONTROLALTER_PREDEC</a><span class="vhdlchar"></span> ||
|
<a name="l02452"></a>02452 :
|
<a name="l02443"></a>02443 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#ae2c794f81236993a23138cbf3f7eda44">`EA_TYPE_CONTROL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a17a8a468ddfc3bdb178081a368f4dd6c">`EA_TYPE_DATAALTER</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a653530f090b85ba7bcd93912b8834412">`EA_TYPE_MEMORYALTER</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>
|
<a name="l02453"></a>02453 (<a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b010</span> && (
|
<a name="l02444"></a>02444 )) ? <a class="code" href="ao68000_8v.html#aa80bb2f21742a46f59c3b8401c9209a3">`MICROPC_LOAD_EA_d8_An_Xn</a><span class="vhdlchar"></span> <span class="keyword">// (d8, An, Xn)</span>
|
<a name="l02454"></a>02454 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a925f0004ba49b82dbdf7c4ae969ba6ed">`EA_TYPE_CONTROL_POSTINC</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a41499eaa1b7aa62f455a07e5435d754a">`EA_TYPE_CONTROLALTER_PREDEC</a><span class="vhdlchar"></span> ||
|
<a name="l02445"></a>02445 :
|
<a name="l02455"></a>02455 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#ae2c794f81236993a23138cbf3f7eda44">`EA_TYPE_CONTROL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a17a8a468ddfc3bdb178081a368f4dd6c">`EA_TYPE_DATAALTER</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a653530f090b85ba7bcd93912b8834412">`EA_TYPE_MEMORYALTER</a><span class="vhdlchar"></span> ||
|
<a name="l02446"></a>02446 (<a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b111</span> && <a class="code" href="classdecoder.html#ab7e5c6aab518d6f4ffb374d0d70774ed">ea_reg</a> == <span class="vhdllogic">3'b000</span> && (
|
<a name="l02456"></a>02456 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>
|
<a name="l02447"></a>02447 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a925f0004ba49b82dbdf7c4ae969ba6ed">`EA_TYPE_CONTROL_POSTINC</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a41499eaa1b7aa62f455a07e5435d754a">`EA_TYPE_CONTROLALTER_PREDEC</a><span class="vhdlchar"></span> ||
|
<a name="l02457"></a>02457 )) ? <a class="code" href="ao68000_8v.html#a52c9fefea5280f08cf24bac6373252ac">`MICROPC_LOAD_EA_An</a><span class="vhdlchar"></span> <span class="keyword">// (An)</span>
|
<a name="l02448"></a>02448 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#ae2c794f81236993a23138cbf3f7eda44">`EA_TYPE_CONTROL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a17a8a468ddfc3bdb178081a368f4dd6c">`EA_TYPE_DATAALTER</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a653530f090b85ba7bcd93912b8834412">`EA_TYPE_MEMORYALTER</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>
|
<a name="l02458"></a>02458 :
|
<a name="l02449"></a>02449 )) ? <a class="code" href="ao68000_8v.html#ade20a2ce9d926ed45a0c6e2d4c2bffad">`MICROPC_LOAD_EA_xxx_W</a><span class="vhdlchar"></span> <span class="keyword">// (xxx).W</span>
|
<a name="l02459"></a>02459 (<a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b011</span> && (
|
<a name="l02450"></a>02450 :
|
<a name="l02460"></a>02460 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a925f0004ba49b82dbdf7c4ae969ba6ed">`EA_TYPE_CONTROL_POSTINC</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a653530f090b85ba7bcd93912b8834412">`EA_TYPE_MEMORYALTER</a><span class="vhdlchar"></span> ||
|
<a name="l02451"></a>02451 (<a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b111</span> && <a class="code" href="classdecoder.html#ab7e5c6aab518d6f4ffb374d0d70774ed">ea_reg</a> == <span class="vhdllogic">3'b001</span> && (
|
<a name="l02461"></a>02461 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a17a8a468ddfc3bdb178081a368f4dd6c">`EA_TYPE_DATAALTER</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>
|
<a name="l02452"></a>02452 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a925f0004ba49b82dbdf7c4ae969ba6ed">`EA_TYPE_CONTROL_POSTINC</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a41499eaa1b7aa62f455a07e5435d754a">`EA_TYPE_CONTROLALTER_PREDEC</a><span class="vhdlchar"></span> ||
|
<a name="l02462"></a>02462 )) ? <a class="code" href="ao68000_8v.html#aafdd46a7740d48b02e781d3136f7ce1d">`MICROPC_LOAD_EA_An_plus</a><span class="vhdlchar"></span> <span class="keyword">// (An)+</span>
|
<a name="l02453"></a>02453 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#ae2c794f81236993a23138cbf3f7eda44">`EA_TYPE_CONTROL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a17a8a468ddfc3bdb178081a368f4dd6c">`EA_TYPE_DATAALTER</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a653530f090b85ba7bcd93912b8834412">`EA_TYPE_MEMORYALTER</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>
|
|
<a name="l02454"></a>02454 )) ? <a class="code" href="ao68000_8v.html#ac3601da82892ec91bbc958628eb6ed03">`MICROPC_LOAD_EA_xxx_L</a><span class="vhdlchar"></span> <span class="keyword">// (xxx).L</span>
|
|
<a name="l02455"></a>02455 :
|
|
<a name="l02456"></a>02456 (<a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b111</span> && <a class="code" href="classdecoder.html#ab7e5c6aab518d6f4ffb374d0d70774ed">ea_reg</a> == <span class="vhdllogic">3'b010</span> && (
|
|
<a name="l02457"></a>02457 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a925f0004ba49b82dbdf7c4ae969ba6ed">`EA_TYPE_CONTROL_POSTINC</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#ae2c794f81236993a23138cbf3f7eda44">`EA_TYPE_CONTROL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>
|
|
<a name="l02458"></a>02458 )) ? <a class="code" href="ao68000_8v.html#a7cb86509757fa3419fbc8980724bd315">`MICROPC_LOAD_EA_d16_PC</a><span class="vhdlchar"></span> <span class="keyword">// (d16, PC)</span>
|
|
<a name="l02459"></a>02459 :
|
|
<a name="l02460"></a>02460 (<a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b111</span> && <a class="code" href="classdecoder.html#ab7e5c6aab518d6f4ffb374d0d70774ed">ea_reg</a> == <span class="vhdllogic">3'b011</span> && (
|
|
<a name="l02461"></a>02461 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a925f0004ba49b82dbdf7c4ae969ba6ed">`EA_TYPE_CONTROL_POSTINC</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#ae2c794f81236993a23138cbf3f7eda44">`EA_TYPE_CONTROL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>
|
|
<a name="l02462"></a>02462 )) ? <a class="code" href="ao68000_8v.html#a785fdbd62d5c0da122ada9db07753b74">`MICROPC_LOAD_EA_d8_PC_Xn</a><span class="vhdlchar"></span> <span class="keyword">// (d8, PC, Xn)</span>
|
<a name="l02463"></a>02463 :
|
<a name="l02463"></a>02463 :
|
<a name="l02464"></a>02464 (<a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b100</span> && (
|
<a name="l02464"></a>02464 <a class="code" href="ao68000_8v.html#a92f21025346f2b9baad5ee3ea27c8833">`MICROPC_LOAD_EA_illegal_command</a><span class="vhdlchar"></span> <span class="keyword">// illegal command</span>
|
<a name="l02465"></a>02465 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a41499eaa1b7aa62f455a07e5435d754a">`EA_TYPE_CONTROLALTER_PREDEC</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a17a8a468ddfc3bdb178081a368f4dd6c">`EA_TYPE_DATAALTER</a><span class="vhdlchar"></span> ||
|
<a name="l02465"></a>02465 ;
|
<a name="l02466"></a>02466 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a653530f090b85ba7bcd93912b8834412">`EA_TYPE_MEMORYALTER</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>
|
<a name="l02466"></a>02466
|
<a name="l02467"></a>02467 )) ? <a class="code" href="ao68000_8v.html#a9b094e5044be3be8167a5b80bd274433">`MICROPC_LOAD_EA_minus_An</a><span class="vhdlchar"></span> <span class="keyword">// -(An)</span>
|
<a name="l02467"></a>02467 <span class="keyword">// perform ea read</span>
|
<a name="l02468"></a>02468 :
|
<a name="l02468"></a>02468 <span class="vhdlkeyword">assign</span> <a class="code" href="classdecoder.html#a0081e82b20c0976ecb13d48dcc0f7554">perform_ea_read</a> =
|
<a name="l02469"></a>02469 (<a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b101</span> && (
|
<a name="l02469"></a>02469 ( <a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b000</span> && (<a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a17a8a468ddfc3bdb178081a368f4dd6c">`EA_TYPE_DATAALTER</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a8e7bc745d4def25f5a995a6955dbdb4b">`EA_TYPE_DN_AN</a><span class="vhdlchar"></span> ||
|
<a name="l02470"></a>02470 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a925f0004ba49b82dbdf7c4ae969ba6ed">`EA_TYPE_CONTROL_POSTINC</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a41499eaa1b7aa62f455a07e5435d754a">`EA_TYPE_CONTROLALTER_PREDEC</a><span class="vhdlchar"></span> ||
|
<a name="l02470"></a>02470 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>) ) ?
|
<a name="l02471"></a>02471 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#ae2c794f81236993a23138cbf3f7eda44">`EA_TYPE_CONTROL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a17a8a468ddfc3bdb178081a368f4dd6c">`EA_TYPE_DATAALTER</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a653530f090b85ba7bcd93912b8834412">`EA_TYPE_MEMORYALTER</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>
|
<a name="l02471"></a>02471 <a class="code" href="ao68000_8v.html#ae21eb6fc6455af78326135e407ee17eb">`MICROPC_PERFORM_EA_READ_Dn</a><span class="vhdlchar"></span> :
|
<a name="l02472"></a>02472 )) ? <a class="code" href="ao68000_8v.html#a6e06b607b9a1a157e3753943d2b015e1">`MICROPC_LOAD_EA_d16_An</a><span class="vhdlchar"></span> <span class="keyword">// (d16, An)</span>
|
<a name="l02472"></a>02472 ( <a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b001</span> && (<a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a8e7bc745d4def25f5a995a6955dbdb4b">`EA_TYPE_DN_AN</a><span class="vhdlchar"></span>) ) ? <a class="code" href="ao68000_8v.html#a8d6dcbc97994c642a8da0be0fecc257a">`MICROPC_PERFORM_EA_READ_An</a><span class="vhdlchar"></span> :
|
<a name="l02473"></a>02473 :
|
<a name="l02473"></a>02473 ( <a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b111</span> && <a class="code" href="classdecoder.html#ab7e5c6aab518d6f4ffb374d0d70774ed">ea_reg</a> == <span class="vhdllogic">3'b100</span> && (<a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>) ) ?
|
<a name="l02474"></a>02474 (<a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b110</span> && (
|
<a name="l02474"></a>02474 <a class="code" href="ao68000_8v.html#ac2394d0cf1bffca610b4c8fb77881207">`MICROPC_PERFORM_EA_READ_imm</a><span class="vhdlchar"></span> :
|
<a name="l02475"></a>02475 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a925f0004ba49b82dbdf7c4ae969ba6ed">`EA_TYPE_CONTROL_POSTINC</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a41499eaa1b7aa62f455a07e5435d754a">`EA_TYPE_CONTROLALTER_PREDEC</a><span class="vhdlchar"></span> ||
|
<a name="l02475"></a>02475 <a class="code" href="ao68000_8v.html#a2c70544d287306914c57f360847a1abd">`MICROPC_PERFORM_EA_READ_memory</a><span class="vhdlchar"></span>
|
<a name="l02476"></a>02476 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#ae2c794f81236993a23138cbf3f7eda44">`EA_TYPE_CONTROL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a17a8a468ddfc3bdb178081a368f4dd6c">`EA_TYPE_DATAALTER</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a653530f090b85ba7bcd93912b8834412">`EA_TYPE_MEMORYALTER</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>
|
<a name="l02476"></a>02476 ;
|
<a name="l02477"></a>02477 )) ? <a class="code" href="ao68000_8v.html#aa80bb2f21742a46f59c3b8401c9209a3">`MICROPC_LOAD_EA_d8_An_Xn</a><span class="vhdlchar"></span> <span class="keyword">// (d8, An, Xn)</span>
|
<a name="l02477"></a>02477
|
<a name="l02478"></a>02478 :
|
<a name="l02478"></a>02478 <span class="keyword">// perform ea write</span>
|
<a name="l02479"></a>02479 (<a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b111</span> && <a class="code" href="classdecoder.html#ab7e5c6aab518d6f4ffb374d0d70774ed">ea_reg</a> == <span class="vhdllogic">3'b000</span> && (
|
<a name="l02479"></a>02479 <span class="vhdlkeyword">assign</span> <a class="code" href="classdecoder.html#a0a10ac646012973ca8a578403894590e">perform_ea_write</a> =
|
<a name="l02480"></a>02480 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a925f0004ba49b82dbdf7c4ae969ba6ed">`EA_TYPE_CONTROL_POSTINC</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a41499eaa1b7aa62f455a07e5435d754a">`EA_TYPE_CONTROLALTER_PREDEC</a><span class="vhdlchar"></span> ||
|
<a name="l02480"></a>02480 ( <a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b000</span> && (<a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a17a8a468ddfc3bdb178081a368f4dd6c">`EA_TYPE_DATAALTER</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a8e7bc745d4def25f5a995a6955dbdb4b">`EA_TYPE_DN_AN</a><span class="vhdlchar"></span> ||
|
<a name="l02481"></a>02481 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#ae2c794f81236993a23138cbf3f7eda44">`EA_TYPE_CONTROL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a17a8a468ddfc3bdb178081a368f4dd6c">`EA_TYPE_DATAALTER</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a653530f090b85ba7bcd93912b8834412">`EA_TYPE_MEMORYALTER</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>
|
<a name="l02481"></a>02481 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>) ) ?
|
<a name="l02482"></a>02482 )) ? <a class="code" href="ao68000_8v.html#ade20a2ce9d926ed45a0c6e2d4c2bffad">`MICROPC_LOAD_EA_xxx_W</a><span class="vhdlchar"></span> <span class="keyword">// (xxx).W</span>
|
<a name="l02482"></a>02482 <a class="code" href="ao68000_8v.html#acb05778c30ee2acc522c18f823a678ff">`MICROPC_PERFORM_EA_WRITE_Dn</a><span class="vhdlchar"></span> :
|
<a name="l02483"></a>02483 :
|
<a name="l02483"></a>02483 ( <a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b001</span> && (<a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a8e7bc745d4def25f5a995a6955dbdb4b">`EA_TYPE_DN_AN</a><span class="vhdlchar"></span>) ) ? <a class="code" href="ao68000_8v.html#a20c5aa2df0d23f8bbdaccfca2bfed9f8">`MICROPC_PERFORM_EA_WRITE_An</a><span class="vhdlchar"></span> :
|
<a name="l02484"></a>02484 (<a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b111</span> && <a class="code" href="classdecoder.html#ab7e5c6aab518d6f4ffb374d0d70774ed">ea_reg</a> == <span class="vhdllogic">3'b001</span> && (
|
<a name="l02484"></a>02484 <a class="code" href="ao68000_8v.html#ab8383cdb4a1df6d5f3296bb4244c7bab">`MICROPC_PERFORM_EA_WRITE_memory</a><span class="vhdlchar"></span>
|
<a name="l02485"></a>02485 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a925f0004ba49b82dbdf7c4ae969ba6ed">`EA_TYPE_CONTROL_POSTINC</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a41499eaa1b7aa62f455a07e5435d754a">`EA_TYPE_CONTROLALTER_PREDEC</a><span class="vhdlchar"></span> ||
|
<a name="l02485"></a>02485 ;
|
<a name="l02486"></a>02486 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#ae2c794f81236993a23138cbf3f7eda44">`EA_TYPE_CONTROL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a17a8a468ddfc3bdb178081a368f4dd6c">`EA_TYPE_DATAALTER</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a653530f090b85ba7bcd93912b8834412">`EA_TYPE_MEMORYALTER</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>
|
<a name="l02486"></a>02486
|
<a name="l02487"></a>02487 )) ? <a class="code" href="ao68000_8v.html#ac3601da82892ec91bbc958628eb6ed03">`MICROPC_LOAD_EA_xxx_L</a><span class="vhdlchar"></span> <span class="keyword">// (xxx).L</span>
|
<a name="l02487"></a>02487 <span class="keyword">// save ea</span>
|
<a name="l02488"></a>02488 :
|
<a name="l02488"></a>02488 <span class="vhdlkeyword">assign</span> <a class="code" href="classdecoder.html#a8f1fa508fbad7ecd8f15a47ac97be0dc">save_ea</a> =
|
<a name="l02489"></a>02489 (<a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b111</span> && <a class="code" href="classdecoder.html#ab7e5c6aab518d6f4ffb374d0d70774ed">ea_reg</a> == <span class="vhdllogic">3'b010</span> && (
|
<a name="l02489"></a>02489 (<a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b011</span> && (
|
<a name="l02490"></a>02490 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a925f0004ba49b82dbdf7c4ae969ba6ed">`EA_TYPE_CONTROL_POSTINC</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#ae2c794f81236993a23138cbf3f7eda44">`EA_TYPE_CONTROL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>
|
<a name="l02490"></a>02490 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a925f0004ba49b82dbdf7c4ae969ba6ed">`EA_TYPE_CONTROL_POSTINC</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a653530f090b85ba7bcd93912b8834412">`EA_TYPE_MEMORYALTER</a><span class="vhdlchar"></span> ||
|
<a name="l02491"></a>02491 )) ? <a class="code" href="ao68000_8v.html#a7cb86509757fa3419fbc8980724bd315">`MICROPC_LOAD_EA_d16_PC</a><span class="vhdlchar"></span> <span class="keyword">// (d16, PC)</span>
|
<a name="l02491"></a>02491 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a17a8a468ddfc3bdb178081a368f4dd6c">`EA_TYPE_DATAALTER</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>
|
<a name="l02492"></a>02492 :
|
<a name="l02492"></a>02492 )) ? <a class="code" href="ao68000_8v.html#a02dc58bcc0412d6c93647a1304f20443">`MICROPC_SAVE_EA_An_plus</a><span class="vhdlchar"></span> <span class="keyword">// (An)+</span>
|
<a name="l02493"></a>02493 (<a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b111</span> && <a class="code" href="classdecoder.html#ab7e5c6aab518d6f4ffb374d0d70774ed">ea_reg</a> == <span class="vhdllogic">3'b011</span> && (
|
<a name="l02493"></a>02493 :
|
<a name="l02494"></a>02494 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a925f0004ba49b82dbdf7c4ae969ba6ed">`EA_TYPE_CONTROL_POSTINC</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#ae2c794f81236993a23138cbf3f7eda44">`EA_TYPE_CONTROL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>
|
<a name="l02494"></a>02494 (<a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b100</span> && (
|
<a name="l02495"></a>02495 )) ? <a class="code" href="ao68000_8v.html#a785fdbd62d5c0da122ada9db07753b74">`MICROPC_LOAD_EA_d8_PC_Xn</a><span class="vhdlchar"></span> <span class="keyword">// (d8, PC, Xn)</span>
|
<a name="l02495"></a>02495 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a41499eaa1b7aa62f455a07e5435d754a">`EA_TYPE_CONTROLALTER_PREDEC</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a17a8a468ddfc3bdb178081a368f4dd6c">`EA_TYPE_DATAALTER</a><span class="vhdlchar"></span> ||
|
<a name="l02496"></a>02496 :
|
<a name="l02496"></a>02496 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a653530f090b85ba7bcd93912b8834412">`EA_TYPE_MEMORYALTER</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>
|
<a name="l02497"></a>02497 <a class="code" href="ao68000_8v.html#a92f21025346f2b9baad5ee3ea27c8833">`MICROPC_LOAD_EA_illegal_command</a><span class="vhdlchar"></span> <span class="keyword">// illegal command</span>
|
<a name="l02497"></a>02497 )) ? <a class="code" href="ao68000_8v.html#ae4c00f630c944a41db777f7b51ee052d">`MICROPC_SAVE_EA_minus_An</a><span class="vhdlchar"></span> <span class="keyword">// -(An)</span>
|
<a name="l02498"></a>02498 ;
|
<a name="l02498"></a>02498 :
|
<a name="l02499"></a>02499
|
<a name="l02499"></a>02499 <span class="vhdllogic">9'd0</span> <span class="keyword">// no ea needed</span>
|
<a name="l02500"></a>02500 <span class="keyword">// perform ea read</span>
|
<a name="l02500"></a>02500 ;
|
<a name="l02501"></a>02501 <span class="vhdlkeyword">assign</span> <a class="code" href="classdecoder.html#a0081e82b20c0976ecb13d48dcc0f7554">perform_ea_read</a> =
|
<a name="l02501"></a>02501
|
<a name="l02502"></a>02502 ( <a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b000</span> && (<a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a17a8a468ddfc3bdb178081a368f4dd6c">`EA_TYPE_DATAALTER</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a8e7bc745d4def25f5a995a6955dbdb4b">`EA_TYPE_DN_AN</a><span class="vhdlchar"></span> ||
|
<a name="l02502"></a>02502 <span class="vhdlkeyword">endmodule</span>
|
<a name="l02503"></a>02503 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>) ) ?
|
<a name="l02503"></a>02503
|
<a name="l02504"></a>02504 <a class="code" href="ao68000_8v.html#ae21eb6fc6455af78326135e407ee17eb">`MICROPC_PERFORM_EA_READ_Dn</a><span class="vhdlchar"></span> :
|
<a name="l02504"></a>02504 <span class="keyword">/***********************************************************************************************************************</span>
|
<a name="l02505"></a>02505 ( <a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b001</span> && (<a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a8e7bc745d4def25f5a995a6955dbdb4b">`EA_TYPE_DN_AN</a><span class="vhdlchar"></span>) ) ? <a class="code" href="ao68000_8v.html#a8d6dcbc97994c642a8da0be0fecc257a">`MICROPC_PERFORM_EA_READ_An</a><span class="vhdlchar"></span> :
|
<a name="l02505"></a>02505 <span class="keyword"> Condition</span>
|
<a name="l02506"></a>02506 ( <a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b111</span> && <a class="code" href="classdecoder.html#ab7e5c6aab518d6f4ffb374d0d70774ed">ea_reg</a> == <span class="vhdllogic">3'b100</span> && (<a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>) ) ?
|
<a name="l02506"></a>02506 <span class="keyword"> ***********************************************************************************************************************/</span>
|
<a name="l02507"></a>02507 <a class="code" href="ao68000_8v.html#ac2394d0cf1bffca610b4c8fb77881207">`MICROPC_PERFORM_EA_READ_imm</a><span class="vhdlchar"></span> :
|
<a name="l02507"></a>02507
|
<a name="l02508"></a>02508 <a class="code" href="ao68000_8v.html#a2c70544d287306914c57f360847a1abd">`MICROPC_PERFORM_EA_READ_memory</a><span class="vhdlchar"></span>
|
<a name="l02508"></a>02508
|
<a name="l02509"></a>02509 ;
|
<a name="l02514"></a><a class="code" href="classcondition.html">02514</a> <span class="vhdlkeyword">module</span> <a class="code" href="classcondition.html">condition</a>(
|
<a name="l02510"></a>02510
|
<a name="l02515"></a><a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">02515</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] <a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a>,
|
<a name="l02511"></a>02511 <span class="keyword">// perform ea write</span>
|
<a name="l02516"></a><a class="code" href="classcondition.html#abac84a257e657e334871ef190cce9616">02516</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <a class="code" href="classcondition.html#abac84a257e657e334871ef190cce9616">ccr</a>,
|
<a name="l02512"></a>02512 <span class="vhdlkeyword">assign</span> <a class="code" href="classdecoder.html#a0a10ac646012973ca8a578403894590e">perform_ea_write</a> =
|
<a name="l02517"></a><a class="code" href="classcondition.html#acb19756f5d198b371846bce84e08d569">02517</a> <span class="vhdlkeyword">output</span> <a class="code" href="classcondition.html#acb19756f5d198b371846bce84e08d569">condition</a>
|
<a name="l02513"></a>02513 ( <a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b000</span> && (<a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a17a8a468ddfc3bdb178081a368f4dd6c">`EA_TYPE_DATAALTER</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a8e7bc745d4def25f5a995a6955dbdb4b">`EA_TYPE_DN_AN</a><span class="vhdlchar"></span> ||
|
<a name="l02518"></a>02518 );
|
<a name="l02514"></a>02514 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>) ) ?
|
|
<a name="l02515"></a>02515 <a class="code" href="ao68000_8v.html#acb05778c30ee2acc522c18f823a678ff">`MICROPC_PERFORM_EA_WRITE_Dn</a><span class="vhdlchar"></span> :
|
|
<a name="l02516"></a>02516 ( <a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b001</span> && (<a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a8e7bc745d4def25f5a995a6955dbdb4b">`EA_TYPE_DN_AN</a><span class="vhdlchar"></span>) ) ? <a class="code" href="ao68000_8v.html#a20c5aa2df0d23f8bbdaccfca2bfed9f8">`MICROPC_PERFORM_EA_WRITE_An</a><span class="vhdlchar"></span> :
|
|
<a name="l02517"></a>02517 <a class="code" href="ao68000_8v.html#ab8383cdb4a1df6d5f3296bb4244c7bab">`MICROPC_PERFORM_EA_WRITE_memory</a><span class="vhdlchar"></span>
|
|
<a name="l02518"></a>02518 ;
|
|
<a name="l02519"></a>02519
|
<a name="l02519"></a>02519
|
<a name="l02520"></a>02520 <span class="keyword">// save ea</span>
|
<a name="l02520"></a><a class="code" href="classcondition.html#a741ec53b25de93d917a650089cd95870">02520</a> <span class="vhdlkeyword">wire</span> <a class="code" href="classcondition.html#a3f5fcf283ca56b2cfe4269cff52ee925">C</a>,<a class="code" href="classcondition.html#a4478c90a4669d8bd947561aaddfe3bfb">V</a>,<a class="code" href="classcondition.html#a88c2e82409be05b0e4072b5fd9fc6048">Z</a>,<a class="code" href="classcondition.html#a741ec53b25de93d917a650089cd95870">N</a>;
|
<a name="l02521"></a>02521 <span class="vhdlkeyword">assign</span> <a class="code" href="classdecoder.html#a8f1fa508fbad7ecd8f15a47ac97be0dc">save_ea</a> =
|
<a name="l02521"></a>02521 <span class="vhdlkeyword">assign</span> <a class="code" href="classcondition.html#a3f5fcf283ca56b2cfe4269cff52ee925">C</a> = <a class="code" href="classcondition.html#abac84a257e657e334871ef190cce9616">ccr</a>[<span class="vhdllogic">0</span>];
|
<a name="l02522"></a>02522 (<a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b011</span> && (
|
<a name="l02522"></a>02522 <span class="vhdlkeyword">assign</span> <a class="code" href="classcondition.html#a4478c90a4669d8bd947561aaddfe3bfb">V</a> = <a class="code" href="classcondition.html#abac84a257e657e334871ef190cce9616">ccr</a>[<span class="vhdllogic">1</span>];
|
<a name="l02523"></a>02523 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a925f0004ba49b82dbdf7c4ae969ba6ed">`EA_TYPE_CONTROL_POSTINC</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a653530f090b85ba7bcd93912b8834412">`EA_TYPE_MEMORYALTER</a><span class="vhdlchar"></span> ||
|
<a name="l02523"></a>02523 <span class="vhdlkeyword">assign</span> <a class="code" href="classcondition.html#a88c2e82409be05b0e4072b5fd9fc6048">Z</a> = <a class="code" href="classcondition.html#abac84a257e657e334871ef190cce9616">ccr</a>[<span class="vhdllogic">2</span>];
|
<a name="l02524"></a>02524 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a17a8a468ddfc3bdb178081a368f4dd6c">`EA_TYPE_DATAALTER</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>
|
<a name="l02524"></a>02524 <span class="vhdlkeyword">assign</span> <a class="code" href="classcondition.html#a741ec53b25de93d917a650089cd95870">N</a> = <a class="code" href="classcondition.html#abac84a257e657e334871ef190cce9616">ccr</a>[<span class="vhdllogic">3</span>];
|
<a name="l02525"></a>02525 )) ? <a class="code" href="ao68000_8v.html#a02dc58bcc0412d6c93647a1304f20443">`MICROPC_SAVE_EA_An_plus</a><span class="vhdlchar"></span> <span class="keyword">// (An)+</span>
|
<a name="l02525"></a>02525
|
<a name="l02526"></a>02526 :
|
<a name="l02526"></a>02526 <span class="vhdlkeyword">assign</span> <a class="code" href="classcondition.html#acb19756f5d198b371846bce84e08d569">condition</a> = (<a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a> == <span class="vhdllogic">4'b0000</span>) ? <span class="vhdllogic">1'b1</span> : <span class="keyword">// true</span>
|
<a name="l02527"></a>02527 (<a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b100</span> && (
|
<a name="l02527"></a>02527 (<a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a> == <span class="vhdllogic">4'b0001</span>) ? <span class="vhdllogic">1'b0</span> : <span class="keyword">// false</span>
|
<a name="l02528"></a>02528 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a41499eaa1b7aa62f455a07e5435d754a">`EA_TYPE_CONTROLALTER_PREDEC</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a17a8a468ddfc3bdb178081a368f4dd6c">`EA_TYPE_DATAALTER</a><span class="vhdlchar"></span> ||
|
<a name="l02528"></a>02528 (<a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a> == <span class="vhdllogic">4'b0010</span>) ? ~<a class="code" href="classcondition.html#a3f5fcf283ca56b2cfe4269cff52ee925">C</a> & ~<a class="code" href="classcondition.html#a88c2e82409be05b0e4072b5fd9fc6048">Z</a> : <span class="keyword">// high</span>
|
<a name="l02529"></a>02529 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a653530f090b85ba7bcd93912b8834412">`EA_TYPE_MEMORYALTER</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>
|
<a name="l02529"></a>02529 (<a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a> == <span class="vhdllogic">4'b0011</span>) ? <a class="code" href="classcondition.html#a3f5fcf283ca56b2cfe4269cff52ee925">C</a> | <a class="code" href="classcondition.html#a88c2e82409be05b0e4072b5fd9fc6048">Z</a> : <span class="keyword">// low or same</span>
|
<a name="l02530"></a>02530 )) ? <a class="code" href="ao68000_8v.html#ae4c00f630c944a41db777f7b51ee052d">`MICROPC_SAVE_EA_minus_An</a><span class="vhdlchar"></span> <span class="keyword">// -(An)</span>
|
<a name="l02530"></a>02530 (<a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a> == <span class="vhdllogic">4'b0100</span>) ? ~<a class="code" href="classcondition.html#a3f5fcf283ca56b2cfe4269cff52ee925">C</a> : <span class="keyword">// carry clear</span>
|
<a name="l02531"></a>02531 :
|
<a name="l02531"></a>02531 (<a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a> == <span class="vhdllogic">4'b0101</span>) ? <a class="code" href="classcondition.html#a3f5fcf283ca56b2cfe4269cff52ee925">C</a> : <span class="keyword">// carry set</span>
|
<a name="l02532"></a>02532 <span class="vhdllogic">9'd0</span> <span class="keyword">// no ea needed</span>
|
<a name="l02532"></a>02532 (<a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a> == <span class="vhdllogic">4'b0110</span>) ? ~<a class="code" href="classcondition.html#a88c2e82409be05b0e4072b5fd9fc6048">Z</a> : <span class="keyword">// not equal</span>
|
<a name="l02533"></a>02533 ;
|
<a name="l02533"></a>02533 (<a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a> == <span class="vhdllogic">4'b0111</span>) ? <a class="code" href="classcondition.html#a88c2e82409be05b0e4072b5fd9fc6048">Z</a> : <span class="keyword">// equal</span>
|
<a name="l02534"></a>02534
|
<a name="l02534"></a>02534 (<a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a> == <span class="vhdllogic">4'b1000</span>) ? ~<a class="code" href="classcondition.html#a4478c90a4669d8bd947561aaddfe3bfb">V</a> : <span class="keyword">// overflow clear</span>
|
<a name="l02535"></a>02535 <span class="vhdlkeyword">endmodule</span>
|
<a name="l02535"></a>02535 (<a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a> == <span class="vhdllogic">4'b1001</span>) ? <a class="code" href="classcondition.html#a4478c90a4669d8bd947561aaddfe3bfb">V</a> : <span class="keyword">// overflow set</span>
|
<a name="l02536"></a>02536
|
<a name="l02536"></a>02536 (<a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a> == <span class="vhdllogic">4'b1010</span>) ? ~<a class="code" href="classcondition.html#a741ec53b25de93d917a650089cd95870">N</a> : <span class="keyword">// plus</span>
|
<a name="l02537"></a>02537 <span class="keyword">/***********************************************************************************************************************</span>
|
<a name="l02537"></a>02537 (<a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a> == <span class="vhdllogic">4'b1011</span>) ? <a class="code" href="classcondition.html#a741ec53b25de93d917a650089cd95870">N</a> : <span class="keyword">// minus</span>
|
<a name="l02538"></a>02538 <span class="keyword"> Condition</span>
|
<a name="l02538"></a>02538 (<a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a> == <span class="vhdllogic">4'b1100</span>) ? (<a class="code" href="classcondition.html#a741ec53b25de93d917a650089cd95870">N</a> & <a class="code" href="classcondition.html#a4478c90a4669d8bd947561aaddfe3bfb">V</a>) | (~<a class="code" href="classcondition.html#a741ec53b25de93d917a650089cd95870">N</a> & ~<a class="code" href="classcondition.html#a4478c90a4669d8bd947561aaddfe3bfb">V</a>) : <span class="keyword">// greater or equal</span>
|
<a name="l02539"></a>02539 <span class="keyword"> ***********************************************************************************************************************/</span>
|
<a name="l02539"></a>02539 (<a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a> == <span class="vhdllogic">4'b1101</span>) ? (<a class="code" href="classcondition.html#a741ec53b25de93d917a650089cd95870">N</a> & ~<a class="code" href="classcondition.html#a4478c90a4669d8bd947561aaddfe3bfb">V</a>) | (~<a class="code" href="classcondition.html#a741ec53b25de93d917a650089cd95870">N</a> & <a class="code" href="classcondition.html#a4478c90a4669d8bd947561aaddfe3bfb">V</a>) : <span class="keyword">// less than</span>
|
<a name="l02540"></a>02540
|
<a name="l02540"></a>02540 (<a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a> == <span class="vhdllogic">4'b1110</span>) ? (<a class="code" href="classcondition.html#a741ec53b25de93d917a650089cd95870">N</a> & <a class="code" href="classcondition.html#a4478c90a4669d8bd947561aaddfe3bfb">V</a> & ~<a class="code" href="classcondition.html#a88c2e82409be05b0e4072b5fd9fc6048">Z</a>) | (~<a class="code" href="classcondition.html#a741ec53b25de93d917a650089cd95870">N</a> & ~<a class="code" href="classcondition.html#a4478c90a4669d8bd947561aaddfe3bfb">V</a> & ~<a class="code" href="classcondition.html#a88c2e82409be05b0e4072b5fd9fc6048">Z</a>) : <span class="keyword">// greater than</span>
|
<a name="l02541"></a>02541
|
<a name="l02541"></a>02541 (<a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a> == <span class="vhdllogic">4'b1111</span>) ? (<a class="code" href="classcondition.html#a88c2e82409be05b0e4072b5fd9fc6048">Z</a>) | (<a class="code" href="classcondition.html#a741ec53b25de93d917a650089cd95870">N</a> & ~<a class="code" href="classcondition.html#a4478c90a4669d8bd947561aaddfe3bfb">V</a>) | (~<a class="code" href="classcondition.html#a741ec53b25de93d917a650089cd95870">N</a> & <a class="code" href="classcondition.html#a4478c90a4669d8bd947561aaddfe3bfb">V</a>) : <span class="keyword">// less or equal</span>
|
<a name="l02547"></a><a class="code" href="classcondition.html">02547</a> <span class="vhdlkeyword">module</span> <a class="code" href="classcondition.html">condition</a>(
|
<a name="l02542"></a>02542 <span class="vhdllogic">1'b0</span>;
|
<a name="l02548"></a><a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">02548</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] <a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a>,
|
<a name="l02543"></a>02543 <span class="vhdlkeyword">endmodule</span>
|
<a name="l02549"></a><a class="code" href="classcondition.html#abac84a257e657e334871ef190cce9616">02549</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <a class="code" href="classcondition.html#abac84a257e657e334871ef190cce9616">ccr</a>,
|
<a name="l02544"></a>02544
|
<a name="l02550"></a><a class="code" href="classcondition.html#acb19756f5d198b371846bce84e08d569">02550</a> <span class="vhdlkeyword">output</span> <a class="code" href="classcondition.html#acb19756f5d198b371846bce84e08d569">condition</a>
|
<a name="l02545"></a>02545 <span class="keyword">/***********************************************************************************************************************</span>
|
<a name="l02551"></a>02551 );
|
<a name="l02546"></a>02546 <span class="keyword"> ALU</span>
|
<a name="l02552"></a>02552
|
<a name="l02547"></a>02547 <span class="keyword"> ***********************************************************************************************************************/</span>
|
<a name="l02553"></a><a class="code" href="classcondition.html#a741ec53b25de93d917a650089cd95870">02553</a> <span class="vhdlkeyword">wire</span> <a class="code" href="classcondition.html#a3f5fcf283ca56b2cfe4269cff52ee925">C</a>,<a class="code" href="classcondition.html#a4478c90a4669d8bd947561aaddfe3bfb">V</a>,<a class="code" href="classcondition.html#a88c2e82409be05b0e4072b5fd9fc6048">Z</a>,<a class="code" href="classcondition.html#a741ec53b25de93d917a650089cd95870">N</a>;
|
<a name="l02548"></a>02548
|
<a name="l02554"></a>02554 <span class="vhdlkeyword">assign</span> <a class="code" href="classcondition.html#a3f5fcf283ca56b2cfe4269cff52ee925">C</a> = <a class="code" href="classcondition.html#abac84a257e657e334871ef190cce9616">ccr</a>[<span class="vhdllogic">0</span>];
|
<a name="l02549"></a>02549
|
<a name="l02555"></a>02555 <span class="vhdlkeyword">assign</span> <a class="code" href="classcondition.html#a4478c90a4669d8bd947561aaddfe3bfb">V</a> = <a class="code" href="classcondition.html#abac84a257e657e334871ef190cce9616">ccr</a>[<span class="vhdllogic">1</span>];
|
<a name="l02558"></a><a class="code" href="classalu.html">02558</a> <span class="vhdlkeyword">module</span> <a class="code" href="classalu.html">alu</a>(
|
<a name="l02556"></a>02556 <span class="vhdlkeyword">assign</span> <a class="code" href="classcondition.html#a88c2e82409be05b0e4072b5fd9fc6048">Z</a> = <a class="code" href="classcondition.html#abac84a257e657e334871ef190cce9616">ccr</a>[<span class="vhdllogic">2</span>];
|
<a name="l02559"></a><a class="code" href="classalu.html#aaa60d149641cba8468ad7791eb5999ab">02559</a> <span class="vhdlkeyword">input</span> <a class="code" href="classalu.html#aaa60d149641cba8468ad7791eb5999ab">clock</a>,
|
<a name="l02557"></a>02557 <span class="vhdlkeyword">assign</span> <a class="code" href="classcondition.html#a741ec53b25de93d917a650089cd95870">N</a> = <a class="code" href="classcondition.html#abac84a257e657e334871ef190cce9616">ccr</a>[<span class="vhdllogic">3</span>];
|
<a name="l02560"></a><a class="code" href="classalu.html#a5e83fb99cb897f45ca128fa1594c5967">02560</a> <span class="vhdlkeyword">input</span> <a class="code" href="classalu.html#a5e83fb99cb897f45ca128fa1594c5967">reset_n</a>,
|
<a name="l02558"></a>02558
|
<a name="l02561"></a>02561
|
<a name="l02559"></a>02559 <span class="vhdlkeyword">assign</span> <a class="code" href="classcondition.html#acb19756f5d198b371846bce84e08d569">condition</a> = (<a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a> == <span class="vhdllogic">4'b0000</span>) ? <span class="vhdllogic">1'b1</span> : <span class="keyword">// true</span>
|
<a name="l02562"></a>02562 <span class="keyword">// only zero bit</span>
|
<a name="l02560"></a>02560 (<a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a> == <span class="vhdllogic">4'b0001</span>) ? <span class="vhdllogic">1'b0</span> : <span class="keyword">// false</span>
|
<a name="l02563"></a><a class="code" href="classalu.html#a379cf0ab5b30f07c291e327fc5bb194f">02563</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#a379cf0ab5b30f07c291e327fc5bb194f">address</a>,
|
<a name="l02561"></a>02561 (<a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a> == <span class="vhdllogic">4'b0010</span>) ? ~<a class="code" href="classcondition.html#a3f5fcf283ca56b2cfe4269cff52ee925">C</a> & ~<a class="code" href="classcondition.html#a88c2e82409be05b0e4072b5fd9fc6048">Z</a> : <span class="keyword">// high</span>
|
<a name="l02564"></a>02564 <span class="keyword">// only ir[11:9] and ir[6]</span>
|
<a name="l02562"></a>02562 (<a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a> == <span class="vhdllogic">4'b0011</span>) ? <a class="code" href="classcondition.html#a3f5fcf283ca56b2cfe4269cff52ee925">C</a> | <a class="code" href="classcondition.html#a88c2e82409be05b0e4072b5fd9fc6048">Z</a> : <span class="keyword">// low or same</span>
|
<a name="l02565"></a><a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">02565</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>,
|
<a name="l02563"></a>02563 (<a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a> == <span class="vhdllogic">4'b0100</span>) ? ~<a class="code" href="classcondition.html#a3f5fcf283ca56b2cfe4269cff52ee925">C</a> : <span class="keyword">// carry clear</span>
|
<a name="l02566"></a>02566 <span class="keyword">// byte 2'b00, word 2'b01, long 2'b10</span>
|
<a name="l02564"></a>02564 (<a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a> == <span class="vhdllogic">4'b0101</span>) ? <a class="code" href="classcondition.html#a3f5fcf283ca56b2cfe4269cff52ee925">C</a> : <span class="keyword">// carry set</span>
|
<a name="l02567"></a><a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">02567</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>,
|
<a name="l02565"></a>02565 (<a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a> == <span class="vhdllogic">4'b0110</span>) ? ~<a class="code" href="classcondition.html#a88c2e82409be05b0e4072b5fd9fc6048">Z</a> : <span class="keyword">// not equal</span>
|
<a name="l02568"></a>02568
|
<a name="l02566"></a>02566 (<a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a> == <span class="vhdllogic">4'b0111</span>) ? <a class="code" href="classcondition.html#a88c2e82409be05b0e4072b5fd9fc6048">Z</a> : <span class="keyword">// equal</span>
|
<a name="l02569"></a><a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">02569</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>,
|
<a name="l02567"></a>02567 (<a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a> == <span class="vhdllogic">4'b1000</span>) ? ~<a class="code" href="classcondition.html#a4478c90a4669d8bd947561aaddfe3bfb">V</a> : <span class="keyword">// overflow clear</span>
|
<a name="l02570"></a><a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">02570</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>,
|
<a name="l02568"></a>02568 (<a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a> == <span class="vhdllogic">4'b1001</span>) ? <a class="code" href="classcondition.html#a4478c90a4669d8bd947561aaddfe3bfb">V</a> : <span class="keyword">// overflow set</span>
|
<a name="l02571"></a>02571
|
<a name="l02569"></a>02569 (<a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a> == <span class="vhdllogic">4'b1010</span>) ? ~<a class="code" href="classcondition.html#a741ec53b25de93d917a650089cd95870">N</a> : <span class="keyword">// plus</span>
|
<a name="l02572"></a><a class="code" href="classalu.html#aaec5e2b3f347a2651f6456b7d0dafe16">02572</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#aaec5e2b3f347a2651f6456b7d0dafe16">interrupt_mask</a>,
|
<a name="l02570"></a>02570 (<a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a> == <span class="vhdllogic">4'b1011</span>) ? <a class="code" href="classcondition.html#a741ec53b25de93d917a650089cd95870">N</a> : <span class="keyword">// minus</span>
|
<a name="l02573"></a><a class="code" href="classalu.html#acd09435ce38c12172a01a2b3725577dc">02573</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">4</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#acd09435ce38c12172a01a2b3725577dc">alu_control</a>,
|
<a name="l02571"></a>02571 (<a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a> == <span class="vhdllogic">4'b1100</span>) ? (<a class="code" href="classcondition.html#a741ec53b25de93d917a650089cd95870">N</a> & <a class="code" href="classcondition.html#a4478c90a4669d8bd947561aaddfe3bfb">V</a>) | (~<a class="code" href="classcondition.html#a741ec53b25de93d917a650089cd95870">N</a> & ~<a class="code" href="classcondition.html#a4478c90a4669d8bd947561aaddfe3bfb">V</a>) : <span class="keyword">// greater or equal</span>
|
<a name="l02574"></a>02574
|
<a name="l02572"></a>02572 (<a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a> == <span class="vhdllogic">4'b1101</span>) ? (<a class="code" href="classcondition.html#a741ec53b25de93d917a650089cd95870">N</a> & ~<a class="code" href="classcondition.html#a4478c90a4669d8bd947561aaddfe3bfb">V</a>) | (~<a class="code" href="classcondition.html#a741ec53b25de93d917a650089cd95870">N</a> & <a class="code" href="classcondition.html#a4478c90a4669d8bd947561aaddfe3bfb">V</a>) : <span class="keyword">// less than</span>
|
<a name="l02575"></a><a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">02575</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>,
|
<a name="l02573"></a>02573 (<a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a> == <span class="vhdllogic">4'b1110</span>) ? (<a class="code" href="classcondition.html#a741ec53b25de93d917a650089cd95870">N</a> & <a class="code" href="classcondition.html#a4478c90a4669d8bd947561aaddfe3bfb">V</a> & ~<a class="code" href="classcondition.html#a88c2e82409be05b0e4072b5fd9fc6048">Z</a>) | (~<a class="code" href="classcondition.html#a741ec53b25de93d917a650089cd95870">N</a> & ~<a class="code" href="classcondition.html#a4478c90a4669d8bd947561aaddfe3bfb">V</a> & ~<a class="code" href="classcondition.html#a88c2e82409be05b0e4072b5fd9fc6048">Z</a>) : <span class="keyword">// greater than</span>
|
<a name="l02576"></a><a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">02576</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>,
|
<a name="l02574"></a>02574 (<a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a> == <span class="vhdllogic">4'b1111</span>) ? (<a class="code" href="classcondition.html#a88c2e82409be05b0e4072b5fd9fc6048">Z</a>) | (<a class="code" href="classcondition.html#a741ec53b25de93d917a650089cd95870">N</a> & ~<a class="code" href="classcondition.html#a4478c90a4669d8bd947561aaddfe3bfb">V</a>) | (~<a class="code" href="classcondition.html#a741ec53b25de93d917a650089cd95870">N</a> & <a class="code" href="classcondition.html#a4478c90a4669d8bd947561aaddfe3bfb">V</a>) : <span class="keyword">// less or equal</span>
|
|
<a name="l02575"></a>02575 <span class="vhdllogic">1'b0</span>;
|
|
<a name="l02576"></a>02576 <span class="vhdlkeyword">endmodule</span>
|
|
<a name="l02577"></a>02577
|
<a name="l02577"></a>02577
|
<a name="l02578"></a>02578 <span class="keyword">/***********************************************************************************************************************</span>
|
<a name="l02578"></a><a class="code" href="classalu.html#a41770492859599997a003e2681e7d955">02578</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> <a class="code" href="classalu.html#a41770492859599997a003e2681e7d955">alu_signal</a>,
|
<a name="l02579"></a>02579 <span class="keyword"> ALU</span>
|
<a name="l02579"></a><a class="code" href="classalu.html#ab6a8e15c686ee360ddad15cd4d995ea9">02579</a> <span class="vhdlkeyword">output</span> <a class="code" href="classalu.html#ab6a8e15c686ee360ddad15cd4d995ea9">alu_mult_div_ready</a>
|
<a name="l02580"></a>02580 <span class="keyword"> ***********************************************************************************************************************/</span>
|
<a name="l02580"></a>02580 );
|
<a name="l02581"></a>02581
|
<a name="l02581"></a>02581
|
<a name="l02582"></a>02582
|
<a name="l02582"></a>02582 <span class="keyword">//****************************************************** Altera-specific multiplication and division modules START</span>
|
<a name="l02591"></a><a class="code" href="classalu.html">02591</a> <span class="vhdlkeyword">module</span> <a class="code" href="classalu.html">alu</a>(
|
<a name="l02583"></a>02583 <span class="keyword">/* Multiplication and division modules.</span>
|
<a name="l02592"></a><a class="code" href="classalu.html#aaa60d149641cba8468ad7791eb5999ab">02592</a> <span class="vhdlkeyword">input</span> <a class="code" href="classalu.html#aaa60d149641cba8468ad7791eb5999ab">clock</a>,
|
<a name="l02584"></a>02584 <span class="keyword"> </span>
|
<a name="l02593"></a><a class="code" href="classalu.html#a5e83fb99cb897f45ca128fa1594c5967">02593</a> <span class="vhdlkeyword">input</span> <a class="code" href="classalu.html#a5e83fb99cb897f45ca128fa1594c5967">reset_n</a>,
|
<a name="l02585"></a>02585 <span class="keyword"> Currently this module contains:</span>
|
<a name="l02594"></a>02594
|
<a name="l02586"></a>02586 <span class="keyword"> - <em>lpm_mult</em> instantiation from Altera Megafunction/LPM library,</span>
|
<a name="l02595"></a>02595 <span class="keyword">// only zero bit</span>
|
<a name="l02587"></a>02587 <span class="keyword"> - a sequential state machine for division written by Frederic Requin</span>
|
<a name="l02596"></a><a class="code" href="classalu.html#a379cf0ab5b30f07c291e327fc5bb194f">02596</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#a379cf0ab5b30f07c291e327fc5bb194f">address</a>,
|
<a name="l02588"></a>02588 <span class="keyword"> */</span>
|
<a name="l02597"></a>02597 <span class="keyword">// only ir[11:9] and ir[6]</span>
|
<a name="l02589"></a>02589
|
<a name="l02598"></a><a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">02598</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>,
|
<a name="l02590"></a><a class="code" href="classalu.html#abbf525422eca0279b697f742b90237e0">02590</a> <span class="vhdlkeyword">wire</span> <a class="code" href="classalu.html#abbf525422eca0279b697f742b90237e0">mult_div_sign</a> = <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>];
|
<a name="l02599"></a>02599 <span class="keyword">// byte 2'b00, word 2'b01, long 2'b10</span>
|
<a name="l02591"></a>02591
|
<a name="l02600"></a><a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">02600</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>,
|
<a name="l02592"></a>02592 <span class="keyword">// 18-2 - division calculation, 1 - waiting for result read, 0 - idle</span>
|
<a name="l02601"></a>02601
|
<a name="l02593"></a><a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">02593</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">4</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a>;
|
<a name="l02602"></a><a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">02602</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>,
|
<a name="l02594"></a><a class="code" href="classalu.html#ab225284f49794091a5a28e73b8b13e14">02594</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">16</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#ab225284f49794091a5a28e73b8b13e14">quotient</a>;
|
<a name="l02603"></a><a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">02603</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>,
|
<a name="l02595"></a><a class="code" href="classalu.html#a9c2364593889150d7f5679fc33b0f1fa">02595</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#a0c2a64b2f5dd32b2159ca0f29de360aa">dividend</a>, <a class="code" href="classalu.html#a9c2364593889150d7f5679fc33b0f1fa">divider</a>;
|
<a name="l02604"></a>02604
|
<a name="l02596"></a>02596
|
<a name="l02605"></a><a class="code" href="classalu.html#aaec5e2b3f347a2651f6456b7d0dafe16">02605</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#aaec5e2b3f347a2651f6456b7d0dafe16">interrupt_mask</a>,
|
<a name="l02597"></a>02597 <span class="keyword">// Compute the difference with borrow</span>
|
<a name="l02606"></a><a class="code" href="classalu.html#acd09435ce38c12172a01a2b3725577dc">02606</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">4</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#acd09435ce38c12172a01a2b3725577dc">alu_control</a>,
|
<a name="l02598"></a><a class="code" href="classalu.html#a07af2646e5b543c5be95dddb22fd4ea6">02598</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">32</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#a07af2646e5b543c5be95dddb22fd4ea6">div_diff</a> = (<a class="code" href="classalu.html#a0c2a64b2f5dd32b2159ca0f29de360aa">dividend</a> - <a class="code" href="classalu.html#a9c2364593889150d7f5679fc33b0f1fa">divider</a>);
|
<a name="l02607"></a>02607
|
<a name="l02599"></a>02599
|
<a name="l02608"></a><a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">02608</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>,
|
<a name="l02600"></a>02600 <span class="keyword">// Overflow flag: when (quotient >= 65536) or (signed division and (quotient >= 32768 or quotient < -32768))</span>
|
<a name="l02609"></a><a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">02609</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>,
|
<a name="l02601"></a><a class="code" href="classalu.html#a8d11b113e74362e74035541da1b0a02e">02601</a> <span class="vhdlkeyword">wire</span> <a class="code" href="classalu.html#a8d11b113e74362e74035541da1b0a02e">div_overflow</a> =
|
<a name="l02610"></a>02610
|
<a name="l02602"></a>02602 (<a class="code" href="classalu.html#ab225284f49794091a5a28e73b8b13e14">quotient</a>[<span class="vhdllogic">16</span>] == <span class="vhdllogic">1'b1</span> ||
|
<a name="l02611"></a><a class="code" href="classalu.html#a41770492859599997a003e2681e7d955">02611</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> <a class="code" href="classalu.html#a41770492859599997a003e2681e7d955">alu_signal</a>,
|
<a name="l02603"></a>02603 (<a class="code" href="classalu.html#abbf525422eca0279b697f742b90237e0">mult_div_sign</a> == <span class="vhdllogic">1'b1</span> && (
|
<a name="l02612"></a><a class="code" href="classalu.html#ab6a8e15c686ee360ddad15cd4d995ea9">02612</a> <span class="vhdlkeyword">output</span> <a class="code" href="classalu.html#ab6a8e15c686ee360ddad15cd4d995ea9">alu_mult_div_ready</a>
|
<a name="l02604"></a>02604 ((<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>] ^ <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">15</span>]) == <span class="vhdllogic">1'b0</span> && <a class="code" href="classalu.html#ab225284f49794091a5a28e73b8b13e14">quotient</a>[<span class="vhdllogic">15</span>] == <span class="vhdllogic">1'b1</span>) ||
|
<a name="l02613"></a>02613 );
|
<a name="l02605"></a>02605 ((<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>] ^ <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">15</span>]) == <span class="vhdllogic">1'b1</span> && <a class="code" href="classalu.html#ab225284f49794091a5a28e73b8b13e14">quotient</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] > <span class="vhdllogic">16'd32768</span>) )));
|
<a name="l02614"></a>02614
|
<a name="l02606"></a>02606
|
<a name="l02615"></a>02615 <span class="keyword">//****************************************************** Altera-specific multiplication and division modules START</span>
|
<a name="l02607"></a><a class="code" href="classalu.html#af65ee78a38f09889c3b8c9efc759f559">02607</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#af65ee78a38f09889c3b8c9efc759f559">div_quotient</a> =
|
<a name="l02616"></a>02616 <span class="keyword">/* Multiplication and division modules.</span>
|
<a name="l02608"></a>02608 <span class="keyword">// positive quotient</span>
|
<a name="l02617"></a>02617 <span class="keyword"> </span>
|
<a name="l02609"></a>02609 (((<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>] ^ <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">15</span>]) & <a class="code" href="classalu.html#abbf525422eca0279b697f742b90237e0">mult_div_sign</a>) == <span class="vhdllogic">1'b0</span>)? <a class="code" href="classalu.html#ab225284f49794091a5a28e73b8b13e14">quotient</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] :
|
<a name="l02618"></a>02618 <span class="keyword"> Currently this module contains:</span>
|
<a name="l02610"></a>02610 <span class="keyword">// negative quotient</span>
|
<a name="l02619"></a>02619 <span class="keyword"> - <em>lpm_mult</em> instantiation from Altera Megafunction/LPM library,</span>
|
<a name="l02611"></a>02611 -<a class="code" href="classalu.html#ab225284f49794091a5a28e73b8b13e14">quotient</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>];
|
<a name="l02620"></a>02620 <span class="keyword"> - a sequential state machine for division written by Frederic Requin</span>
|
<a name="l02612"></a>02612
|
<a name="l02621"></a>02621 <span class="keyword"> */</span>
|
<a name="l02613"></a><a class="code" href="classalu.html#ad32bb10563baa2d2d78c2a23e8f2219e">02613</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#ad32bb10563baa2d2d78c2a23e8f2219e">div_remainder</a> =
|
<a name="l02622"></a>02622
|
<a name="l02614"></a>02614 <span class="keyword">// positive remainder</span>
|
<a name="l02623"></a><a class="code" href="classalu.html#abbf525422eca0279b697f742b90237e0">02623</a> <span class="vhdlkeyword">wire</span> <a class="code" href="classalu.html#abbf525422eca0279b697f742b90237e0">mult_div_sign</a> = <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>];
|
<a name="l02615"></a>02615 ((<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>] & <a class="code" href="classalu.html#abbf525422eca0279b697f742b90237e0">mult_div_sign</a>) == <span class="vhdllogic">1'b0</span>)? <a class="code" href="classalu.html#a0c2a64b2f5dd32b2159ca0f29de360aa">dividend</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] :
|
<a name="l02624"></a>02624
|
<a name="l02616"></a>02616 <span class="keyword">// negative remainder</span>
|
<a name="l02625"></a>02625 <span class="keyword">// 18-2 - division calculation, 1 - waiting for result read, 0 - idle</span>
|
<a name="l02617"></a>02617 -<a class="code" href="classalu.html#a0c2a64b2f5dd32b2159ca0f29de360aa">dividend</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>];
|
<a name="l02626"></a><a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">02626</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">4</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a>;
|
<a name="l02618"></a>02618
|
<a name="l02627"></a><a class="code" href="classalu.html#ab225284f49794091a5a28e73b8b13e14">02627</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">16</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#ab225284f49794091a5a28e73b8b13e14">quotient</a>;
|
<a name="l02619"></a><a class="code" href="classalu.html#a833db0d5eda614d712b846b259c0f4d3">02619</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classalu.html#aaa60d149641cba8468ad7791eb5999ab">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classalu.html#a5e83fb99cb897f45ca128fa1594c5967">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l02628"></a><a class="code" href="classalu.html#a9c2364593889150d7f5679fc33b0f1fa">02628</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#a0c2a64b2f5dd32b2159ca0f29de360aa">dividend</a>, <a class="code" href="classalu.html#a9c2364593889150d7f5679fc33b0f1fa">divider</a>;
|
<a name="l02620"></a>02620 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a5e83fb99cb897f45ca128fa1594c5967">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
|
<a name="l02621"></a>02621 <a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a> <= <span class="vhdllogic">5'd0</span>;
|
|
<a name="l02622"></a>02622 <span class="vhdlkeyword">end</span>
|
|
<a name="l02623"></a>02623 <span class="keyword">// Cycle #0 : load the registers</span>
|
|
<a name="l02624"></a>02624 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#acd09435ce38c12172a01a2b3725577dc">alu_control</a> == <a class="code" href="ao68000_8v.html#aed07d190bb88f0cce7768028698020f9">`ALU_MULS_MULU_DIVS_DIVU</a><span class="vhdlchar"></span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1000</span> && <a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a> == <span class="vhdllogic">5'd0</span>) <span class="vhdlkeyword">begin</span>
|
|
<a name="l02625"></a>02625 <span class="keyword">// 17 cycles to finish + wait state</span>
|
|
<a name="l02626"></a>02626 <a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a> <= <span class="vhdllogic">5'd18</span>;
|
|
<a name="l02627"></a>02627 <span class="keyword">// Clear the quotient</span>
|
|
<a name="l02628"></a>02628 <a class="code" href="classalu.html#ab225284f49794091a5a28e73b8b13e14">quotient</a> <= <span class="vhdllogic">17'd0</span>;
|
<a name="l02629"></a>02629
|
<a name="l02629"></a>02629
|
<a name="l02630"></a>02630 <span class="keyword">// Compute the difference with borrow</span>
|
<a name="l02630"></a>02630 <span class="keyword">// Unsigned divide or positive numerator</span>
|
<a name="l02631"></a><a class="code" href="classalu.html#a07af2646e5b543c5be95dddb22fd4ea6">02631</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">32</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#a07af2646e5b543c5be95dddb22fd4ea6">div_diff</a> = (<a class="code" href="classalu.html#a0c2a64b2f5dd32b2159ca0f29de360aa">dividend</a> - <a class="code" href="classalu.html#a9c2364593889150d7f5679fc33b0f1fa">divider</a>);
|
<a name="l02631"></a>02631 <span class="vhdlkeyword">if</span> ((!<a class="code" href="classalu.html#abbf525422eca0279b697f742b90237e0">mult_div_sign</a>) || (!<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>])) <a class="code" href="classalu.html#a0c2a64b2f5dd32b2159ca0f29de360aa">dividend</a> <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>;
|
<a name="l02632"></a>02632
|
<a name="l02632"></a>02632 <span class="keyword">// Negative numerator</span>
|
<a name="l02633"></a>02633 <span class="keyword">// Overflow flag: when (quotient >= 65536) or (signed division and (quotient >= 32768 or quotient < -32768))</span>
|
<a name="l02633"></a>02633 <span class="vhdlkeyword">else</span> <a class="code" href="classalu.html#a0c2a64b2f5dd32b2159ca0f29de360aa">dividend</a> <= -<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>;
|
<a name="l02634"></a><a class="code" href="classalu.html#a8d11b113e74362e74035541da1b0a02e">02634</a> <span class="vhdlkeyword">wire</span> <a class="code" href="classalu.html#a8d11b113e74362e74035541da1b0a02e">div_overflow</a> =
|
<a name="l02634"></a>02634
|
<a name="l02635"></a>02635 (<a class="code" href="classalu.html#ab225284f49794091a5a28e73b8b13e14">quotient</a>[<span class="vhdllogic">16</span>] == <span class="vhdllogic">1'b1</span> ||
|
<a name="l02635"></a>02635 <span class="keyword">// Unsigned divide or positive denominator</span>
|
<a name="l02636"></a>02636 (<a class="code" href="classalu.html#abbf525422eca0279b697f742b90237e0">mult_div_sign</a> == <span class="vhdllogic">1'b1</span> && (
|
<a name="l02636"></a>02636 <span class="vhdlkeyword">if</span> ((!<a class="code" href="classalu.html#abbf525422eca0279b697f742b90237e0">mult_div_sign</a>) || (!<a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">15</span>])) <a class="code" href="classalu.html#a9c2364593889150d7f5679fc33b0f1fa">divider</a> <= {<a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>],<span class="vhdllogic">16'd0</span>};
|
<a name="l02637"></a>02637 ((<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>] ^ <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">15</span>]) == <span class="vhdllogic">1'b0</span> && <a class="code" href="classalu.html#ab225284f49794091a5a28e73b8b13e14">quotient</a>[<span class="vhdllogic">15</span>] == <span class="vhdllogic">1'b1</span>) ||
|
<a name="l02637"></a>02637 <span class="keyword">// Negative denominator</span>
|
<a name="l02638"></a>02638 ((<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>] ^ <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">15</span>]) == <span class="vhdllogic">1'b1</span> && <a class="code" href="classalu.html#ab225284f49794091a5a28e73b8b13e14">quotient</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] > <span class="vhdllogic">16'd32768</span>) )));
|
<a name="l02638"></a>02638 <span class="vhdlkeyword">else</span> <a class="code" href="classalu.html#a9c2364593889150d7f5679fc33b0f1fa">divider</a> <= {-<a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>],<span class="vhdllogic">16'd0</span>};
|
<a name="l02639"></a>02639
|
<a name="l02639"></a>02639 <span class="vhdlkeyword">end</span>
|
<a name="l02640"></a><a class="code" href="classalu.html#af65ee78a38f09889c3b8c9efc759f559">02640</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#af65ee78a38f09889c3b8c9efc759f559">div_quotient</a> =
|
<a name="l02640"></a>02640 <span class="keyword">// Cycles #1-17 : division calculation</span>
|
<a name="l02641"></a>02641 <span class="keyword">// positive quotient</span>
|
<a name="l02641"></a>02641 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a> > <span class="vhdllogic">5'd1</span>) <span class="vhdlkeyword">begin</span>
|
<a name="l02642"></a>02642 (((<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>] ^ <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">15</span>]) & <a class="code" href="classalu.html#abbf525422eca0279b697f742b90237e0">mult_div_sign</a>) == <span class="vhdllogic">1'b0</span>)? <a class="code" href="classalu.html#ab225284f49794091a5a28e73b8b13e14">quotient</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] :
|
<a name="l02642"></a>02642 <span class="keyword">// Check difference's sign</span>
|
<a name="l02643"></a>02643 <span class="keyword">// negative quotient</span>
|
<a name="l02643"></a>02643 <span class="vhdlkeyword">if</span> (!<a class="code" href="classalu.html#a07af2646e5b543c5be95dddb22fd4ea6">div_diff</a>[<span class="vhdllogic">32</span>]) <span class="vhdlkeyword">begin</span>
|
<a name="l02644"></a>02644 -<a class="code" href="classalu.html#ab225284f49794091a5a28e73b8b13e14">quotient</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>];
|
<a name="l02644"></a>02644 <span class="keyword">// Difference is positive : shift a one</span>
|
<a name="l02645"></a>02645
|
<a name="l02645"></a>02645 <a class="code" href="classalu.html#a0c2a64b2f5dd32b2159ca0f29de360aa">dividend</a> <= <a class="code" href="classalu.html#a07af2646e5b543c5be95dddb22fd4ea6">div_diff</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
<a name="l02646"></a><a class="code" href="classalu.html#ad32bb10563baa2d2d78c2a23e8f2219e">02646</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#ad32bb10563baa2d2d78c2a23e8f2219e">div_remainder</a> =
|
<a name="l02646"></a>02646 <a class="code" href="classalu.html#ab225284f49794091a5a28e73b8b13e14">quotient</a> <= {<a class="code" href="classalu.html#ab225284f49794091a5a28e73b8b13e14">quotient</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>], <span class="vhdllogic">1'b1</span>};
|
<a name="l02647"></a>02647 <span class="keyword">// positive remainder</span>
|
<a name="l02647"></a>02647 <span class="vhdlkeyword">end</span>
|
<a name="l02648"></a>02648 ((<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>] & <a class="code" href="classalu.html#abbf525422eca0279b697f742b90237e0">mult_div_sign</a>) == <span class="vhdllogic">1'b0</span>)? <a class="code" href="classalu.html#a0c2a64b2f5dd32b2159ca0f29de360aa">dividend</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] :
|
<a name="l02648"></a>02648 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
<a name="l02649"></a>02649 <span class="keyword">// negative remainder</span>
|
<a name="l02649"></a>02649 <span class="keyword">// Difference is negative : shift a zero</span>
|
<a name="l02650"></a>02650 -<a class="code" href="classalu.html#a0c2a64b2f5dd32b2159ca0f29de360aa">dividend</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>];
|
<a name="l02650"></a>02650 <a class="code" href="classalu.html#ab225284f49794091a5a28e73b8b13e14">quotient</a> <= {<a class="code" href="classalu.html#ab225284f49794091a5a28e73b8b13e14">quotient</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>], <span class="vhdllogic">1'b0</span>};
|
<a name="l02651"></a>02651
|
<a name="l02651"></a>02651 <span class="vhdlkeyword">end</span>
|
<a name="l02652"></a><a class="code" href="classalu.html#a833db0d5eda614d712b846b259c0f4d3">02652</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classalu.html#aaa60d149641cba8468ad7791eb5999ab">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classalu.html#a5e83fb99cb897f45ca128fa1594c5967">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l02652"></a>02652 <span class="keyword">// Shift right divider</span>
|
<a name="l02653"></a>02653 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a5e83fb99cb897f45ca128fa1594c5967">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
<a name="l02653"></a>02653 <a class="code" href="classalu.html#a9c2364593889150d7f5679fc33b0f1fa">divider</a> <= {<span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#a9c2364593889150d7f5679fc33b0f1fa">divider</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">1</span>]};
|
<a name="l02654"></a>02654 <a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a> <= <span class="vhdllogic">5'd0</span>;
|
<a name="l02654"></a>02654 <span class="keyword">// Count one bit</span>
|
<a name="l02655"></a>02655 <span class="vhdlkeyword">end</span>
|
<a name="l02655"></a>02655 <a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a> <= <a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a> - <span class="vhdllogic">5'd1</span>;
|
<a name="l02656"></a>02656 <span class="keyword">// Cycle #0 : load the registers</span>
|
<a name="l02656"></a>02656 <span class="vhdlkeyword">end</span>
|
<a name="l02657"></a>02657 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#acd09435ce38c12172a01a2b3725577dc">alu_control</a> == <a class="code" href="ao68000_8v.html#aed07d190bb88f0cce7768028698020f9">`ALU_MULS_MULU_DIVS_DIVU</a><span class="vhdlchar"></span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1000</span> && <a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a> == <span class="vhdllogic">5'd0</span>) <span class="vhdlkeyword">begin</span>
|
<a name="l02657"></a>02657 <span class="keyword">// result read</span>
|
<a name="l02658"></a>02658 <span class="keyword">// 17 cycles to finish + wait state</span>
|
<a name="l02658"></a>02658 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#acd09435ce38c12172a01a2b3725577dc">alu_control</a> == <a class="code" href="ao68000_8v.html#aed07d190bb88f0cce7768028698020f9">`ALU_MULS_MULU_DIVS_DIVU</a><span class="vhdlchar"></span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1000</span> && <a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a> == <span class="vhdllogic">5'd1</span>) <span class="vhdlkeyword">begin</span>
|
<a name="l02659"></a>02659 <a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a> <= <span class="vhdllogic">5'd18</span>;
|
<a name="l02659"></a>02659 <span class="keyword">// goto idle</span>
|
<a name="l02660"></a>02660 <span class="keyword">// Clear the quotient</span>
|
<a name="l02660"></a>02660 <a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a> <= <a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a> - <span class="vhdllogic">5'd1</span>;
|
<a name="l02661"></a>02661 <a class="code" href="classalu.html#ab225284f49794091a5a28e73b8b13e14">quotient</a> <= <span class="vhdllogic">17'd0</span>;
|
<a name="l02661"></a>02661 <span class="vhdlkeyword">end</span>
|
<a name="l02662"></a>02662
|
<a name="l02662"></a>02662 <span class="vhdlkeyword">end</span>
|
<a name="l02663"></a>02663 <span class="keyword">// Unsigned divide or positive numerator</span>
|
<a name="l02663"></a>02663
|
<a name="l02664"></a>02664 <span class="vhdlkeyword">if</span> ((!<a class="code" href="classalu.html#abbf525422eca0279b697f742b90237e0">mult_div_sign</a>) || (!<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>])) <a class="code" href="classalu.html#a0c2a64b2f5dd32b2159ca0f29de360aa">dividend</a> <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>;
|
<a name="l02664"></a>02664 <span class="keyword">// MULS/MULU: 16-bit operand1[15:0] signed/unsigned * operand2[15:0] signed/unsigned = 32-bit result signed/unsigned</span>
|
<a name="l02665"></a>02665 <span class="keyword">// Negative numerator</span>
|
<a name="l02665"></a>02665 <span class="keyword">// Optimization by Frederic Requin</span>
|
<a name="l02666"></a>02666 <span class="vhdlkeyword">else</span> <a class="code" href="classalu.html#a0c2a64b2f5dd32b2159ca0f29de360aa">dividend</a> <= -<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>;
|
<a name="l02666"></a><a class="code" href="classalu.html#aff5530027f36561324e060e703004b6b">02666</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">33</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#aff5530027f36561324e060e703004b6b">mult_result</a>;
|
<a name="l02667"></a>02667
|
<a name="l02667"></a>02667
|
<a name="l02668"></a>02668 <span class="keyword">// Unsigned divide or positive denominator</span>
|
<a name="l02668"></a><a class="code" href="classalu.html#a6447478386a93e0306b7cb09937c23c3">02668</a> <a class="code" href="classalu.html#a6447478386a93e0306b7cb09937c23c3">lpm_mult</a> <span class="vhdlchar">muls</span>(
|
<a name="l02669"></a>02669 <span class="vhdlkeyword">if</span> ((!<a class="code" href="classalu.html#abbf525422eca0279b697f742b90237e0">mult_div_sign</a>) || (!<a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">15</span>])) <a class="code" href="classalu.html#a9c2364593889150d7f5679fc33b0f1fa">divider</a> <= {<a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>],<span class="vhdllogic">16'd0</span>};
|
<a name="l02669"></a>02669 .<a class="code" href="classalu.html#aaa60d149641cba8468ad7791eb5999ab">clock</a> (<a class="code" href="classalu.html#aaa60d149641cba8468ad7791eb5999ab">clock</a>),
|
<a name="l02670"></a>02670 <span class="keyword">// Negative denominator</span>
|
<a name="l02670"></a>02670 .<span class="vhdlchar">dataa</span> ({<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>] & <a class="code" href="classalu.html#abbf525422eca0279b697f742b90237e0">mult_div_sign</a>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>]}),
|
<a name="l02671"></a>02671 <span class="vhdlkeyword">else</span> <a class="code" href="classalu.html#a9c2364593889150d7f5679fc33b0f1fa">divider</a> <= {-<a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>],<span class="vhdllogic">16'd0</span>};
|
<a name="l02671"></a>02671 .<span class="vhdlchar">datab</span> ({<a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">15</span>] & <a class="code" href="classalu.html#abbf525422eca0279b697f742b90237e0">mult_div_sign</a>, <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>]}),
|
<a name="l02672"></a>02672 <span class="vhdlkeyword">end</span>
|
<a name="l02672"></a>02672 .<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> (<a class="code" href="classalu.html#aff5530027f36561324e060e703004b6b">mult_result</a>)
|
<a name="l02673"></a>02673 <span class="keyword">// Cycles #1-17 : division calculation</span>
|
<a name="l02673"></a>02673 );
|
<a name="l02674"></a>02674 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a> > <span class="vhdllogic">5'd1</span>) <span class="vhdlkeyword">begin</span>
|
<a name="l02674"></a>02674 <span class="vhdlkeyword">defparam</span>
|
<a name="l02675"></a>02675 <span class="keyword">// Check difference's sign</span>
|
<a name="l02675"></a>02675 <span class="vhdlchar">muls</span>.<span class="vhdlchar">lpm_widtha</span> = <span class="vhdllogic">17</span>,
|
<a name="l02676"></a>02676 <span class="vhdlkeyword">if</span> (!<a class="code" href="classalu.html#a07af2646e5b543c5be95dddb22fd4ea6">div_diff</a>[<span class="vhdllogic">32</span>]) <span class="vhdlkeyword">begin</span>
|
<a name="l02676"></a>02676 <span class="vhdlchar">muls</span>.<span class="vhdlchar">lpm_widthb</span> = <span class="vhdllogic">17</span>,
|
<a name="l02677"></a>02677 <span class="keyword">// Difference is positive : shift a one</span>
|
<a name="l02677"></a>02677 <span class="vhdlchar">muls</span>.<span class="vhdlchar">lpm_widthp</span> = <span class="vhdllogic">34</span>,
|
<a name="l02678"></a>02678 <a class="code" href="classalu.html#a0c2a64b2f5dd32b2159ca0f29de360aa">dividend</a> <= <a class="code" href="classalu.html#a07af2646e5b543c5be95dddb22fd4ea6">div_diff</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
<a name="l02678"></a>02678 <span class="vhdlchar">muls</span>.<span class="vhdlchar">lpm_representation</span> = <span class="keyword">"SIGNED"</span>,
|
<a name="l02679"></a>02679 <a class="code" href="classalu.html#ab225284f49794091a5a28e73b8b13e14">quotient</a> <= {<a class="code" href="classalu.html#ab225284f49794091a5a28e73b8b13e14">quotient</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>], <span class="vhdllogic">1'b1</span>};
|
<a name="l02679"></a>02679 <span class="vhdlchar">muls</span>.<span class="vhdlchar">lpm_pipeline</span> = <span class="vhdllogic">1</span>;
|
<a name="l02680"></a>02680 <span class="vhdlkeyword">end</span>
|
<a name="l02680"></a>02680
|
<a name="l02681"></a>02681 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
<a name="l02681"></a>02681 <span class="keyword">// multiplication ready in one cycle, division ready when div_count in waiting or idle state</span>
|
<a name="l02682"></a>02682 <span class="keyword">// Difference is negative : shift a zero</span>
|
<a name="l02682"></a>02682 <span class="vhdlkeyword">assign</span> <a class="code" href="classalu.html#ab6a8e15c686ee360ddad15cd4d995ea9">alu_mult_div_ready</a> = (<a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a> == <span class="vhdllogic">5'd1</span> || <a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a> == <span class="vhdllogic">5'd0</span>);
|
<a name="l02683"></a>02683 <a class="code" href="classalu.html#ab225284f49794091a5a28e73b8b13e14">quotient</a> <= {<a class="code" href="classalu.html#ab225284f49794091a5a28e73b8b13e14">quotient</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>], <span class="vhdllogic">1'b0</span>};
|
<a name="l02683"></a>02683
|
<a name="l02684"></a>02684 <span class="vhdlkeyword">end</span>
|
<a name="l02684"></a>02684 <span class="keyword">//****************************************************** Altera-specific multiplication and division modules END</span>
|
<a name="l02685"></a>02685 <span class="keyword">// Shift right divider</span>
|
<a name="l02685"></a>02685
|
<a name="l02686"></a>02686 <a class="code" href="classalu.html#a9c2364593889150d7f5679fc33b0f1fa">divider</a> <= {<span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#a9c2364593889150d7f5679fc33b0f1fa">divider</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">1</span>]};
|
<a name="l02686"></a>02686 <span class="keyword">// ALU internal defines</span>
|
<a name="l02687"></a>02687 <span class="keyword">// Count one bit</span>
|
<a name="l02687"></a><a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">02687</a> <span class="preprocessor">`define</span> <a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">Sm</a> ((<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) ? operand2[<span class="vhdllogic">7</span>] : (<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) ? operand2[<span class="vhdllogic">15</span>] : <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">31</span>])
|
<a name="l02688"></a>02688 <a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a> <= <a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a> - <span class="vhdllogic">5'd1</span>;
|
<a name="l02688"></a>02688
|
<a name="l02689"></a>02689 <span class="vhdlkeyword">end</span>
|
<a name="l02689"></a><a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">02689</a> <span class="preprocessor">`define</span> <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">Dm</a> ((<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) ? operand1[<span class="vhdllogic">7</span>] : (<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) ? operand1[<span class="vhdllogic">15</span>] : <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>])
|
<a name="l02690"></a>02690 <span class="keyword">// result read</span>
|
<a name="l02690"></a>02690
|
<a name="l02691"></a>02691 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#acd09435ce38c12172a01a2b3725577dc">alu_control</a> == <a class="code" href="ao68000_8v.html#aed07d190bb88f0cce7768028698020f9">`ALU_MULS_MULU_DIVS_DIVU</a><span class="vhdlchar"></span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1000</span> && <a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a> == <span class="vhdllogic">5'd1</span>) <span class="vhdlkeyword">begin</span>
|
<a name="l02691"></a><a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">02691</a> <span class="preprocessor">`define</span> <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">Rm</a> ((<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) ? result[<span class="vhdllogic">7</span>] : (<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) ? result[<span class="vhdllogic">15</span>] : <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>])
|
<a name="l02692"></a>02692 <span class="keyword">// goto idle</span>
|
<a name="l02692"></a>02692
|
<a name="l02693"></a>02693 <a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a> <= <a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a> - <span class="vhdllogic">5'd1</span>;
|
<a name="l02693"></a><a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">02693</a> <span class="preprocessor">`define</span> <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">Z</a> ((<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) ? (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">8'b0</span>) : (<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) ? (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0</span>) : (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">32'b0</span>))
|
<a name="l02694"></a>02694 <span class="vhdlkeyword">end</span>
|
<a name="l02694"></a>02694
|
<a name="l02695"></a>02695 <span class="vhdlkeyword">end</span>
|
<a name="l02695"></a>02695 <span class="keyword">// ALU operations</span>
|
<a name="l02696"></a>02696
|
<a name="l02696"></a>02696
|
<a name="l02697"></a>02697
|
<a name="l02697"></a><a class="code" href="classalu.html#ab6caa4c83db93eebe29133a1ce68435e">02697</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#ab6caa4c83db93eebe29133a1ce68435e">interrupt_mask_copy</a>;
|
<a name="l02698"></a>02698
|
<a name="l02698"></a><a class="code" href="classalu.html#afbfdb3d9663bb0dbde8f5ad7af046b27">02698</a> <span class="vhdlkeyword">reg</span> <a class="code" href="classalu.html#afbfdb3d9663bb0dbde8f5ad7af046b27">was_interrupt</a>;
|
<a name="l02699"></a>02699 <span class="keyword">/*OPTIM</span>
|
<a name="l02699"></a>02699
|
<a name="l02700"></a>02700 <span class="keyword"></span>
|
<a name="l02700"></a><a class="code" href="classalu.html#a04b10dc82e8a06c3856bfd16a7e18d06">02700</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classalu.html#aaa60d149641cba8468ad7791eb5999ab">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classalu.html#a5e83fb99cb897f45ca128fa1594c5967">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l02701"></a>02701 <span class="keyword">wire [31:0] divu_quotient;</span>
|
<a name="l02701"></a>02701 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a5e83fb99cb897f45ca128fa1594c5967">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
<a name="l02702"></a>02702 <span class="keyword">wire [15:0] divu_remainder;</span>
|
<a name="l02702"></a>02702 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a> <= { <span class="vhdllogic">1'b0</span>, <span class="vhdllogic">1'b0</span>, <span class="vhdllogic">1'b1</span>, <span class="vhdllogic">2'b0</span>, <span class="vhdllogic">3'b111</span>, <span class="vhdllogic">8'b0</span> };
|
<a name="l02703"></a>02703 <span class="keyword">wire [31:0] divs_quotient;</span>
|
<a name="l02703"></a>02703 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> <= <span class="vhdllogic">32'd0</span>;
|
<a name="l02704"></a>02704 <span class="keyword">wire [15:0] divs_remainder;</span>
|
<a name="l02704"></a>02704 <a class="code" href="classalu.html#a41770492859599997a003e2681e7d955">alu_signal</a> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l02705"></a>02705 <span class="keyword"></span>
|
<a name="l02705"></a>02705 <a class="code" href="classalu.html#ab6caa4c83db93eebe29133a1ce68435e">interrupt_mask_copy</a> <= <span class="vhdllogic">3'b0</span>;
|
<a name="l02706"></a>02706 <span class="keyword">// DIVU: 32-bit operand1 unsigned / 16-bit operand2 unsigned = {16-bit remainer unsigned, 16-bit quotient unsigned}</span>
|
<a name="l02706"></a>02706 <a class="code" href="classalu.html#afbfdb3d9663bb0dbde8f5ad7af046b27">was_interrupt</a> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l02707"></a>02707 <span class="keyword">// DIVU: division by 0: trap, overflow when quotient > 16-bit signed integer, operands not affected</span>
|
<a name="l02707"></a>02707 <span class="vhdlkeyword">end</span>
|
<a name="l02708"></a>02708 <span class="keyword">lpm_divide divu_inst(</span>
|
<a name="l02708"></a>02708 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
<a name="l02709"></a>02709 <span class="keyword"> .clock(clock),</span>
|
<a name="l02709"></a>02709 <span class="vhdlkeyword">case</span>(<a class="code" href="classalu.html#acd09435ce38c12172a01a2b3725577dc">alu_control</a>)
|
<a name="l02710"></a>02710 <span class="keyword"> .numer(operand1[31:0]),</span>
|
<a name="l02710"></a>02710 <a class="code" href="ao68000_8v.html#a687e6310453b4cedb64aa6e66b058c18">`ALU_SR_SET_INTERRUPT</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
<a name="l02711"></a>02711 <span class="keyword"> .denom(operand2[15:0]),</span>
|
<a name="l02711"></a>02711 <a class="code" href="classalu.html#ab6caa4c83db93eebe29133a1ce68435e">interrupt_mask_copy</a> <= <a class="code" href="classalu.html#aaec5e2b3f347a2651f6456b7d0dafe16">interrupt_mask</a>[<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>];
|
<a name="l02712"></a>02712 <span class="keyword"> .quotient(divu_quotient),</span>
|
<a name="l02712"></a>02712 <a class="code" href="classalu.html#afbfdb3d9663bb0dbde8f5ad7af046b27">was_interrupt</a> <= <span class="vhdllogic">1'b1</span>;
|
<a name="l02713"></a>02713 <span class="keyword"> .remain(divu_remainder)</span>
|
<a name="l02713"></a>02713 <span class="vhdlkeyword">end</span>
|
<a name="l02714"></a>02714 <span class="keyword">);</span>
|
<a name="l02714"></a>02714
|
<a name="l02715"></a>02715 <span class="keyword"><span class="vhdlkeyword">defparam</span></span>
|
<a name="l02715"></a>02715 <a class="code" href="ao68000_8v.html#ac9fc44b8d3bbcd6c742f1ba074fc668d">`ALU_SR_SET_TRAP</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
<a name="l02716"></a>02716 <span class="keyword"> divu_inst.lpm_widthn = 32,</span>
|
<a name="l02716"></a>02716 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#afbfdb3d9663bb0dbde8f5ad7af046b27">was_interrupt</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
<a name="l02717"></a>02717 <span class="keyword"> divu_inst.lpm_widthd = 16,</span>
|
<a name="l02717"></a>02717 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a> <= { <span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">14</span>], <span class="vhdllogic">1'b1</span>, <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">12</span>:<span class="vhdllogic">11</span>], <a class="code" href="classalu.html#ab6caa4c83db93eebe29133a1ce68435e">interrupt_mask_copy</a>[<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>], <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] };
|
<a name="l02718"></a>02718 <span class="keyword"> divu_inst.lpm_nrepresentation = "UNSIGNED",</span>
|
<a name="l02718"></a>02718 <span class="vhdlkeyword">end</span>
|
<a name="l02719"></a>02719 <span class="keyword"> divu_inst.lpm_drepresentation = "UNSIGNED",</span>
|
<a name="l02719"></a>02719 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
<a name="l02720"></a>02720 <span class="keyword"> divu_inst.lpm_hint = "LPM_REMAINDERPOSITIVE=TRUE",</span>
|
<a name="l02720"></a>02720 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a> <= { <span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">14</span>], <span class="vhdllogic">1'b1</span>, <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">12</span>:<span class="vhdllogic">0</span>] };
|
<a name="l02721"></a>02721 <span class="keyword"> divu_inst.lpm_pipeline = 30;</span>
|
<a name="l02721"></a>02721 <span class="vhdlkeyword">end</span>
|
<a name="l02722"></a>02722 <span class="keyword"></span>
|
<a name="l02722"></a>02722 <a class="code" href="classalu.html#afbfdb3d9663bb0dbde8f5ad7af046b27">was_interrupt</a> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l02723"></a>02723 <span class="keyword">// DIVS: 32-bit operand1 signed / 16-bit operand2 signed = {16-bit remainer signed = sign of dividend, 16-bit quotient signed}</span>
|
<a name="l02723"></a>02723 <span class="vhdlkeyword">end</span>
|
<a name="l02724"></a>02724 <span class="keyword">// DIVS: division by 0: trap, overflow when quotient > 16-bit signed integer, operands not affected</span>
|
<a name="l02724"></a>02724
|
<a name="l02725"></a>02725 <span class="keyword">lpm_divide divs_inst(</span>
|
<a name="l02725"></a>02725 <a class="code" href="ao68000_8v.html#a59147ff996e0ba496f1f06d7a06decae">`ALU_MOVEP_M2R_1</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
<a name="l02726"></a>02726 <span class="keyword"> .clock(clock),</span>
|
<a name="l02726"></a>02726 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">6</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">24</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>];
|
<a name="l02727"></a>02727 <span class="keyword"> .numer(operand1[31:0]),</span>
|
<a name="l02727"></a>02727 <span class="vhdlkeyword">else</span> <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">8</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>];
|
<a name="l02728"></a>02728 <span class="keyword"> .denom(operand2[15:0]),</span>
|
<a name="l02728"></a>02728 <span class="keyword">//CCR: no change</span>
|
<a name="l02729"></a>02729 <span class="keyword"> .quotient(divs_quotient),</span>
|
<a name="l02729"></a>02729 <span class="vhdlkeyword">end</span>
|
<a name="l02730"></a>02730 <span class="keyword"> .remain(divs_remainder)</span>
|
<a name="l02730"></a>02730 <a class="code" href="ao68000_8v.html#a3b1155f3496b0fc984e5418e09586bf5">`ALU_MOVEP_M2R_2</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
<a name="l02731"></a>02731 <span class="keyword">);</span>
|
<a name="l02731"></a>02731 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">6</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">23</span>:<span class="vhdllogic">16</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>];
|
<a name="l02732"></a>02732 <span class="keyword"><span class="vhdlkeyword">defparam</span></span>
|
<a name="l02732"></a>02732 <span class="vhdlkeyword">else</span> <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>];
|
<a name="l02733"></a>02733 <span class="keyword"> divs_inst.lpm_widthn = 32,</span>
|
<a name="l02733"></a>02733 <span class="keyword">//CCR: no change</span>
|
<a name="l02734"></a>02734 <span class="keyword"> divs_inst.lpm_widthd = 16,</span>
|
<a name="l02734"></a>02734 <span class="vhdlkeyword">end</span>
|
<a name="l02735"></a>02735 <span class="keyword"> divs_inst.lpm_nrepresentation = "SIGNED",</span>
|
<a name="l02735"></a>02735 <a class="code" href="ao68000_8v.html#a5458c8548afc8f7517bdc582c9946b2f">`ALU_MOVEP_M2R_3</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
<a name="l02736"></a>02736 <span class="keyword"> divs_inst.lpm_drepresentation = "SIGNED",</span>
|
<a name="l02736"></a>02736 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">6</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">8</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>];
|
<a name="l02737"></a>02737 <span class="keyword"> divs_inst.lpm_hint = "LPM_REMAINDERPOSITIVE=FALSE",</span>
|
<a name="l02737"></a>02737 <span class="keyword">//CCR: no change</span>
|
<a name="l02738"></a>02738 <span class="keyword"> divs_inst.lpm_pipeline = 30;</span>
|
<a name="l02738"></a>02738 <span class="vhdlkeyword">end</span>
|
<a name="l02739"></a>02739 <span class="keyword">*/</span>
|
<a name="l02739"></a>02739 <a class="code" href="ao68000_8v.html#a8ec0074ca9c5cfec15aa93b92353e09b">`ALU_MOVEP_M2R_4</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
<a name="l02740"></a>02740
|
<a name="l02740"></a>02740 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">6</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>];
|
<a name="l02741"></a>02741 <span class="keyword">// MULS/MULU: 16-bit operand1[15:0] signed/unsigned * operand2[15:0] signed/unsigned = 32-bit result signed/unsigned</span>
|
<a name="l02741"></a>02741 <span class="keyword">//CCR: no change</span>
|
<a name="l02742"></a>02742 <span class="keyword">// Optimization by Frederic Requin</span>
|
<a name="l02742"></a>02742 <span class="vhdlkeyword">end</span>
|
<a name="l02743"></a><a class="code" href="classalu.html#aff5530027f36561324e060e703004b6b">02743</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">33</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#aff5530027f36561324e060e703004b6b">mult_result</a>;
|
<a name="l02743"></a>02743
|
<a name="l02744"></a>02744
|
<a name="l02744"></a>02744
|
<a name="l02745"></a><a class="code" href="classalu.html#a6447478386a93e0306b7cb09937c23c3">02745</a> <a class="code" href="classalu.html#a6447478386a93e0306b7cb09937c23c3">lpm_mult</a> <span class="vhdlchar">muls</span>(
|
<a name="l02745"></a>02745 <a class="code" href="ao68000_8v.html#aab7548aba43c6c12259a2a154ce2982b">`ALU_MOVEP_R2M_1</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
<a name="l02746"></a>02746 .<a class="code" href="classalu.html#aaa60d149641cba8468ad7791eb5999ab">clock</a> (<a class="code" href="classalu.html#aaa60d149641cba8468ad7791eb5999ab">clock</a>),
|
<a name="l02746"></a>02746 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">6</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">24</span>];
|
<a name="l02747"></a>02747 .<span class="vhdlchar">dataa</span> ({<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>] & <a class="code" href="classalu.html#abbf525422eca0279b697f742b90237e0">mult_div_sign</a>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>]}),
|
<a name="l02747"></a>02747 <span class="vhdlkeyword">else</span> <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">8</span>];
|
<a name="l02748"></a>02748 .<span class="vhdlchar">datab</span> ({<a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">15</span>] & <a class="code" href="classalu.html#abbf525422eca0279b697f742b90237e0">mult_div_sign</a>, <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>]}),
|
<a name="l02748"></a>02748 <span class="keyword">// CCR: no change</span>
|
<a name="l02749"></a>02749 .<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> (<a class="code" href="classalu.html#aff5530027f36561324e060e703004b6b">mult_result</a>)
|
<a name="l02749"></a>02749 <span class="vhdlkeyword">end</span>
|
<a name="l02750"></a>02750 );
|
<a name="l02750"></a>02750 <a class="code" href="ao68000_8v.html#a9918f4663f481092da549f3cb008721d">`ALU_MOVEP_R2M_2</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
<a name="l02751"></a>02751 <span class="vhdlkeyword">defparam</span>
|
<a name="l02751"></a>02751 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">6</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">23</span>:<span class="vhdllogic">16</span>];
|
<a name="l02752"></a>02752 <span class="vhdlchar">muls</span>.<span class="vhdlchar">lpm_widtha</span> = <span class="vhdllogic">17</span>,
|
<a name="l02752"></a>02752 <span class="vhdlkeyword">else</span> <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>];
|
<a name="l02753"></a>02753 <span class="vhdlchar">muls</span>.<span class="vhdlchar">lpm_widthb</span> = <span class="vhdllogic">17</span>,
|
<a name="l02753"></a>02753 <span class="keyword">// CCR: no change</span>
|
<a name="l02754"></a>02754 <span class="vhdlchar">muls</span>.<span class="vhdlchar">lpm_widthp</span> = <span class="vhdllogic">34</span>,
|
<a name="l02754"></a>02754 <span class="vhdlkeyword">end</span>
|
<a name="l02755"></a>02755 <span class="vhdlchar">muls</span>.<span class="vhdlchar">lpm_representation</span> = <span class="keyword">"SIGNED"</span>,
|
<a name="l02755"></a>02755 <a class="code" href="ao68000_8v.html#aee5fc91f58c97ffa4d252e127c9e4226">`ALU_MOVEP_R2M_3</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
<a name="l02756"></a>02756 <span class="vhdlchar">muls</span>.<span class="vhdlchar">lpm_pipeline</span> = <span class="vhdllogic">1</span>;
|
<a name="l02756"></a>02756 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">8</span>];
|
<a name="l02757"></a>02757
|
<a name="l02757"></a>02757 <span class="keyword">// CCR: no change</span>
|
<a name="l02758"></a>02758 <span class="keyword">/*OPTIM - count LE & MHz in comment in switch</span>
|
<a name="l02758"></a>02758 <span class="vhdlkeyword">end</span>
|
<a name="l02759"></a>02759 <span class="keyword">// MULU: 16-bit operand1[15:0] unsigned * 16-bit operand2 unsigned = 32-bit result unsigned</span>
|
<a name="l02759"></a>02759 <a class="code" href="ao68000_8v.html#a0bc85184fda7b9fcbf00afa29be91d42">`ALU_MOVEP_R2M_4</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
<a name="l02760"></a>02760 <span class="keyword">lpm_mult mulu_inst(</span>
|
<a name="l02760"></a>02760 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>];
|
<a name="l02761"></a>02761 <span class="keyword"> .clock(clock),</span>
|
<a name="l02761"></a>02761 <span class="keyword">// CCR: no change</span>
|
<a name="l02762"></a>02762 <span class="keyword"> .dataa(operand1[15:0]),</span>
|
<a name="l02762"></a>02762 <span class="vhdlkeyword">end</span>
|
<a name="l02763"></a>02763 <span class="keyword"> .datab(operand2[15:0]),</span>
|
<a name="l02763"></a>02763
|
<a name="l02764"></a>02764 <span class="keyword"> .result(mulu_result)</span>
|
<a name="l02764"></a>02764
|
<a name="l02765"></a>02765 <span class="keyword">);</span>
|
<a name="l02765"></a>02765
|
<a name="l02766"></a>02766 <span class="keyword"><span class="vhdlkeyword">defparam</span></span>
|
<a name="l02766"></a>02766 <a class="code" href="ao68000_8v.html#a6a119b7268e4e0a78e0307ba0c693ccb">`ALU_SIGN_EXTEND</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
<a name="l02767"></a>02767 <span class="keyword"> mulu_inst.lpm_widtha = 16,</span>
|
<a name="l02767"></a>02767 <span class="keyword">// move operand1 with sign-extension to result</span>
|
<a name="l02768"></a>02768 <span class="keyword"> mulu_inst.lpm_widthb = 16,</span>
|
<a name="l02768"></a>02768 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
<a name="l02769"></a>02769 <span class="keyword"> mulu_inst.lpm_widthp = 32,</span>
|
<a name="l02769"></a>02769 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> <= { {<span class="vhdllogic">16</span>{<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>]}}, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] };
|
<a name="l02770"></a>02770 <span class="keyword"> mulu_inst.lpm_representation = "UNSIGNED",</span>
|
<a name="l02770"></a>02770 <span class="vhdlkeyword">end</span>
|
<a name="l02771"></a>02771 <span class="keyword"> mulu_inst.lpm_pipeline = 18;</span>
|
<a name="l02771"></a>02771 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
<a name="l02772"></a>02772 <span class="keyword"></span>
|
<a name="l02772"></a>02772 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>;
|
<a name="l02773"></a>02773 <span class="keyword">// MULS: 16-bit operand1[15:0] signed * 16-bit operand2 signed = 32-bit result signed</span>
|
<a name="l02773"></a>02773 <span class="vhdlkeyword">end</span>
|
<a name="l02774"></a>02774 <span class="keyword">lpm_mult muls_inst(</span>
|
<a name="l02774"></a>02774 <span class="keyword">// CCR: no change</span>
|
<a name="l02775"></a>02775 <span class="keyword"> .clock(clock),</span>
|
<a name="l02775"></a>02775 <span class="vhdlkeyword">end</span>
|
<a name="l02776"></a>02776 <span class="keyword"> .dataa(operand1[15:0]),</span>
|
<a name="l02776"></a>02776
|
<a name="l02777"></a>02777 <span class="keyword"> .datab(operand2[15:0]),</span>
|
<a name="l02777"></a>02777 <a class="code" href="ao68000_8v.html#ae497ab0b3e0550245c333bdb426d4236">`ALU_ARITHMETIC_LOGIC</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
<a name="l02778"></a>02778 <span class="keyword"> .result(muls_result)</span>
|
<a name="l02778"></a>02778
|
<a name="l02779"></a>02779 <span class="keyword">);</span>
|
<a name="l02779"></a>02779 <span class="keyword">// OR,OR to mem,OR to Dn</span>
|
<a name="l02780"></a>02780 <span class="keyword"><span class="vhdlkeyword">defparam</span></span>
|
<a name="l02780"></a>02780 <span class="vhdlkeyword">if</span>( (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">3'b000</span>) ||
|
<a name="l02781"></a>02781 <span class="keyword"> muls_inst.lpm_widtha = 16,</span>
|
<a name="l02781"></a>02781 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1000</span>)
|
<a name="l02782"></a>02782 <span class="keyword"> muls_inst.lpm_widthb = 16,</span>
|
<a name="l02782"></a>02782 ) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] | <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
<a name="l02783"></a>02783 <span class="keyword"> muls_inst.lpm_widthp = 32,</span>
|
<a name="l02783"></a>02783 <span class="keyword">// AND,AND to mem,AND to Dn</span>
|
<a name="l02784"></a>02784 <span class="keyword"> muls_inst.lpm_representation = "SIGNED",</span>
|
<a name="l02784"></a>02784 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">3'b001</span>) ||
|
<a name="l02785"></a>02785 <span class="keyword"> muls_inst.lpm_pipeline = 18;</span>
|
<a name="l02785"></a>02785 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1100</span>)
|
<a name="l02786"></a>02786 <span class="keyword">*/</span>
|
<a name="l02786"></a>02786 ) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] & <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
<a name="l02787"></a>02787
|
<a name="l02787"></a>02787 <span class="keyword">// EORI,EOR</span>
|
<a name="l02788"></a>02788 <span class="keyword">// multiplication ready in one cycle, division ready when div_count in waiting or idle state</span>
|
<a name="l02788"></a>02788 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">3'b101</span>) ||
|
<a name="l02789"></a>02789 <span class="vhdlkeyword">assign</span> <a class="code" href="classalu.html#ab6a8e15c686ee360ddad15cd4d995ea9">alu_mult_div_ready</a> = (<a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a> == <span class="vhdllogic">5'd1</span> || <a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a> == <span class="vhdllogic">5'd0</span>);
|
<a name="l02789"></a>02789 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1011</span> && (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b100</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b101</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b110</span>) && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span>)
|
<a name="l02790"></a>02790
|
<a name="l02790"></a>02790 ) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] ^ <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
<a name="l02791"></a>02791 <span class="keyword">//****************************************************** Altera-specific multiplication and division modules END</span>
|
<a name="l02791"></a>02791 <span class="keyword">// ADD,ADD to mem,ADD to Dn,ADDQ</span>
|
<a name="l02792"></a>02792
|
<a name="l02792"></a>02792 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">3'b011</span>) ||
|
<a name="l02793"></a>02793 <span class="keyword">// ALU internal defines</span>
|
<a name="l02793"></a>02793 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1101</span>) ||
|
<a name="l02794"></a><a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">02794</a> <span class="preprocessor">`define</span> <a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">Sm</a> ((<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) ? operand2[<span class="vhdllogic">7</span>] : (<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) ? operand2[<span class="vhdllogic">15</span>] : <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">31</span>])
|
<a name="l02794"></a>02794 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0101</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b0</span>)
|
<a name="l02795"></a>02795
|
<a name="l02795"></a>02795 ) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] + <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
<a name="l02796"></a><a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">02796</a> <span class="preprocessor">`define</span> <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">Dm</a> ((<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) ? operand1[<span class="vhdllogic">7</span>] : (<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) ? operand1[<span class="vhdllogic">15</span>] : <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>])
|
<a name="l02796"></a>02796 <span class="keyword">// SUBI,CMPI,CMPM,SUB to mem,SUB to Dn,CMP,SUBQ</span>
|
<a name="l02797"></a>02797
|
<a name="l02797"></a>02797 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">3'b010</span>) ||
|
<a name="l02798"></a><a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">02798</a> <span class="preprocessor">`define</span> <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">Rm</a> ((<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) ? result[<span class="vhdllogic">7</span>] : (<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) ? result[<span class="vhdllogic">15</span>] : <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>])
|
<a name="l02798"></a>02798 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">3'b110</span>) ||
|
<a name="l02799"></a>02799
|
<a name="l02799"></a>02799 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1011</span> && (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b100</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b101</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b110</span>) && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b001</span>) ||
|
<a name="l02800"></a><a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">02800</a> <span class="preprocessor">`define</span> <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">Z</a> ((<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) ? (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">8'b0</span>) : (<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) ? (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0</span>) : (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">32'b0</span>))
|
<a name="l02800"></a>02800 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1001</span>) ||
|
<a name="l02801"></a>02801
|
<a name="l02801"></a>02801 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1011</span> && (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b000</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b001</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b010</span>)) ||
|
<a name="l02802"></a>02802 <span class="keyword">// ALU operations</span>
|
<a name="l02802"></a>02802 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0101</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b1</span>)
|
<a name="l02803"></a>02803
|
<a name="l02803"></a>02803 ) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] - <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
<a name="l02804"></a><a class="code" href="classalu.html#ab6caa4c83db93eebe29133a1ce68435e">02804</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#ab6caa4c83db93eebe29133a1ce68435e">interrupt_mask_copy</a>;
|
<a name="l02804"></a>02804
|
<a name="l02805"></a><a class="code" href="classalu.html#afbfdb3d9663bb0dbde8f5ad7af046b27">02805</a> <span class="vhdlkeyword">reg</span> <a class="code" href="classalu.html#afbfdb3d9663bb0dbde8f5ad7af046b27">was_interrupt</a>;
|
<a name="l02805"></a>02805 <span class="keyword">// Z</span>
|
<a name="l02806"></a>02806
|
<a name="l02806"></a>02806 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">`Z</a><span class="vhdlchar"></span>;
|
<a name="l02807"></a><a class="code" href="classalu.html#a04b10dc82e8a06c3856bfd16a7e18d06">02807</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classalu.html#aaa60d149641cba8468ad7791eb5999ab">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classalu.html#a5e83fb99cb897f45ca128fa1594c5967">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l02807"></a>02807 <span class="keyword">// N</span>
|
<a name="l02808"></a>02808 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a5e83fb99cb897f45ca128fa1594c5967">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
<a name="l02808"></a>02808 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
<a name="l02809"></a>02809 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a> <= { <span class="vhdllogic">1'b0</span>, <span class="vhdllogic">1'b0</span>, <span class="vhdllogic">1'b1</span>, <span class="vhdllogic">2'b0</span>, <span class="vhdllogic">3'b111</span>, <span class="vhdllogic">8'b0</span> };
|
<a name="l02809"></a>02809
|
<a name="l02810"></a>02810 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> <= <span class="vhdllogic">32'd0</span>;
|
<a name="l02810"></a>02810 <span class="keyword">// CMPI,CMPM,CMP</span>
|
<a name="l02811"></a>02811 <a class="code" href="classalu.html#a41770492859599997a003e2681e7d955">alu_signal</a> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l02811"></a>02811 <span class="vhdlkeyword">if</span>( (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">3'b110</span>) ||
|
<a name="l02812"></a>02812 <a class="code" href="classalu.html#ab6caa4c83db93eebe29133a1ce68435e">interrupt_mask_copy</a> <= <span class="vhdllogic">3'b0</span>;
|
<a name="l02812"></a>02812 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1011</span> && (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b100</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b101</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b110</span>) && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b001</span>) ||
|
<a name="l02813"></a>02813 <a class="code" href="classalu.html#afbfdb3d9663bb0dbde8f5ad7af046b27">was_interrupt</a> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l02813"></a>02813 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1011</span> && (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b000</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b001</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b010</span>))
|
<a name="l02814"></a>02814 <span class="vhdlkeyword">end</span>
|
<a name="l02814"></a>02814 ) <span class="vhdlkeyword">begin</span>
|
<a name="l02815"></a>02815 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
<a name="l02815"></a>02815 <span class="keyword">// C,V</span>
|
<a name="l02816"></a>02816 <span class="vhdlkeyword">case</span>(<a class="code" href="classalu.html#acd09435ce38c12172a01a2b3725577dc">alu_control</a>)
|
<a name="l02816"></a>02816 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
<a name="l02817"></a>02817 <a class="code" href="ao68000_8v.html#a687e6310453b4cedb64aa6e66b058c18">`ALU_SR_SET_INTERRUPT</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
<a name="l02817"></a>02817 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= (~<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
<a name="l02818"></a>02818 <a class="code" href="classalu.html#ab6caa4c83db93eebe29133a1ce68435e">interrupt_mask_copy</a> <= <a class="code" href="classalu.html#aaec5e2b3f347a2651f6456b7d0dafe16">interrupt_mask</a>[<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>];
|
<a name="l02818"></a>02818 <span class="keyword">// X not affected</span>
|
<a name="l02819"></a>02819 <a class="code" href="classalu.html#afbfdb3d9663bb0dbde8f5ad7af046b27">was_interrupt</a> <= <span class="vhdllogic">1'b1</span>;
|
<a name="l02819"></a>02819 <span class="vhdlkeyword">end</span>
|
<a name="l02820"></a>02820 <span class="vhdlkeyword">end</span>
|
<a name="l02820"></a>02820 <span class="keyword">// ADDI,ADD to mem,ADD to Dn,ADDQ</span>
|
<a name="l02821"></a>02821
|
<a name="l02821"></a>02821 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">3'b011</span>) ||
|
<a name="l02822"></a>02822 <a class="code" href="ao68000_8v.html#ac9fc44b8d3bbcd6c742f1ba074fc668d">`ALU_SR_SET_TRAP</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
<a name="l02822"></a>02822 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1101</span>) ||
|
<a name="l02823"></a>02823 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#afbfdb3d9663bb0dbde8f5ad7af046b27">was_interrupt</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
<a name="l02823"></a>02823 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0101</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b0</span>)
|
<a name="l02824"></a>02824 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a> <= { <span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">14</span>], <span class="vhdllogic">1'b1</span>, <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">12</span>:<span class="vhdllogic">11</span>], <a class="code" href="classalu.html#ab6caa4c83db93eebe29133a1ce68435e">interrupt_mask_copy</a>[<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>], <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] };
|
<a name="l02824"></a>02824 ) <span class="vhdlkeyword">begin</span>
|
<a name="l02825"></a>02825 <span class="vhdlkeyword">end</span>
|
<a name="l02825"></a>02825 <span class="keyword">// C,X,V</span>
|
<a name="l02826"></a>02826 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
<a name="l02826"></a>02826 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
<a name="l02827"></a>02827 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a> <= { <span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">14</span>], <span class="vhdllogic">1'b1</span>, <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">12</span>:<span class="vhdllogic">0</span>] };
|
<a name="l02827"></a>02827 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>); <span class="keyword">//=ccr[0];</span>
|
<a name="l02828"></a>02828 <span class="vhdlkeyword">end</span>
|
<a name="l02828"></a>02828 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>) | (~<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
<a name="l02829"></a>02829 <a class="code" href="classalu.html#afbfdb3d9663bb0dbde8f5ad7af046b27">was_interrupt</a> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l02829"></a>02829 <span class="vhdlkeyword">end</span>
|
<a name="l02830"></a>02830 <span class="vhdlkeyword">end</span>
|
<a name="l02830"></a>02830 <span class="keyword">// SUBI,SUB to mem,SUB to Dn,SUBQ</span>
|
<a name="l02831"></a>02831
|
<a name="l02831"></a>02831 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">3'b010</span>) ||
|
<a name="l02832"></a>02832 <a class="code" href="ao68000_8v.html#a59147ff996e0ba496f1f06d7a06decae">`ALU_MOVEP_M2R_1</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
<a name="l02832"></a>02832 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1001</span>) ||
|
<a name="l02833"></a>02833 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">6</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">24</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>];
|
<a name="l02833"></a>02833 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0101</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b1</span>)
|
<a name="l02834"></a>02834 <span class="vhdlkeyword">else</span> <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">8</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>];
|
<a name="l02834"></a>02834 ) <span class="vhdlkeyword">begin</span>
|
<a name="l02835"></a>02835 <span class="keyword">//CCR: no change</span>
|
<a name="l02835"></a>02835 <span class="keyword">// C,X,V</span>
|
<a name="l02836"></a>02836 <span class="vhdlkeyword">end</span>
|
<a name="l02836"></a>02836 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
<a name="l02837"></a>02837 <a class="code" href="ao68000_8v.html#a3b1155f3496b0fc984e5418e09586bf5">`ALU_MOVEP_M2R_2</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
<a name="l02837"></a>02837 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>); <span class="keyword">//=ccr[0];</span>
|
<a name="l02838"></a>02838 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">6</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">23</span>:<span class="vhdllogic">16</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>];
|
<a name="l02838"></a>02838 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= (~<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
<a name="l02839"></a>02839 <span class="vhdlkeyword">else</span> <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>];
|
<a name="l02839"></a>02839 <span class="vhdlkeyword">end</span>
|
<a name="l02840"></a>02840 <span class="keyword">//CCR: no change</span>
|
<a name="l02840"></a>02840 <span class="keyword">// ANDI,EORI,ORI,EOR,OR to mem,AND to mem,OR to Dn,AND to Dn</span>
|
<a name="l02841"></a>02841 <span class="vhdlkeyword">end</span>
|
<a name="l02841"></a>02841 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
<a name="l02842"></a>02842 <a class="code" href="ao68000_8v.html#a5458c8548afc8f7517bdc582c9946b2f">`ALU_MOVEP_M2R_3</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
<a name="l02842"></a>02842 <span class="keyword">// C,V</span>
|
<a name="l02843"></a>02843 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">6</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">8</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>];
|
<a name="l02843"></a>02843 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <span class="vhdllogic">1'b0</span>;
|
<a name="l02844"></a>02844 <span class="keyword">//CCR: no change</span>
|
<a name="l02844"></a>02844 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>;
|
<a name="l02845"></a>02845 <span class="vhdlkeyword">end</span>
|
<a name="l02845"></a>02845 <span class="keyword">// X not affected</span>
|
<a name="l02846"></a>02846 <a class="code" href="ao68000_8v.html#a8ec0074ca9c5cfec15aa93b92353e09b">`ALU_MOVEP_M2R_4</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
<a name="l02846"></a>02846 <span class="vhdlkeyword">end</span>
|
<a name="l02847"></a>02847 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">6</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>];
|
<a name="l02847"></a>02847 <span class="vhdlkeyword">end</span>
|
<a name="l02848"></a>02848 <span class="keyword">//CCR: no change</span>
|
<a name="l02848"></a>02848
|
<a name="l02849"></a>02849 <span class="vhdlkeyword">end</span>
|
<a name="l02849"></a>02849 <a class="code" href="ao68000_8v.html#a3e54001e73374bd4f7cfda3de55bd944">`ALU_ABCD_SBCD_ADDX_SUBX</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span> <span class="keyword">// 259 LE</span>
|
<a name="l02850"></a>02850
|
<a name="l02850"></a>02850 <span class="keyword">// ABCD</span>
|
<a name="l02851"></a>02851
|
<a name="l02851"></a>02851 <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">14</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">3'b100</span> ) <span class="vhdlkeyword">begin</span>
|
<a name="l02852"></a>02852 <a class="code" href="ao68000_8v.html#aab7548aba43c6c12259a2a154ce2982b">`ALU_MOVEP_R2M_1</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
<a name="l02852"></a>02852 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] = {<span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>]} + {<span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>]} + {<span class="vhdllogic">4'b0</span>, <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>]};
|
<a name="l02853"></a>02853 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">6</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">24</span>];
|
<a name="l02853"></a>02853 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] = {<span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>]} + {<span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>]};
|
<a name="l02854"></a>02854 <span class="vhdlkeyword">else</span> <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">8</span>];
|
<a name="l02854"></a>02854
|
<a name="l02855"></a>02855 <span class="keyword">// CCR: no change</span>
|
<a name="l02855"></a>02855 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">23</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] + <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] + {<span class="vhdllogic">7'b0</span>, <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>]};
|
<a name="l02856"></a>02856 <span class="vhdlkeyword">end</span>
|
<a name="l02856"></a>02856
|
<a name="l02857"></a>02857 <a class="code" href="ao68000_8v.html#a9918f4663f481092da549f3cb008721d">`ALU_MOVEP_R2M_2</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
<a name="l02857"></a>02857 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] = (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] > <span class="vhdllogic">6'd9</span>) ? (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] + <span class="vhdllogic">6'd6</span>) : <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>];
|
<a name="l02858"></a>02858 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">6</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">23</span>:<span class="vhdllogic">16</span>];
|
<a name="l02858"></a>02858 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] = (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] > <span class="vhdllogic">6'h1F</span>) ? (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] + <span class="vhdllogic">6'd2</span>) :
|
<a name="l02859"></a>02859 <span class="vhdlkeyword">else</span> <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>];
|
<a name="l02859"></a>02859 (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] > <span class="vhdllogic">6'h0F</span>) ? (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] + <span class="vhdllogic">6'd1</span>) :
|
<a name="l02860"></a>02860 <span class="keyword">// CCR: no change</span>
|
<a name="l02860"></a>02860 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>];
|
<a name="l02861"></a>02861 <span class="vhdlkeyword">end</span>
|
<a name="l02861"></a>02861 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] = (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] > <span class="vhdllogic">6'd9</span>) ? (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] + <span class="vhdllogic">6'd6</span>) : <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>];
|
<a name="l02862"></a>02862 <a class="code" href="ao68000_8v.html#aee5fc91f58c97ffa4d252e127c9e4226">`ALU_MOVEP_R2M_3</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
<a name="l02862"></a>02862
|
<a name="l02863"></a>02863 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">8</span>];
|
<a name="l02863"></a>02863 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] = <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">17</span>:<span class="vhdllogic">14</span>];
|
<a name="l02864"></a>02864 <span class="keyword">// CCR: no change</span>
|
<a name="l02864"></a>02864 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>];
|
<a name="l02865"></a>02865 <span class="vhdlkeyword">end</span>
|
<a name="l02865"></a>02865
|
<a name="l02866"></a>02866 <a class="code" href="ao68000_8v.html#a0bc85184fda7b9fcbf00afa29be91d42">`ALU_MOVEP_R2M_4</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
<a name="l02866"></a>02866 <span class="keyword">// C</span>
|
<a name="l02867"></a>02867 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>];
|
<a name="l02867"></a>02867 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] > <span class="vhdllogic">6'd9</span>) ? <span class="vhdllogic">1'b1</span> : <span class="vhdllogic">1'b0</span>;
|
<a name="l02868"></a>02868 <span class="keyword">// CCR: no change</span>
|
<a name="l02868"></a>02868 <span class="keyword">// X = C</span>
|
<a name="l02869"></a>02869 <span class="vhdlkeyword">end</span>
|
<a name="l02869"></a>02869 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] > <span class="vhdllogic">6'd9</span>) ? <span class="vhdllogic">1'b1</span> : <span class="vhdllogic">1'b0</span>;
|
<a name="l02870"></a>02870
|
<a name="l02870"></a>02870
|
<a name="l02871"></a>02871
|
<a name="l02871"></a>02871 <span class="keyword">// V</span>
|
<a name="l02872"></a>02872
|
<a name="l02872"></a>02872 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">30</span>] == <span class="vhdllogic">1'b0</span> && <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>] == <span class="vhdllogic">1'b1</span>) ? <span class="vhdllogic">1'b1</span> : <span class="vhdllogic">1'b0</span>;
|
<a name="l02873"></a>02873 <a class="code" href="ao68000_8v.html#a6a119b7268e4e0a78e0307ba0c693ccb">`ALU_SIGN_EXTEND</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
<a name="l02873"></a>02873 <span class="vhdlkeyword">end</span>
|
<a name="l02874"></a>02874 <span class="keyword">// move operand1 with sign-extension to result</span>
|
<a name="l02874"></a>02874 <span class="keyword">// SBCD</span>
|
<a name="l02875"></a>02875 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
<a name="l02875"></a>02875 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">14</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">3'b000</span> ) <span class="vhdlkeyword">begin</span>
|
<a name="l02876"></a>02876 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> <= { {<span class="vhdllogic">16</span>{<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>]}}, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] };
|
<a name="l02876"></a>02876
|
<a name="l02877"></a>02877 <span class="vhdlkeyword">end</span>
|
<a name="l02877"></a>02877 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] = <span class="vhdllogic">6'd32</span> + {<span class="vhdllogic">2'b0</span>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>]} - {<span class="vhdllogic">2'b0</span>, <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>]} - {<span class="vhdllogic">5'b0</span>, <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>]};
|
<a name="l02878"></a>02878 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
<a name="l02878"></a>02878 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] = <span class="vhdllogic">6'd32</span> + {<span class="vhdllogic">2'b0</span>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>]} - {<span class="vhdllogic">2'b0</span>, <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>]};
|
<a name="l02879"></a>02879 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>;
|
<a name="l02879"></a>02879
|
<a name="l02880"></a>02880 <span class="vhdlkeyword">end</span>
|
<a name="l02880"></a>02880 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">23</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] - <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] - {<span class="vhdllogic">7'b0</span>, <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>]};
|
<a name="l02881"></a>02881 <span class="keyword">// CCR: no change</span>
|
<a name="l02881"></a>02881
|
<a name="l02882"></a>02882 <span class="vhdlkeyword">end</span>
|
<a name="l02882"></a>02882 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] = (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] < <span class="vhdllogic">6'd32</span>) ? (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] - <span class="vhdllogic">6'd6</span>) : <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>];
|
<a name="l02883"></a>02883
|
<a name="l02883"></a>02883 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] = (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] < <span class="vhdllogic">6'd16</span>) ? (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] - <span class="vhdllogic">6'd2</span>) :
|
<a name="l02884"></a>02884 <a class="code" href="ao68000_8v.html#ae497ab0b3e0550245c333bdb426d4236">`ALU_ARITHMETIC_LOGIC</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
<a name="l02884"></a>02884 (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] < <span class="vhdllogic">6'd32</span>) ? (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] - <span class="vhdllogic">6'd1</span>) :
|
<a name="l02885"></a>02885
|
<a name="l02885"></a>02885 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>];
|
<a name="l02886"></a>02886 <span class="keyword">// OR,OR to mem,OR to Dn</span>
|
<a name="l02886"></a>02886 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] = (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] < <span class="vhdllogic">6'd32</span> && <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>] == <span class="vhdllogic">1'b1</span>) ? (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] - <span class="vhdllogic">6'd6</span>) : <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>];
|
<a name="l02887"></a>02887 <span class="vhdlkeyword">if</span>( (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">3'b000</span>) ||
|
<a name="l02887"></a>02887
|
<a name="l02888"></a>02888 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1000</span>)
|
<a name="l02888"></a>02888 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] = <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">17</span>:<span class="vhdllogic">14</span>];
|
<a name="l02889"></a>02889 ) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] | <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
<a name="l02889"></a>02889 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>];
|
<a name="l02890"></a>02890 <span class="keyword">// AND,AND to mem,AND to Dn</span>
|
<a name="l02890"></a>02890
|
<a name="l02891"></a>02891 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">3'b001</span>) ||
|
<a name="l02891"></a>02891 <span class="keyword">// C</span>
|
<a name="l02892"></a>02892 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1100</span>)
|
<a name="l02892"></a>02892 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] < <span class="vhdllogic">6'd32</span>) ? <span class="vhdllogic">1'b1</span> : <span class="vhdllogic">1'b0</span>;
|
<a name="l02893"></a>02893 ) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] & <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
<a name="l02893"></a>02893 <span class="keyword">// X = C</span>
|
<a name="l02894"></a>02894 <span class="keyword">// EORI,EOR</span>
|
<a name="l02894"></a>02894 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] < <span class="vhdllogic">6'd32</span>) ? <span class="vhdllogic">1'b1</span> : <span class="vhdllogic">1'b0</span>;
|
<a name="l02895"></a>02895 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">3'b101</span>) ||
|
<a name="l02895"></a>02895
|
<a name="l02896"></a>02896 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1011</span> && (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b100</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b101</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b110</span>) && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span>)
|
<a name="l02896"></a>02896 <span class="keyword">// V</span>
|
<a name="l02897"></a>02897 ) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] ^ <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
<a name="l02897"></a>02897 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">30</span>] == <span class="vhdllogic">1'b1</span> && <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>] == <span class="vhdllogic">1'b0</span>) ? <span class="vhdllogic">1'b1</span> : <span class="vhdllogic">1'b0</span>;
|
<a name="l02898"></a>02898 <span class="keyword">// ADD,ADD to mem,ADD to Dn,ADDQ</span>
|
<a name="l02898"></a>02898 <span class="vhdlkeyword">end</span>
|
<a name="l02899"></a>02899 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">3'b011</span>) ||
|
<a name="l02899"></a>02899 <span class="keyword">// ADDX</span>
|
<a name="l02900"></a>02900 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1101</span>) ||
|
<a name="l02900"></a>02900 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">14</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">3'b101</span> ) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] + <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] + <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>];
|
<a name="l02901"></a>02901 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0101</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b0</span>)
|
<a name="l02901"></a>02901 <span class="keyword">// SUBX</span>
|
<a name="l02902"></a>02902 ) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] + <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
<a name="l02902"></a>02902 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">14</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">3'b001</span> ) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] - <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] - <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>];
|
<a name="l02903"></a>02903 <span class="keyword">// SUBI,CMPI,CMPM,SUB to mem,SUB to Dn,CMP,SUBQ</span>
|
<a name="l02903"></a>02903
|
<a name="l02904"></a>02904 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">3'b010</span>) ||
|
<a name="l02904"></a>02904 <span class="keyword">// Z</span>
|
<a name="l02905"></a>02905 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">3'b110</span>) ||
|
<a name="l02905"></a>02905 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] & <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">`Z</a><span class="vhdlchar"></span>;
|
<a name="l02906"></a>02906 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1011</span> && (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b100</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b101</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b110</span>) && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b001</span>) ||
|
<a name="l02906"></a>02906 <span class="keyword">// N</span>
|
<a name="l02907"></a>02907 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1001</span>) ||
|
<a name="l02907"></a>02907 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
<a name="l02908"></a>02908 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1011</span> && (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b000</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b001</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b010</span>)) ||
|
<a name="l02908"></a>02908
|
<a name="l02909"></a>02909 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0101</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b1</span>)
|
<a name="l02909"></a>02909 <span class="keyword">// ADDX</span>
|
<a name="l02910"></a>02910 ) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] - <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
<a name="l02910"></a>02910 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">14</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">3'b101</span> ) <span class="vhdlkeyword">begin</span>
|
<a name="l02911"></a>02911
|
<a name="l02911"></a>02911 <span class="keyword">// C,X,V</span>
|
<a name="l02912"></a>02912 <span class="keyword">// Z</span>
|
<a name="l02912"></a>02912 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
<a name="l02913"></a>02913 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">`Z</a><span class="vhdlchar"></span>;
|
<a name="l02913"></a>02913 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>); <span class="keyword">//=ccr[0];</span>
|
<a name="l02914"></a>02914 <span class="keyword">// N</span>
|
<a name="l02914"></a>02914 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>) | (~<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
<a name="l02915"></a>02915 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
<a name="l02915"></a>02915 <span class="vhdlkeyword">end</span>
|
<a name="l02916"></a>02916
|
<a name="l02916"></a>02916 <span class="keyword">// SUBX</span>
|
<a name="l02917"></a>02917 <span class="keyword">// CMPI,CMPM,CMP</span>
|
<a name="l02917"></a>02917 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">14</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">3'b001</span> ) <span class="vhdlkeyword">begin</span>
|
<a name="l02918"></a>02918 <span class="vhdlkeyword">if</span>( (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">3'b110</span>) ||
|
<a name="l02918"></a>02918 <span class="keyword">// C,X,V</span>
|
<a name="l02919"></a>02919 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1011</span> && (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b100</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b101</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b110</span>) && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b001</span>) ||
|
<a name="l02919"></a>02919 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
<a name="l02920"></a>02920 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1011</span> && (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b000</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b001</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b010</span>))
|
<a name="l02920"></a>02920 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>); <span class="keyword">//=ccr[0];</span>
|
<a name="l02921"></a>02921 ) <span class="vhdlkeyword">begin</span>
|
<a name="l02921"></a>02921 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= (~<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
<a name="l02922"></a>02922 <span class="keyword">// C,V</span>
|
<a name="l02922"></a>02922 <span class="vhdlkeyword">end</span>
|
<a name="l02923"></a>02923 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
<a name="l02923"></a>02923 <span class="vhdlkeyword">end</span>
|
<a name="l02924"></a>02924 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= (~<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
<a name="l02924"></a>02924
|
<a name="l02925"></a>02925 <span class="keyword">// X not affected</span>
|
<a name="l02925"></a>02925 <a class="code" href="ao68000_8v.html#ac444f659b2726fd335e839dfadabbfe3">`ALU_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR_prepare</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
<a name="l02926"></a>02926 <span class="vhdlkeyword">end</span>
|
<a name="l02926"></a>02926
|
<a name="l02927"></a>02927 <span class="keyword">// ADDI,ADD to mem,ADD to Dn,ADDQ</span>
|
<a name="l02927"></a>02927 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>];
|
<a name="l02928"></a>02928 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">3'b011</span>) ||
|
<a name="l02928"></a>02928 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>];
|
<a name="l02929"></a>02929 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1101</span>) ||
|
<a name="l02929"></a>02929 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">2</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
<a name="l02930"></a>02930 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0101</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b0</span>)
|
<a name="l02930"></a>02930
|
<a name="l02931"></a>02931 ) <span class="vhdlkeyword">begin</span>
|
<a name="l02931"></a>02931 <span class="keyword">// X for ASL</span>
|
<a name="l02932"></a>02932 <span class="keyword">// C,X,V</span>
|
<a name="l02932"></a>02932 <span class="keyword">//if(operand2[5:0] > 6'b0 && ir[8] == 1'b1 && ((ir[7:6] == 2'b11 && ir[10:9] == 2'b00) || (ir[7:6] != 2'b11 && ir[4:3] == 2'b00)) ) begin</span>
|
<a name="l02933"></a>02933 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
<a name="l02933"></a>02933 <span class="keyword">// X set to Dm</span>
|
<a name="l02934"></a>02934 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>); <span class="keyword">//=ccr[0];</span>
|
<a name="l02934"></a>02934 <span class="keyword">// sr[4] <= `Dm;</span>
|
<a name="l02935"></a>02935 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>) | (~<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
<a name="l02935"></a>02935 <span class="keyword">//end</span>
|
<a name="l02936"></a>02936 <span class="vhdlkeyword">end</span>
|
<a name="l02936"></a>02936 <span class="keyword">// else X not affected</span>
|
<a name="l02937"></a>02937 <span class="keyword">// SUBI,SUB to mem,SUB to Dn,SUBQ</span>
|
<a name="l02937"></a>02937
|
<a name="l02938"></a>02938 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">3'b010</span>) ||
|
<a name="l02938"></a>02938 <span class="keyword">// V cleared</span>
|
<a name="l02939"></a>02939 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1001</span>) ||
|
<a name="l02939"></a>02939 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>;
|
<a name="l02940"></a>02940 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0101</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b1</span>)
|
<a name="l02940"></a>02940 <span class="keyword">// C for ROXL,ROXR: set to X</span>
|
<a name="l02941"></a>02941 ) <span class="vhdlkeyword">begin</span>
|
<a name="l02941"></a>02941 <span class="vhdlkeyword">if</span>( (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">10</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">2'b10</span>) || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">2'b10</span>) ) <span class="vhdlkeyword">begin</span>
|
<a name="l02942"></a>02942 <span class="keyword">// C,X,V</span>
|
<a name="l02942"></a>02942 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>];
|
<a name="l02943"></a>02943 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
<a name="l02943"></a>02943 <span class="vhdlkeyword">end</span>
|
<a name="l02944"></a>02944 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>); <span class="keyword">//=ccr[0];</span>
|
<a name="l02944"></a>02944 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
<a name="l02945"></a>02945 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= (~<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
<a name="l02945"></a>02945 <span class="keyword">// C cleared</span>
|
<a name="l02946"></a>02946 <span class="vhdlkeyword">end</span>
|
<a name="l02946"></a>02946 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <span class="vhdllogic">1'b0</span>;
|
<a name="l02947"></a>02947 <span class="keyword">// ANDI,EORI,ORI,EOR,OR to mem,AND to mem,OR to Dn,AND to Dn</span>
|
<a name="l02947"></a>02947 <span class="vhdlkeyword">end</span>
|
<a name="l02948"></a>02948 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
<a name="l02948"></a>02948
|
<a name="l02949"></a>02949 <span class="keyword">// C,V</span>
|
<a name="l02949"></a>02949 <span class="keyword">// N set</span>
|
<a name="l02950"></a>02950 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <span class="vhdllogic">1'b0</span>;
|
<a name="l02950"></a>02950 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
<a name="l02951"></a>02951 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>;
|
<a name="l02951"></a>02951 <span class="keyword">// Z set</span>
|
<a name="l02952"></a>02952 <span class="keyword">// X not affected</span>
|
<a name="l02952"></a>02952 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">`Z</a><span class="vhdlchar"></span>;
|
<a name="l02953"></a>02953 <span class="vhdlkeyword">end</span>
|
<a name="l02953"></a>02953 <span class="vhdlkeyword">end</span>
|
<a name="l02954"></a>02954 <span class="vhdlkeyword">end</span>
|
<a name="l02954"></a>02954
|
<a name="l02955"></a>02955
|
<a name="l02955"></a>02955 <a class="code" href="ao68000_8v.html#ac946f278d039868214c441c11fcf2587">`ALU_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
<a name="l02956"></a>02956 <a class="code" href="ao68000_8v.html#a3e54001e73374bd4f7cfda3de55bd944">`ALU_ABCD_SBCD_ADDX_SUBX</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span> <span class="keyword">// 259 LE</span>
|
<a name="l02956"></a>02956
|
<a name="l02957"></a>02957 <span class="keyword">// ABCD</span>
|
<a name="l02957"></a>02957 <span class="keyword">// ASL</span>
|
<a name="l02958"></a>02958 <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">14</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">3'b100</span> ) <span class="vhdlkeyword">begin</span>
|
<a name="l02958"></a>02958 <span class="vhdlkeyword">if</span>( ((<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">10</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">2'b00</span>) || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">2'b00</span>)) && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
<a name="l02959"></a>02959 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] = {<span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>]} + {<span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>]} + {<span class="vhdllogic">4'b0</span>, <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>]};
|
<a name="l02959"></a>02959 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = {<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">30</span>:<span class="vhdllogic">0</span>], <span class="vhdllogic">1'b0</span>};
|
<a name="l02960"></a>02960 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] = {<span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>]} + {<span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>]};
|
<a name="l02960"></a>02960
|
<a name="l02961"></a>02961
|
<a name="l02961"></a>02961 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= (<a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b0</span>)? (<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> != <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) : <span class="vhdllogic">1'b1</span>; <span class="keyword">// V</span>
|
<a name="l02962"></a>02962 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">23</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] + <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] + {<span class="vhdllogic">7'b0</span>, <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>]};
|
<a name="l02962"></a>02962 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>; <span class="keyword">// C</span>
|
<a name="l02963"></a>02963
|
<a name="l02963"></a>02963 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>; <span class="keyword">// X</span>
|
<a name="l02964"></a>02964 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] = (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] > <span class="vhdllogic">6'd9</span>) ? (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] + <span class="vhdllogic">6'd6</span>) : <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>];
|
<a name="l02964"></a>02964 <span class="vhdlkeyword">end</span>
|
<a name="l02965"></a>02965 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] = (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] > <span class="vhdllogic">6'h1F</span>) ? (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] + <span class="vhdllogic">6'd2</span>) :
|
<a name="l02965"></a>02965 <span class="keyword">// LSL</span>
|
<a name="l02966"></a>02966 (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] > <span class="vhdllogic">6'h0F</span>) ? (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] + <span class="vhdllogic">6'd1</span>) :
|
<a name="l02966"></a>02966 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( ((<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">10</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">2'b01</span>) || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">2'b01</span>)) && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
<a name="l02967"></a>02967 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>];
|
<a name="l02967"></a>02967 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = {<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">30</span>:<span class="vhdllogic">0</span>], <span class="vhdllogic">1'b0</span>};
|
<a name="l02968"></a>02968 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] = (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] > <span class="vhdllogic">6'd9</span>) ? (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] + <span class="vhdllogic">6'd6</span>) : <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>];
|
<a name="l02968"></a>02968
|
<a name="l02969"></a>02969
|
<a name="l02969"></a>02969 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>; <span class="keyword">// V</span>
|
<a name="l02970"></a>02970 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] = <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">17</span>:<span class="vhdllogic">14</span>];
|
<a name="l02970"></a>02970 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>; <span class="keyword">// C</span>
|
<a name="l02971"></a>02971 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>];
|
<a name="l02971"></a>02971 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>; <span class="keyword">// X</span>
|
<a name="l02972"></a>02972
|
<a name="l02972"></a>02972 <span class="vhdlkeyword">end</span>
|
<a name="l02973"></a>02973 <span class="keyword">// C</span>
|
<a name="l02973"></a>02973 <span class="keyword">// ROL</span>
|
<a name="l02974"></a>02974 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] > <span class="vhdllogic">6'd9</span>) ? <span class="vhdllogic">1'b1</span> : <span class="vhdllogic">1'b0</span>;
|
<a name="l02974"></a>02974 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( ((<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">10</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">2'b11</span>) || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">2'b11</span>)) && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
<a name="l02975"></a>02975 <span class="keyword">// X = C</span>
|
<a name="l02975"></a>02975 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = {<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">30</span>:<span class="vhdllogic">0</span>], <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>};
|
<a name="l02976"></a>02976 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] > <span class="vhdllogic">6'd9</span>) ? <span class="vhdllogic">1'b1</span> : <span class="vhdllogic">1'b0</span>;
|
<a name="l02976"></a>02976
|
<a name="l02977"></a>02977
|
<a name="l02977"></a>02977 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>; <span class="keyword">// V</span>
|
<a name="l02978"></a>02978 <span class="keyword">// V</span>
|
<a name="l02978"></a>02978 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>; <span class="keyword">// C</span>
|
<a name="l02979"></a>02979 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">30</span>] == <span class="vhdllogic">1'b0</span> && <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>] == <span class="vhdllogic">1'b1</span>) ? <span class="vhdllogic">1'b1</span> : <span class="vhdllogic">1'b0</span>;
|
<a name="l02979"></a>02979 <span class="keyword">// X not affected</span>
|
<a name="l02980"></a>02980 <span class="vhdlkeyword">end</span>
|
<a name="l02980"></a>02980 <span class="vhdlkeyword">end</span>
|
<a name="l02981"></a>02981 <span class="keyword">// SBCD</span>
|
<a name="l02981"></a>02981 <span class="keyword">// ROXL</span>
|
<a name="l02982"></a>02982 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">14</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">3'b000</span> ) <span class="vhdlkeyword">begin</span>
|
<a name="l02982"></a>02982 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( ((<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">10</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">2'b10</span>) || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">2'b10</span>)) && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
<a name="l02983"></a>02983
|
<a name="l02983"></a>02983 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = {<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">30</span>:<span class="vhdllogic">0</span>], <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>]};
|
<a name="l02984"></a>02984 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] = <span class="vhdllogic">6'd32</span> + {<span class="vhdllogic">2'b0</span>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>]} - {<span class="vhdllogic">2'b0</span>, <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>]} - {<span class="vhdllogic">5'b0</span>, <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>]};
|
<a name="l02984"></a>02984
|
<a name="l02985"></a>02985 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] = <span class="vhdllogic">6'd32</span> + {<span class="vhdllogic">2'b0</span>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>]} - {<span class="vhdllogic">2'b0</span>, <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>]};
|
<a name="l02985"></a>02985 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>; <span class="keyword">// V</span>
|
<a name="l02986"></a>02986
|
<a name="l02986"></a>02986 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>; <span class="keyword">// C</span>
|
<a name="l02987"></a>02987 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">23</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] - <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] - {<span class="vhdllogic">7'b0</span>, <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>]};
|
<a name="l02987"></a>02987 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>; <span class="keyword">// X</span>
|
<a name="l02988"></a>02988
|
<a name="l02988"></a>02988 <span class="vhdlkeyword">end</span>
|
<a name="l02989"></a>02989 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] = (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] < <span class="vhdllogic">6'd32</span>) ? (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] - <span class="vhdllogic">6'd6</span>) : <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>];
|
<a name="l02989"></a>02989 <span class="keyword">// ASR</span>
|
<a name="l02990"></a>02990 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] = (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] < <span class="vhdllogic">6'd16</span>) ? (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] - <span class="vhdllogic">6'd2</span>) :
|
<a name="l02990"></a>02990 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( ((<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">10</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">2'b00</span>) || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">2'b00</span>)) && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
<a name="l02991"></a>02991 (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] < <span class="vhdllogic">6'd32</span>) ? (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] - <span class="vhdllogic">6'd1</span>) :
|
<a name="l02991"></a>02991 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] = { <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>], <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">1</span>] };
|
<a name="l02992"></a>02992 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>];
|
<a name="l02992"></a>02992 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] = { <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>], <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">1</span>] };
|
<a name="l02993"></a>02993 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] = (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] < <span class="vhdllogic">6'd32</span> && <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>] == <span class="vhdllogic">1'b1</span>) ? (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] - <span class="vhdllogic">6'd6</span>) : <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>];
|
<a name="l02993"></a>02993 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">2</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = { <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>], <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">1</span>] };
|
<a name="l02994"></a>02994
|
<a name="l02994"></a>02994
|
<a name="l02995"></a>02995 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] = <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">17</span>:<span class="vhdllogic">14</span>];
|
<a name="l02995"></a>02995 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>; <span class="keyword">// V</span>
|
<a name="l02996"></a>02996 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>];
|
<a name="l02996"></a>02996 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">0</span>]; <span class="keyword">// C</span>
|
<a name="l02997"></a>02997
|
<a name="l02997"></a>02997 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">0</span>]; <span class="keyword">// X</span>
|
<a name="l02998"></a>02998 <span class="keyword">// C</span>
|
<a name="l02998"></a>02998 <span class="vhdlkeyword">end</span>
|
<a name="l02999"></a>02999 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] < <span class="vhdllogic">6'd32</span>) ? <span class="vhdllogic">1'b1</span> : <span class="vhdllogic">1'b0</span>;
|
<a name="l02999"></a>02999 <span class="keyword">// LSR</span>
|
<a name="l03000"></a>03000 <span class="keyword">// X = C</span>
|
<a name="l03000"></a>03000 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( ((<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">10</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">2'b01</span>) || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">2'b01</span>)) && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
<a name="l03001"></a>03001 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] < <span class="vhdllogic">6'd32</span>) ? <span class="vhdllogic">1'b1</span> : <span class="vhdllogic">1'b0</span>;
|
<a name="l03001"></a>03001 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] = { <span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">1</span>] };
|
<a name="l03002"></a>03002
|
<a name="l03002"></a>03002 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] = { <span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">1</span>] };
|
<a name="l03003"></a>03003 <span class="keyword">// V</span>
|
<a name="l03003"></a>03003 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">2</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = { <span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">1</span>] };
|
<a name="l03004"></a>03004 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">30</span>] == <span class="vhdllogic">1'b1</span> && <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>] == <span class="vhdllogic">1'b0</span>) ? <span class="vhdllogic">1'b1</span> : <span class="vhdllogic">1'b0</span>;
|
<a name="l03004"></a>03004
|
<a name="l03005"></a>03005 <span class="vhdlkeyword">end</span>
|
<a name="l03005"></a>03005 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>; <span class="keyword">// V</span>
|
<a name="l03006"></a>03006 <span class="keyword">// ADDX</span>
|
<a name="l03006"></a>03006 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">0</span>]; <span class="keyword">// C</span>
|
<a name="l03007"></a>03007 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">14</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">3'b101</span> ) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] + <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] + <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>];
|
<a name="l03007"></a>03007 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">0</span>]; <span class="keyword">// X</span>
|
<a name="l03008"></a>03008 <span class="keyword">// SUBX</span>
|
<a name="l03008"></a>03008 <span class="vhdlkeyword">end</span>
|
<a name="l03009"></a>03009 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">14</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">3'b001</span> ) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] - <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] - <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>];
|
<a name="l03009"></a>03009 <span class="keyword">// ROR</span>
|
<a name="l03010"></a>03010
|
<a name="l03010"></a>03010 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( ((<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">10</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">2'b11</span>) || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">2'b11</span>)) && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
<a name="l03011"></a>03011 <span class="keyword">// Z</span>
|
<a name="l03011"></a>03011 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] = { <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">0</span>], <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">1</span>] };
|
<a name="l03012"></a>03012 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] & <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">`Z</a><span class="vhdlchar"></span>;
|
<a name="l03012"></a>03012 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] = { <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">0</span>], <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">1</span>] };
|
<a name="l03013"></a>03013 <span class="keyword">// N</span>
|
<a name="l03013"></a>03013 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">2</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = { <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">0</span>], <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">1</span>] };
|
<a name="l03014"></a>03014 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
<a name="l03014"></a>03014
|
<a name="l03015"></a>03015
|
<a name="l03015"></a>03015 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>; <span class="keyword">// V</span>
|
<a name="l03016"></a>03016 <span class="keyword">// ADDX</span>
|
<a name="l03016"></a>03016 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">0</span>]; <span class="keyword">// C</span>
|
<a name="l03017"></a>03017 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">14</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">3'b101</span> ) <span class="vhdlkeyword">begin</span>
|
<a name="l03017"></a>03017 <span class="keyword">// X not affected</span>
|
<a name="l03018"></a>03018 <span class="keyword">// C,X,V</span>
|
<a name="l03018"></a>03018 <span class="vhdlkeyword">end</span>
|
<a name="l03019"></a>03019 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
<a name="l03019"></a>03019 <span class="keyword">// ROXR</span>
|
<a name="l03020"></a>03020 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>); <span class="keyword">//=ccr[0];</span>
|
<a name="l03020"></a>03020 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( ((<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">10</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">2'b10</span>) || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">2'b10</span>)) && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
<a name="l03021"></a>03021 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>) | (~<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
<a name="l03021"></a>03021 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] = {<a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>], <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">1</span>]};
|
<a name="l03022"></a>03022 <span class="vhdlkeyword">end</span>
|
<a name="l03022"></a>03022 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] = {<a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>], <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">1</span>]};
|
<a name="l03023"></a>03023 <span class="keyword">// SUBX</span>
|
<a name="l03023"></a>03023 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">2</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = {<a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>], <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">1</span>]};
|
<a name="l03024"></a>03024 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">14</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">3'b001</span> ) <span class="vhdlkeyword">begin</span>
|
<a name="l03024"></a>03024
|
<a name="l03025"></a>03025 <span class="keyword">// C,X,V</span>
|
<a name="l03025"></a>03025 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>; <span class="keyword">// V</span>
|
<a name="l03026"></a>03026 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
<a name="l03026"></a>03026 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">0</span>]; <span class="keyword">// C</span>
|
<a name="l03027"></a>03027 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>); <span class="keyword">//=ccr[0];</span>
|
<a name="l03027"></a>03027 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">0</span>]; <span class="keyword">// X</span>
|
<a name="l03028"></a>03028 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= (~<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
<a name="l03028"></a>03028 <span class="vhdlkeyword">end</span>
|
<a name="l03029"></a>03029 <span class="vhdlkeyword">end</span>
|
<a name="l03029"></a>03029
|
<a name="l03030"></a>03030 <span class="vhdlkeyword">end</span>
|
<a name="l03030"></a>03030 <span class="keyword">// N set</span>
|
<a name="l03031"></a>03031
|
<a name="l03031"></a>03031 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
<a name="l03032"></a>03032 <a class="code" href="ao68000_8v.html#ac444f659b2726fd335e839dfadabbfe3">`ALU_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR_prepare</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
<a name="l03032"></a>03032 <span class="keyword">// Z set</span>
|
<a name="l03033"></a>03033
|
<a name="l03033"></a>03033 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">`Z</a><span class="vhdlchar"></span>;
|
<a name="l03034"></a>03034 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>];
|
<a name="l03034"></a>03034 <span class="vhdlkeyword">end</span>
|
<a name="l03035"></a>03035 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>];
|
<a name="l03035"></a>03035
|
<a name="l03036"></a>03036 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">2</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
<a name="l03036"></a>03036 <a class="code" href="ao68000_8v.html#a268aa82704bd8f1c1548dfc69a12a951">`ALU_MOVE</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
<a name="l03037"></a>03037
|
<a name="l03037"></a>03037 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>;
|
<a name="l03038"></a>03038 <span class="keyword">// X for ASL</span>
|
<a name="l03038"></a>03038
|
<a name="l03039"></a>03039 <span class="keyword">//if(operand2[5:0] > 6'b0 && ir[8] == 1'b1 && ((ir[7:6] == 2'b11 && ir[10:9] == 2'b00) || (ir[7:6] != 2'b11 && ir[4:3] == 2'b00)) ) begin</span>
|
<a name="l03039"></a>03039 <span class="keyword">// X not affected</span>
|
<a name="l03040"></a>03040 <span class="keyword">// X set to Dm</span>
|
<a name="l03040"></a>03040 <span class="keyword">// C cleared</span>
|
<a name="l03041"></a>03041 <span class="keyword">// sr[4] <= `Dm;</span>
|
<a name="l03041"></a>03041 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <span class="vhdllogic">1'b0</span>;
|
<a name="l03042"></a>03042 <span class="keyword">//end</span>
|
<a name="l03042"></a>03042 <span class="keyword">// V cleared</span>
|
<a name="l03043"></a>03043 <span class="keyword">// else X not affected</span>
|
<a name="l03043"></a>03043 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>;
|
<a name="l03044"></a>03044
|
<a name="l03044"></a>03044
|
<a name="l03045"></a>03045 <span class="keyword">// V cleared</span>
|
<a name="l03045"></a>03045 <span class="keyword">// N set</span>
|
<a name="l03046"></a>03046 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>;
|
<a name="l03046"></a>03046 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
<a name="l03047"></a>03047 <span class="keyword">// C for ROXL,ROXR: set to X</span>
|
<a name="l03047"></a>03047 <span class="keyword">// Z set</span>
|
<a name="l03048"></a>03048 <span class="vhdlkeyword">if</span>( (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">10</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">2'b10</span>) || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">2'b10</span>) ) <span class="vhdlkeyword">begin</span>
|
<a name="l03048"></a>03048 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">`Z</a><span class="vhdlchar"></span>;
|
<a name="l03049"></a>03049 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>];
|
<a name="l03049"></a>03049 <span class="vhdlkeyword">end</span>
|
<a name="l03050"></a>03050 <span class="vhdlkeyword">end</span>
|
<a name="l03050"></a>03050
|
<a name="l03051"></a>03051 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
<a name="l03051"></a>03051 <a class="code" href="ao68000_8v.html#a30a87601d2ca38286bb0d486d59f6a07">`ALU_ADDA_SUBA_CMPA_ADDQ_SUBQ</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
<a name="l03052"></a>03052 <span class="keyword">// C cleared</span>
|
<a name="l03052"></a>03052 <span class="keyword">// ADDA: 1101</span>
|
<a name="l03053"></a>03053 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <span class="vhdllogic">1'b0</span>;
|
<a name="l03053"></a>03053 <span class="keyword">// CMPA: 1011</span>
|
<a name="l03054"></a>03054 <span class="vhdlkeyword">end</span>
|
<a name="l03054"></a>03054 <span class="keyword">// SUBA: 1001</span>
|
<a name="l03055"></a>03055
|
<a name="l03055"></a>03055 <span class="keyword">// ADDQ,SUBQ: 0101 xxx0,1</span>
|
<a name="l03056"></a>03056 <span class="keyword">// N set</span>
|
<a name="l03056"></a>03056 <span class="keyword">// operation requires that operand2 was sign extended</span>
|
<a name="l03057"></a>03057 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
<a name="l03057"></a>03057
|
<a name="l03058"></a>03058 <span class="keyword">// Z set</span>
|
<a name="l03058"></a>03058 <span class="keyword">// ADDA,ADDQ</span>
|
<a name="l03059"></a>03059 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">`Z</a><span class="vhdlchar"></span>;
|
<a name="l03059"></a>03059 <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1101</span> || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0101</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b0</span>) )
|
<a name="l03060"></a>03060 <span class="vhdlkeyword">end</span>
|
<a name="l03060"></a>03060 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] + <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
<a name="l03061"></a>03061
|
<a name="l03061"></a>03061 <span class="keyword">// SUBA,CMPA,SUBQ</span>
|
<a name="l03062"></a>03062 <a class="code" href="ao68000_8v.html#ac946f278d039868214c441c11fcf2587">`ALU_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
<a name="l03062"></a>03062 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1001</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1011</span> || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0101</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b1</span>) )
|
<a name="l03063"></a>03063
|
<a name="l03063"></a>03063 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] - <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
<a name="l03064"></a>03064 <span class="keyword">// ASL</span>
|
<a name="l03064"></a>03064
|
<a name="l03065"></a>03065 <span class="vhdlkeyword">if</span>( ((<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">10</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">2'b00</span>) || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">2'b00</span>)) && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
<a name="l03065"></a>03065 <span class="keyword">// for CMPA</span>
|
<a name="l03066"></a>03066 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = {<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">30</span>:<span class="vhdllogic">0</span>], <span class="vhdllogic">1'b0</span>};
|
<a name="l03066"></a>03066 <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1011</span> ) <span class="vhdlkeyword">begin</span>
|
<a name="l03067"></a>03067
|
<a name="l03067"></a>03067 <span class="keyword">// Z</span>
|
<a name="l03068"></a>03068 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= (<a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b0</span>)? (<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> != <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) : <span class="vhdllogic">1'b1</span>; <span class="keyword">// V</span>
|
<a name="l03068"></a>03068 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">`Z</a><span class="vhdlchar"></span>;
|
<a name="l03069"></a>03069 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>; <span class="keyword">// C</span>
|
<a name="l03069"></a>03069 <span class="keyword">// N</span>
|
<a name="l03070"></a>03070 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>; <span class="keyword">// X</span>
|
<a name="l03070"></a>03070 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
<a name="l03071"></a>03071 <span class="vhdlkeyword">end</span>
|
<a name="l03071"></a>03071
|
<a name="l03072"></a>03072 <span class="keyword">// LSL</span>
|
<a name="l03072"></a>03072 <span class="keyword">// C,V</span>
|
<a name="l03073"></a>03073 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( ((<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">10</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">2'b01</span>) || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">2'b01</span>)) && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
<a name="l03073"></a>03073 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
<a name="l03074"></a>03074 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = {<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">30</span>:<span class="vhdllogic">0</span>], <span class="vhdllogic">1'b0</span>};
|
<a name="l03074"></a>03074 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= (~<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
<a name="l03075"></a>03075
|
<a name="l03075"></a>03075 <span class="keyword">// X not affected</span>
|
<a name="l03076"></a>03076 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>; <span class="keyword">// V</span>
|
<a name="l03076"></a>03076 <span class="vhdlkeyword">end</span>
|
<a name="l03077"></a>03077 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>; <span class="keyword">// C</span>
|
<a name="l03077"></a>03077 <span class="keyword">// for ADDA,SUBA,ADDQ,SUBQ: ccr not affected</span>
|
<a name="l03078"></a>03078 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>; <span class="keyword">// X</span>
|
<a name="l03078"></a>03078 <span class="vhdlkeyword">end</span>
|
<a name="l03079"></a>03079 <span class="vhdlkeyword">end</span>
|
<a name="l03079"></a>03079
|
<a name="l03080"></a>03080 <span class="keyword">// ROL</span>
|
<a name="l03080"></a>03080 <a class="code" href="ao68000_8v.html#af0a4db089a5eb288abf9453ca2d79c26">`ALU_CHK</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
<a name="l03081"></a>03081 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( ((<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">10</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">2'b11</span>) || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">2'b11</span>)) && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
<a name="l03081"></a>03081 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] - <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>];
|
<a name="l03082"></a>03082 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = {<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">30</span>:<span class="vhdllogic">0</span>], <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>};
|
<a name="l03082"></a>03082
|
<a name="l03083"></a>03083
|
<a name="l03083"></a>03083 <span class="keyword">// undocumented behavior: Z flag, see 68knotes.txt</span>
|
<a name="l03084"></a>03084 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>; <span class="keyword">// V</span>
|
<a name="l03084"></a>03084 <span class="keyword">//sr[2] <= (operand1[15:0] == 16'b0) ? 1'b1 : 1'b0;</span>
|
<a name="l03085"></a>03085 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>; <span class="keyword">// C</span>
|
<a name="l03085"></a>03085 <span class="keyword">// undocumented behavior: C,V flags, see 68knotes.txt</span>
|
<a name="l03086"></a>03086 <span class="keyword">// X not affected</span>
|
<a name="l03086"></a>03086 <span class="keyword">//sr[0] <= 1'b0;</span>
|
<a name="l03087"></a>03087 <span class="vhdlkeyword">end</span>
|
<a name="l03087"></a>03087 <span class="keyword">//sr[1] <= 1'b0;</span>
|
<a name="l03088"></a>03088 <span class="keyword">// ROXL</span>
|
<a name="l03088"></a>03088
|
<a name="l03089"></a>03089 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( ((<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">10</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">2'b10</span>) || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">2'b10</span>)) && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
<a name="l03089"></a>03089 <span class="keyword">// C,X,V</span>
|
<a name="l03090"></a>03090 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = {<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">30</span>:<span class="vhdllogic">0</span>], <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>]};
|
<a name="l03090"></a>03090 <span class="keyword">// sr[0] <= (`Sm & ~`Dm) | (`Rm & ~`Dm) | (`Sm & `Rm);</span>
|
<a name="l03091"></a>03091
|
<a name="l03091"></a>03091 <span class="keyword">// sr[4] <= (`Sm & ~`Dm) | (`Rm & ~`Dm) | (`Sm & `Rm); //=ccr[0];</span>
|
<a name="l03092"></a>03092 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>; <span class="keyword">// V</span>
|
<a name="l03092"></a>03092 <span class="keyword">// sr[1] <= (~`Sm & `Dm & ~`Rm) | (`Sm & ~`Dm & `Rm);</span>
|
<a name="l03093"></a>03093 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>; <span class="keyword">// C</span>
|
<a name="l03093"></a>03093 <span class="keyword">// +: 0-1, 0-0=0, 1-1=0</span>
|
<a name="l03094"></a>03094 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>; <span class="keyword">// X</span>
|
<a name="l03094"></a>03094 <span class="keyword">// -: 0-0=1, 1-0, 1-1=1</span>
|
<a name="l03095"></a>03095 <span class="vhdlkeyword">end</span>
|
<a name="l03095"></a>03095 <span class="keyword">// operand1 - operand2 > 0</span>
|
<a name="l03096"></a>03096 <span class="keyword">// ASR</span>
|
<a name="l03096"></a>03096 <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] != <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] && ((~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span>) | (~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>)) == <span class="vhdllogic">1'b1</span> ) <span class="vhdlkeyword">begin</span>
|
<a name="l03097"></a>03097 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( ((<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">10</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">2'b00</span>) || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">2'b00</span>)) && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
<a name="l03097"></a>03097 <span class="keyword">// clear N</span>
|
<a name="l03098"></a>03098 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] = { <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>], <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">1</span>] };
|
<a name="l03098"></a>03098 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= <span class="vhdllogic">1'b0</span>;
|
<a name="l03099"></a>03099 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] = { <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>], <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">1</span>] };
|
<a name="l03099"></a>03099 <a class="code" href="classalu.html#a41770492859599997a003e2681e7d955">alu_signal</a> <= <span class="vhdllogic">1'b1</span>;
|
<a name="l03100"></a>03100 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">2</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = { <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>], <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">1</span>] };
|
<a name="l03100"></a>03100 <span class="vhdlkeyword">end</span>
|
<a name="l03101"></a>03101
|
<a name="l03101"></a>03101 <span class="keyword">// operand1 < 0</span>
|
<a name="l03102"></a>03102 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>; <span class="keyword">// V</span>
|
<a name="l03102"></a>03102 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>] == <span class="vhdllogic">1'b1</span> ) <span class="vhdlkeyword">begin</span>
|
<a name="l03103"></a>03103 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">0</span>]; <span class="keyword">// C</span>
|
<a name="l03103"></a>03103 <span class="keyword">// set N</span>
|
<a name="l03104"></a>03104 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">0</span>]; <span class="keyword">// X</span>
|
<a name="l03104"></a>03104 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= <span class="vhdllogic">1'b1</span>;
|
<a name="l03105"></a>03105 <span class="vhdlkeyword">end</span>
|
<a name="l03105"></a>03105 <a class="code" href="classalu.html#a41770492859599997a003e2681e7d955">alu_signal</a> <= <span class="vhdllogic">1'b1</span>;
|
<a name="l03106"></a>03106 <span class="keyword">// LSR</span>
|
<a name="l03106"></a>03106 <span class="vhdlkeyword">end</span>
|
<a name="l03107"></a>03107 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( ((<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">10</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">2'b01</span>) || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">2'b01</span>)) && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
<a name="l03107"></a>03107 <span class="keyword">// no trap</span>
|
<a name="l03108"></a>03108 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] = { <span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">1</span>] };
|
<a name="l03108"></a>03108 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
<a name="l03109"></a>03109 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] = { <span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">1</span>] };
|
<a name="l03109"></a>03109 <span class="keyword">// N undefined: not affected</span>
|
<a name="l03110"></a>03110 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">2</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = { <span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">1</span>] };
|
<a name="l03110"></a>03110 <a class="code" href="classalu.html#a41770492859599997a003e2681e7d955">alu_signal</a> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l03111"></a>03111
|
<a name="l03111"></a>03111 <span class="vhdlkeyword">end</span>
|
<a name="l03112"></a>03112 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>; <span class="keyword">// V</span>
|
<a name="l03112"></a>03112
|
<a name="l03113"></a>03113 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">0</span>]; <span class="keyword">// C</span>
|
<a name="l03113"></a>03113 <span class="keyword">// X not affected</span>
|
<a name="l03114"></a>03114 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">0</span>]; <span class="keyword">// X</span>
|
<a name="l03114"></a>03114 <span class="vhdlkeyword">end</span>
|
<a name="l03115"></a>03115 <span class="vhdlkeyword">end</span>
|
<a name="l03115"></a>03115
|
<a name="l03116"></a>03116 <span class="keyword">// ROR</span>
|
<a name="l03116"></a>03116 <a class="code" href="ao68000_8v.html#aed07d190bb88f0cce7768028698020f9">`ALU_MULS_MULU_DIVS_DIVU</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
<a name="l03117"></a>03117 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( ((<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">10</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">2'b11</span>) || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">2'b11</span>)) && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
<a name="l03117"></a>03117
|
<a name="l03118"></a>03118 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] = { <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">0</span>], <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">1</span>] };
|
<a name="l03118"></a>03118 <span class="keyword">// division by 0</span>
|
<a name="l03119"></a>03119 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] = { <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">0</span>], <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">1</span>] };
|
<a name="l03119"></a>03119 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1000</span> && <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0</span>) <span class="vhdlkeyword">begin</span>
|
<a name="l03120"></a>03120 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">2</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = { <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">0</span>], <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">1</span>] };
|
<a name="l03120"></a>03120 <span class="keyword">// X not affected</span>
|
<a name="l03121"></a>03121
|
<a name="l03121"></a>03121 <span class="keyword">// C cleared</span>
|
<a name="l03122"></a>03122 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>; <span class="keyword">// V</span>
|
<a name="l03122"></a>03122 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <span class="vhdllogic">1'b0</span>;
|
<a name="l03123"></a>03123 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">0</span>]; <span class="keyword">// C</span>
|
<a name="l03123"></a>03123 <span class="keyword">// V,Z,N undefined: cleared</span>
|
<a name="l03124"></a>03124 <span class="keyword">// X not affected</span>
|
<a name="l03124"></a>03124 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>;
|
<a name="l03125"></a>03125 <span class="vhdlkeyword">end</span>
|
<a name="l03125"></a>03125 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= <span class="vhdllogic">1'b0</span>;
|
<a name="l03126"></a>03126 <span class="keyword">// ROXR</span>
|
<a name="l03126"></a>03126 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= <span class="vhdllogic">1'b0</span>;
|
<a name="l03127"></a>03127 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( ((<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">10</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">2'b10</span>) || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">2'b10</span>)) && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
<a name="l03127"></a>03127
|
<a name="l03128"></a>03128 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] = {<a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>], <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">1</span>]};
|
<a name="l03128"></a>03128 <span class="keyword">// set trap</span>
|
<a name="l03129"></a>03129 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] = {<a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>], <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">1</span>]};
|
<a name="l03129"></a>03129 <a class="code" href="classalu.html#a41770492859599997a003e2681e7d955">alu_signal</a> <= <span class="vhdllogic">1'b1</span>;
|
<a name="l03130"></a>03130 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">2</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = {<a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>], <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">1</span>]};
|
<a name="l03130"></a>03130 <span class="vhdlkeyword">end</span>
|
<a name="l03131"></a>03131
|
<a name="l03131"></a>03131 <span class="keyword">// division in idle state</span>
|
<a name="l03132"></a>03132 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>; <span class="keyword">// V</span>
|
<a name="l03132"></a>03132 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1000</span> && <a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a> == <span class="vhdllogic">5'd0</span>) <span class="vhdlkeyword">begin</span>
|
<a name="l03133"></a>03133 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">0</span>]; <span class="keyword">// C</span>
|
<a name="l03133"></a>03133 <a class="code" href="classalu.html#a41770492859599997a003e2681e7d955">alu_signal</a> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l03134"></a>03134 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">0</span>]; <span class="keyword">// X</span>
|
<a name="l03134"></a>03134 <span class="vhdlkeyword">end</span>
|
<a name="l03135"></a>03135 <span class="vhdlkeyword">end</span>
|
<a name="l03135"></a>03135 <span class="keyword">// division overflow: divu, divs</span>
|
<a name="l03136"></a>03136
|
<a name="l03136"></a>03136 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1000</span> && <a class="code" href="classalu.html#a8d11b113e74362e74035541da1b0a02e">div_overflow</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
<a name="l03137"></a>03137 <span class="keyword">// N set</span>
|
<a name="l03137"></a>03137 <span class="keyword">// X not affected</span>
|
<a name="l03138"></a>03138 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
<a name="l03138"></a>03138 <span class="keyword">// C cleared</span>
|
<a name="l03139"></a>03139 <span class="keyword">// Z set</span>
|
<a name="l03139"></a>03139 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <span class="vhdllogic">1'b0</span>;
|
<a name="l03140"></a>03140 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">`Z</a><span class="vhdlchar"></span>;
|
<a name="l03140"></a>03140 <span class="keyword">// V set</span>
|
<a name="l03141"></a>03141 <span class="vhdlkeyword">end</span>
|
<a name="l03141"></a>03141 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b1</span>;
|
<a name="l03142"></a>03142
|
<a name="l03142"></a>03142 <span class="keyword">// Z,N undefined: cleared and set</span>
|
<a name="l03143"></a>03143 <a class="code" href="ao68000_8v.html#a268aa82704bd8f1c1548dfc69a12a951">`ALU_MOVE</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
<a name="l03143"></a>03143 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= <span class="vhdllogic">1'b0</span>;
|
<a name="l03144"></a>03144 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>;
|
<a name="l03144"></a>03144 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= <span class="vhdllogic">1'b1</span>;
|
<a name="l03145"></a>03145
|
<a name="l03145"></a>03145
|
<a name="l03146"></a>03146 <span class="keyword">// X not affected</span>
|
<a name="l03146"></a>03146 <span class="keyword">// set trap</span>
|
<a name="l03147"></a>03147 <span class="keyword">// C cleared</span>
|
<a name="l03147"></a>03147 <a class="code" href="classalu.html#a41770492859599997a003e2681e7d955">alu_signal</a> <= <span class="vhdllogic">1'b1</span>;
|
<a name="l03148"></a>03148 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <span class="vhdllogic">1'b0</span>;
|
<a name="l03148"></a>03148 <span class="vhdlkeyword">end</span>
|
<a name="l03149"></a>03149 <span class="keyword">// V cleared</span>
|
<a name="l03149"></a>03149 <span class="keyword">// division</span>
|
<a name="l03150"></a>03150 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>;
|
<a name="l03150"></a>03150 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1000</span> ) <span class="vhdlkeyword">begin</span>
|
<a name="l03151"></a>03151
|
<a name="l03151"></a>03151 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <= {<a class="code" href="classalu.html#ad32bb10563baa2d2d78c2a23e8f2219e">div_remainder</a>, <a class="code" href="classalu.html#af65ee78a38f09889c3b8c9efc759f559">div_quotient</a>};
|
<a name="l03152"></a>03152 <span class="keyword">// N set</span>
|
<a name="l03152"></a>03152
|
<a name="l03153"></a>03153 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
<a name="l03153"></a>03153 <span class="keyword">// X not affected</span>
|
<a name="l03154"></a>03154 <span class="keyword">// Z set</span>
|
<a name="l03154"></a>03154 <span class="keyword">// C cleared</span>
|
<a name="l03155"></a>03155 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">`Z</a><span class="vhdlchar"></span>;
|
<a name="l03155"></a>03155 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <span class="vhdllogic">1'b0</span>;
|
<a name="l03156"></a>03156 <span class="vhdlkeyword">end</span>
|
<a name="l03156"></a>03156 <span class="keyword">// V cleared</span>
|
<a name="l03157"></a>03157
|
<a name="l03157"></a>03157 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>;
|
<a name="l03158"></a>03158 <a class="code" href="ao68000_8v.html#a30a87601d2ca38286bb0d486d59f6a07">`ALU_ADDA_SUBA_CMPA_ADDQ_SUBQ</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
<a name="l03158"></a>03158 <span class="keyword">// Z</span>
|
<a name="l03159"></a>03159 <span class="keyword">// ADDA: 1101</span>
|
<a name="l03159"></a>03159 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= (<a class="code" href="classalu.html#af65ee78a38f09889c3b8c9efc759f559">div_quotient</a> == <span class="vhdllogic">16'b0</span>);
|
<a name="l03160"></a>03160 <span class="keyword">// CMPA: 1011</span>
|
<a name="l03160"></a>03160 <span class="keyword">// N</span>
|
<a name="l03161"></a>03161 <span class="keyword">// SUBA: 1001</span>
|
<a name="l03161"></a>03161 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= (<a class="code" href="classalu.html#af65ee78a38f09889c3b8c9efc759f559">div_quotient</a>[<span class="vhdllogic">15</span>] == <span class="vhdllogic">1'b1</span>);
|
<a name="l03162"></a>03162 <span class="keyword">// ADDQ,SUBQ: 0101 xxx0,1</span>
|
<a name="l03162"></a>03162
|
<a name="l03163"></a>03163 <span class="keyword">// operation requires that operand2 was sign extended</span>
|
<a name="l03163"></a>03163 <span class="keyword">// set trap</span>
|
<a name="l03164"></a>03164
|
<a name="l03164"></a>03164 <a class="code" href="classalu.html#a41770492859599997a003e2681e7d955">alu_signal</a> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l03165"></a>03165 <span class="keyword">// ADDA,ADDQ</span>
|
<a name="l03165"></a>03165 <span class="vhdlkeyword">end</span>
|
<a name="l03166"></a>03166 <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1101</span> || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0101</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b0</span>) )
|
<a name="l03166"></a>03166 <span class="keyword">// multiplication</span>
|
<a name="l03167"></a>03167 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] + <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
<a name="l03167"></a>03167 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1100</span> ) <span class="vhdlkeyword">begin</span>
|
<a name="l03168"></a>03168 <span class="keyword">// SUBA,CMPA,SUBQ</span>
|
<a name="l03168"></a>03168 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#aff5530027f36561324e060e703004b6b">mult_result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
<a name="l03169"></a>03169 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1001</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1011</span> || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0101</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b1</span>) )
|
<a name="l03169"></a>03169
|
<a name="l03170"></a>03170 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] - <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
<a name="l03170"></a>03170 <span class="keyword">// X not affected</span>
|
<a name="l03171"></a>03171
|
<a name="l03171"></a>03171 <span class="keyword">// C cleared</span>
|
<a name="l03172"></a>03172 <span class="keyword">// for CMPA</span>
|
<a name="l03172"></a>03172 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <span class="vhdllogic">1'b0</span>;
|
<a name="l03173"></a>03173 <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1011</span> ) <span class="vhdlkeyword">begin</span>
|
<a name="l03173"></a>03173 <span class="keyword">// V cleared</span>
|
<a name="l03174"></a>03174 <span class="keyword">// Z</span>
|
<a name="l03174"></a>03174 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>;
|
<a name="l03175"></a>03175 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">`Z</a><span class="vhdlchar"></span>;
|
<a name="l03175"></a>03175 <span class="keyword">// Z</span>
|
<a name="l03176"></a>03176 <span class="keyword">// N</span>
|
<a name="l03176"></a>03176 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= (<a class="code" href="classalu.html#aff5530027f36561324e060e703004b6b">mult_result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">32'b0</span>);
|
<a name="l03177"></a>03177 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
<a name="l03177"></a>03177 <span class="keyword">// N</span>
|
<a name="l03178"></a>03178
|
<a name="l03178"></a>03178 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= (<a class="code" href="classalu.html#aff5530027f36561324e060e703004b6b">mult_result</a>[<span class="vhdllogic">31</span>] == <span class="vhdllogic">1'b1</span>);
|
<a name="l03179"></a>03179 <span class="keyword">// C,V</span>
|
<a name="l03179"></a>03179
|
<a name="l03180"></a>03180 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
<a name="l03180"></a>03180 <span class="keyword">// set trap</span>
|
<a name="l03181"></a>03181 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= (~<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
<a name="l03181"></a>03181 <a class="code" href="classalu.html#a41770492859599997a003e2681e7d955">alu_signal</a> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l03182"></a>03182 <span class="keyword">// X not affected</span>
|
<a name="l03182"></a>03182 <span class="vhdlkeyword">end</span>
|
<a name="l03183"></a>03183 <span class="vhdlkeyword">end</span>
|
<a name="l03183"></a>03183 <span class="vhdlkeyword">end</span>
|
<a name="l03184"></a>03184 <span class="keyword">// for ADDA,SUBA,ADDQ,SUBQ: ccr not affected</span>
|
<a name="l03184"></a>03184
|
<a name="l03185"></a>03185 <span class="vhdlkeyword">end</span>
|
<a name="l03185"></a>03185
|
<a name="l03186"></a>03186
|
<a name="l03186"></a>03186 <a class="code" href="ao68000_8v.html#a14b85ce3e5b4ede3b2c4e89f420c8c3c">`ALU_BCHG_BCLR_BSET_BTST</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span> <span class="keyword">// 97 LE</span>
|
<a name="l03187"></a>03187 <a class="code" href="ao68000_8v.html#af0a4db089a5eb288abf9453ca2d79c26">`ALU_CHK</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
<a name="l03187"></a>03187 <span class="keyword">// byte</span>
|
<a name="l03188"></a>03188 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] - <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>];
|
<a name="l03188"></a>03188 <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b000</span> ) <span class="vhdlkeyword">begin</span>
|
<a name="l03189"></a>03189
|
<a name="l03189"></a>03189 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= ~(<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[ <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] ]);
|
<a name="l03190"></a>03190 <span class="keyword">// undocumented behavior: Z flag, see 68knotes.txt</span>
|
<a name="l03190"></a>03190 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>;
|
<a name="l03191"></a>03191 <span class="keyword">//sr[2] <= (operand1[15:0] == 16'b0) ? 1'b1 : 1'b0;</span>
|
<a name="l03191"></a>03191 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[ <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] ] = (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b01</span>) ? ~(<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[ <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] ]) : (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b10</span>) ? <span class="vhdllogic">1'b0</span> : <span class="vhdllogic">1'b1</span>;
|
<a name="l03192"></a>03192 <span class="keyword">// undocumented behavior: C,V flags, see 68knotes.txt</span>
|
<a name="l03192"></a>03192 <span class="vhdlkeyword">end</span>
|
<a name="l03193"></a>03193 <span class="keyword">//sr[0] <= 1'b0;</span>
|
<a name="l03193"></a>03193 <span class="keyword">// long</span>
|
<a name="l03194"></a>03194 <span class="keyword">//sr[1] <= 1'b0;</span>
|
<a name="l03194"></a>03194 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b000</span> ) <span class="vhdlkeyword">begin</span>
|
<a name="l03195"></a>03195
|
<a name="l03195"></a>03195 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= ~(<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[ <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">0</span>] ]);
|
<a name="l03196"></a>03196 <span class="keyword">// C,X,V</span>
|
<a name="l03196"></a>03196 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>;
|
<a name="l03197"></a>03197 <span class="keyword">// sr[0] <= (`Sm & ~`Dm) | (`Rm & ~`Dm) | (`Sm & `Rm);</span>
|
<a name="l03197"></a>03197 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[ <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">0</span>] ] = (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b01</span>) ? ~(<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[ <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">0</span>] ]) : (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b10</span>) ? <span class="vhdllogic">1'b0</span> : <span class="vhdllogic">1'b1</span>;
|
<a name="l03198"></a>03198 <span class="keyword">// sr[4] <= (`Sm & ~`Dm) | (`Rm & ~`Dm) | (`Sm & `Rm); //=ccr[0];</span>
|
<a name="l03198"></a>03198 <span class="vhdlkeyword">end</span>
|
<a name="l03199"></a>03199 <span class="keyword">// sr[1] <= (~`Sm & `Dm & ~`Rm) | (`Sm & ~`Dm & `Rm);</span>
|
<a name="l03199"></a>03199
|
<a name="l03200"></a>03200 <span class="keyword">// +: 0-1, 0-0=0, 1-1=0</span>
|
<a name="l03200"></a>03200 <span class="keyword">// C,V,N,X not affected</span>
|
<a name="l03201"></a>03201 <span class="keyword">// -: 0-0=1, 1-0, 1-1=1</span>
|
<a name="l03201"></a>03201 <span class="vhdlkeyword">end</span>
|
<a name="l03202"></a>03202 <span class="keyword">// operand1 - operand2 > 0</span>
|
<a name="l03202"></a>03202
|
<a name="l03203"></a>03203 <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] != <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] && ((~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span>) | (~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>)) == <span class="vhdllogic">1'b1</span> ) <span class="vhdlkeyword">begin</span>
|
<a name="l03203"></a>03203 <a class="code" href="ao68000_8v.html#ac7de3ab6c8eec4381bde5e4f61b45761">`ALU_TAS</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
<a name="l03204"></a>03204 <span class="keyword">// clear N</span>
|
<a name="l03204"></a>03204 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <= { <span class="vhdllogic">1'b1</span>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">6</span>:<span class="vhdllogic">0</span>] };
|
<a name="l03205"></a>03205 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= <span class="vhdllogic">1'b0</span>;
|
<a name="l03205"></a>03205
|
<a name="l03206"></a>03206 <a class="code" href="classalu.html#a41770492859599997a003e2681e7d955">alu_signal</a> <= <span class="vhdllogic">1'b1</span>;
|
<a name="l03206"></a>03206 <span class="keyword">// X not affected</span>
|
<a name="l03207"></a>03207 <span class="vhdlkeyword">end</span>
|
<a name="l03207"></a>03207 <span class="keyword">// C cleared</span>
|
<a name="l03208"></a>03208 <span class="keyword">// operand1 < 0</span>
|
<a name="l03208"></a>03208 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <span class="vhdllogic">1'b0</span>;
|
<a name="l03209"></a>03209 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>] == <span class="vhdllogic">1'b1</span> ) <span class="vhdlkeyword">begin</span>
|
<a name="l03209"></a>03209 <span class="keyword">// V cleared</span>
|
<a name="l03210"></a>03210 <span class="keyword">// set N</span>
|
<a name="l03210"></a>03210 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>;
|
<a name="l03211"></a>03211 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= <span class="vhdllogic">1'b1</span>;
|
<a name="l03211"></a>03211
|
<a name="l03212"></a>03212 <a class="code" href="classalu.html#a41770492859599997a003e2681e7d955">alu_signal</a> <= <span class="vhdllogic">1'b1</span>;
|
<a name="l03212"></a>03212 <span class="keyword">// N set</span>
|
<a name="l03213"></a>03213 <span class="vhdlkeyword">end</span>
|
<a name="l03213"></a>03213 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= (<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>] == <span class="vhdllogic">1'b1</span>);
|
<a name="l03214"></a>03214 <span class="keyword">// no trap</span>
|
<a name="l03214"></a>03214 <span class="keyword">// Z set</span>
|
<a name="l03215"></a>03215 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
<a name="l03215"></a>03215 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= (<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">8'b0</span>);
|
<a name="l03216"></a>03216 <span class="keyword">// N undefined: not affected</span>
|
<a name="l03216"></a>03216 <span class="vhdlkeyword">end</span>
|
<a name="l03217"></a>03217 <a class="code" href="classalu.html#a41770492859599997a003e2681e7d955">alu_signal</a> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l03217"></a>03217
|
<a name="l03218"></a>03218 <span class="vhdlkeyword">end</span>
|
<a name="l03218"></a>03218
|
<a name="l03219"></a>03219
|
<a name="l03219"></a>03219 <a class="code" href="ao68000_8v.html#a07c7e53af3f4995a167966ba18c2728f">`ALU_NEGX_CLR_NEG_NOT_NBCD_SWAP_EXT</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
<a name="l03220"></a>03220 <span class="keyword">// X not affected</span>
|
<a name="l03220"></a>03220 <span class="keyword">// NEGX / CLR / NEG / NOT</span>
|
<a name="l03221"></a>03221 <span class="vhdlkeyword">end</span>
|
<a name="l03221"></a>03221 <span class="vhdlkeyword">if</span> ((<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0000</span>) || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0010</span>) || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0100</span>) || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0110</span>))
|
<a name="l03222"></a>03222
|
<a name="l03222"></a>03222 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> = <span class="vhdllogic">32'b0</span> - (<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] & {<span class="vhdllogic">32</span>{<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">10</span>] | ~<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">9</span>]}}) - ((<a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] & ~<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">10</span>] & ~<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">9</span>]) | (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">10</span>] & <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">9</span>]));
|
<a name="l03223"></a>03223 <a class="code" href="ao68000_8v.html#aed07d190bb88f0cce7768028698020f9">`ALU_MULS_MULU_DIVS_DIVU</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
<a name="l03223"></a>03223 <span class="keyword">// NBCD</span>
|
<a name="l03224"></a>03224
|
<a name="l03224"></a>03224 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">6'b1000_00</span> ) <span class="vhdlkeyword">begin</span>
|
<a name="l03225"></a>03225 <span class="keyword">// division by 0</span>
|
<a name="l03225"></a>03225
|
<a name="l03226"></a>03226 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1000</span> && <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0</span>) <span class="vhdlkeyword">begin</span>
|
<a name="l03226"></a>03226 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] = <span class="vhdllogic">5'd25</span> - <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>];
|
<a name="l03227"></a>03227 <span class="keyword">// X not affected</span>
|
<a name="l03227"></a>03227 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] = (<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] > <span class="vhdllogic">4'd9</span>) ? (<span class="vhdllogic">5'd24</span> - <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>]) : (<span class="vhdllogic">5'd25</span> - <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>]);
|
<a name="l03228"></a>03228 <span class="keyword">// C cleared</span>
|
<a name="l03228"></a>03228
|
<a name="l03229"></a>03229 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <span class="vhdllogic">1'b0</span>;
|
<a name="l03229"></a>03229 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] == <span class="vhdllogic">1'b0</span> && <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">4'd9</span> && <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">4'd9</span>) <span class="vhdlkeyword">begin</span>
|
<a name="l03230"></a>03230 <span class="keyword">// V,Z,N undefined: cleared</span>
|
<a name="l03230"></a>03230 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] = <span class="vhdllogic">4'd0</span>;
|
<a name="l03231"></a>03231 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>;
|
<a name="l03231"></a>03231 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] = <span class="vhdllogic">4'd0</span>;
|
<a name="l03232"></a>03232 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= <span class="vhdllogic">1'b0</span>;
|
<a name="l03232"></a>03232 <span class="vhdlkeyword">end</span>
|
<a name="l03233"></a>03233 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= <span class="vhdllogic">1'b0</span>;
|
<a name="l03233"></a>03233 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] == <span class="vhdllogic">1'b0</span> && (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">4'd9</span> || <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">4'd15</span>)) <span class="vhdlkeyword">begin</span>
|
<a name="l03234"></a>03234
|
<a name="l03234"></a>03234 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] = <span class="vhdllogic">4'd0</span>;
|
<a name="l03235"></a>03235 <span class="keyword">// set trap</span>
|
<a name="l03235"></a>03235 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] = <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] + <span class="vhdllogic">4'd1</span>;
|
<a name="l03236"></a>03236 <a class="code" href="classalu.html#a41770492859599997a003e2681e7d955">alu_signal</a> <= <span class="vhdllogic">1'b1</span>;
|
<a name="l03236"></a>03236 <span class="vhdlkeyword">end</span>
|
<a name="l03237"></a>03237 <span class="vhdlkeyword">end</span>
|
<a name="l03237"></a>03237 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
<a name="l03238"></a>03238 <span class="keyword">// division in idle state</span>
|
<a name="l03238"></a>03238 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] + <span class="vhdllogic">4'd1</span>;
|
<a name="l03239"></a>03239 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1000</span> && <a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a> == <span class="vhdllogic">5'd0</span>) <span class="vhdlkeyword">begin</span>
|
<a name="l03239"></a>03239 <span class="vhdlkeyword">end</span>
|
<a name="l03240"></a>03240 <a class="code" href="classalu.html#a41770492859599997a003e2681e7d955">alu_signal</a> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l03240"></a>03240
|
<a name="l03241"></a>03241 <span class="vhdlkeyword">end</span>
|
<a name="l03241"></a>03241 <span class="keyword">//V undefined: unchanged</span>
|
<a name="l03242"></a>03242 <span class="keyword">// division overflow: divu, divs</span>
|
<a name="l03242"></a>03242 <span class="keyword">//Z</span>
|
<a name="l03243"></a>03243 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1000</span> && <a class="code" href="classalu.html#a8d11b113e74362e74035541da1b0a02e">div_overflow</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
<a name="l03243"></a>03243 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] & <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">`Z</a><span class="vhdlchar"></span>;
|
<a name="l03244"></a>03244 <span class="keyword">/*OPTIM</span>
|
<a name="l03244"></a>03244 <span class="keyword">//C,X</span>
|
<a name="l03245"></a>03245 <span class="keyword"> else if( ((ir[15:12] == 4'b1000 && mult_div_sign == 1'b0) && (divu_quotient[31:16] != 16'd0)) ||</span>
|
<a name="l03245"></a>03245 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= (<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">8'd0</span> && <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] == <span class="vhdllogic">1'b0</span>) ? <span class="vhdllogic">1'b0</span> : <span class="vhdllogic">1'b1</span>;
|
<a name="l03246"></a>03246 <span class="keyword"> ((ir[15:12] == 4'b1000 && mult_div_sign == 1'b1) && (divs_quotient[31:16] != {16{divs_quotient[15]}}))</span>
|
<a name="l03246"></a>03246 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= (<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">8'd0</span> && <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] == <span class="vhdllogic">1'b0</span>) ? <span class="vhdllogic">1'b0</span> : <span class="vhdllogic">1'b1</span>; <span class="keyword">//=C</span>
|
<a name="l03247"></a>03247 <span class="keyword"> ) begin</span>
|
<a name="l03247"></a>03247 <span class="vhdlkeyword">end</span>
|
<a name="l03248"></a>03248 <span class="keyword"> */</span>
|
<a name="l03248"></a>03248 <span class="keyword">// SWAP</span>
|
<a name="l03249"></a>03249 <span class="keyword">// X not affected</span>
|
<a name="l03249"></a>03249 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">6'b1000_01</span> ) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> = { <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>], <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">16</span>] };
|
<a name="l03250"></a>03250 <span class="keyword">// C cleared</span>
|
<a name="l03250"></a>03250 <span class="keyword">// EXT byte to word</span>
|
<a name="l03251"></a>03251 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <span class="vhdllogic">1'b0</span>;
|
<a name="l03251"></a>03251 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">6'b1000_10</span> ) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> = { <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">16</span>], {<span class="vhdllogic">8</span>{<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>]}}, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] };
|
<a name="l03252"></a>03252 <span class="keyword">// V set</span>
|
<a name="l03252"></a>03252 <span class="keyword">// EXT word to long</span>
|
<a name="l03253"></a>03253 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b1</span>;
|
<a name="l03253"></a>03253 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">6'b1000_11</span> ) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> = { {<span class="vhdllogic">16</span>{<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>]}}, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] };
|
<a name="l03254"></a>03254 <span class="keyword">// Z,N undefined: cleared and set</span>
|
<a name="l03254"></a>03254
|
<a name="l03255"></a>03255 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= <span class="vhdllogic">1'b0</span>;
|
<a name="l03255"></a>03255 <span class="keyword">// N set if negative else clear</span>
|
<a name="l03256"></a>03256 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= <span class="vhdllogic">1'b1</span>;
|
<a name="l03256"></a>03256 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
<a name="l03257"></a>03257
|
<a name="l03257"></a>03257
|
<a name="l03258"></a>03258 <span class="keyword">// set trap</span>
|
<a name="l03258"></a>03258 <span class="keyword">// CLR,NOT,SWAP,EXT</span>
|
<a name="l03259"></a>03259 <a class="code" href="classalu.html#a41770492859599997a003e2681e7d955">alu_signal</a> <= <span class="vhdllogic">1'b1</span>;
|
<a name="l03259"></a>03259 <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0010</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0110</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">6'b1000_01</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">7</span>] == <span class="vhdllogic">5'b1000_1</span> ) <span class="vhdlkeyword">begin</span>
|
<a name="l03260"></a>03260 <span class="vhdlkeyword">end</span>
|
<a name="l03260"></a>03260 <span class="keyword">// X not affected</span>
|
<a name="l03261"></a>03261 <span class="keyword">// division</span>
|
<a name="l03261"></a>03261 <span class="keyword">// C,V cleared</span>
|
<a name="l03262"></a>03262 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1000</span> ) <span class="vhdlkeyword">begin</span>
|
<a name="l03262"></a>03262 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <span class="vhdllogic">1'b0</span>;
|
<a name="l03263"></a>03263 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <= {<a class="code" href="classalu.html#ad32bb10563baa2d2d78c2a23e8f2219e">div_remainder</a>, <a class="code" href="classalu.html#af65ee78a38f09889c3b8c9efc759f559">div_quotient</a>};
|
<a name="l03263"></a>03263 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>;
|
<a name="l03264"></a>03264
|
<a name="l03264"></a>03264 <span class="keyword">// Z set</span>
|
<a name="l03265"></a>03265 <span class="keyword">// X not affected</span>
|
<a name="l03265"></a>03265 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">`Z</a><span class="vhdlchar"></span>;
|
<a name="l03266"></a>03266 <span class="keyword">// C cleared</span>
|
<a name="l03266"></a>03266 <span class="vhdlkeyword">end</span>
|
<a name="l03267"></a>03267 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <span class="vhdllogic">1'b0</span>;
|
<a name="l03267"></a>03267 <span class="keyword">// NEGX</span>
|
<a name="l03268"></a>03268 <span class="keyword">// V cleared</span>
|
<a name="l03268"></a>03268 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0000</span> ) <span class="vhdlkeyword">begin</span>
|
<a name="l03269"></a>03269 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>;
|
<a name="l03269"></a>03269 <span class="keyword">// C set if borrow</span>
|
<a name="l03270"></a>03270 <span class="keyword">// Z</span>
|
<a name="l03270"></a>03270 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> | <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
<a name="l03271"></a>03271 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= (<a class="code" href="classalu.html#af65ee78a38f09889c3b8c9efc759f559">div_quotient</a> == <span class="vhdllogic">16'b0</span>);
|
<a name="l03271"></a>03271 <span class="keyword">// X=C</span>
|
<a name="l03272"></a>03272 <span class="keyword">// N</span>
|
<a name="l03272"></a>03272 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> | <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
<a name="l03273"></a>03273 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= (<a class="code" href="classalu.html#af65ee78a38f09889c3b8c9efc759f559">div_quotient</a>[<span class="vhdllogic">15</span>] == <span class="vhdllogic">1'b1</span>);
|
<a name="l03273"></a>03273 <span class="keyword">// V set if overflow</span>
|
<a name="l03274"></a>03274
|
<a name="l03274"></a>03274 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
<a name="l03275"></a>03275 <span class="keyword">// set trap</span>
|
<a name="l03275"></a>03275 <span class="keyword">// Z cleared if nonzero else unchanged</span>
|
<a name="l03276"></a>03276 <a class="code" href="classalu.html#a41770492859599997a003e2681e7d955">alu_signal</a> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l03276"></a>03276 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] & <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">`Z</a><span class="vhdlchar"></span>;
|
<a name="l03277"></a>03277 <span class="vhdlkeyword">end</span>
|
<a name="l03277"></a>03277 <span class="vhdlkeyword">end</span>
|
<a name="l03278"></a>03278 <span class="keyword">// multiplication</span>
|
<a name="l03278"></a>03278 <span class="keyword">// NEG</span>
|
<a name="l03279"></a>03279 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1100</span> ) <span class="vhdlkeyword">begin</span>
|
<a name="l03279"></a>03279 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0100</span> ) <span class="vhdlkeyword">begin</span>
|
<a name="l03280"></a>03280 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#aff5530027f36561324e060e703004b6b">mult_result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
<a name="l03280"></a>03280 <span class="keyword">// C clear if zero else set</span>
|
<a name="l03281"></a>03281
|
<a name="l03281"></a>03281 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> | <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
<a name="l03282"></a>03282 <span class="keyword">// X not affected</span>
|
<a name="l03282"></a>03282 <span class="keyword">// X=C</span>
|
<a name="l03283"></a>03283 <span class="keyword">// C cleared</span>
|
<a name="l03283"></a>03283 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> | <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
<a name="l03284"></a>03284 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <span class="vhdllogic">1'b0</span>;
|
<a name="l03284"></a>03284 <span class="keyword">// V set if overflow</span>
|
<a name="l03285"></a>03285 <span class="keyword">// V cleared</span>
|
<a name="l03285"></a>03285 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
<a name="l03286"></a>03286 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>;
|
<a name="l03286"></a>03286 <span class="keyword">// Z set if zero else clear</span>
|
<a name="l03287"></a>03287 <span class="keyword">// Z</span>
|
<a name="l03287"></a>03287 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">`Z</a><span class="vhdlchar"></span>;
|
<a name="l03288"></a>03288 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= (<a class="code" href="classalu.html#aff5530027f36561324e060e703004b6b">mult_result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">32'b0</span>);
|
<a name="l03288"></a>03288 <span class="vhdlkeyword">end</span>
|
<a name="l03289"></a>03289 <span class="keyword">// N</span>
|
<a name="l03289"></a>03289 <span class="vhdlkeyword">end</span>
|
<a name="l03290"></a>03290 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= (<a class="code" href="classalu.html#aff5530027f36561324e060e703004b6b">mult_result</a>[<span class="vhdllogic">31</span>] == <span class="vhdllogic">1'b1</span>);
|
<a name="l03290"></a>03290
|
<a name="l03291"></a>03291
|
<a name="l03291"></a>03291
|
<a name="l03292"></a>03292 <span class="keyword">// set trap</span>
|
<a name="l03292"></a>03292 <a class="code" href="ao68000_8v.html#a32c0e163ff437b07e40593ab59e42fe3">`ALU_SIMPLE_LONG_ADD</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
<a name="l03293"></a>03293 <a class="code" href="classalu.html#a41770492859599997a003e2681e7d955">alu_signal</a> <= <span class="vhdllogic">1'b0</span>;
|
<a name="l03293"></a>03293 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] + <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
<a name="l03294"></a>03294 <span class="vhdlkeyword">end</span>
|
<a name="l03294"></a>03294
|
<a name="l03295"></a>03295 <span class="vhdlkeyword">end</span>
|
<a name="l03295"></a>03295 <span class="keyword">// CCR not affected</span>
|
<a name="l03296"></a>03296
|
<a name="l03296"></a>03296 <span class="vhdlkeyword">end</span>
|
<a name="l03297"></a>03297
|
<a name="l03297"></a>03297
|
<a name="l03298"></a>03298 <a class="code" href="ao68000_8v.html#a14b85ce3e5b4ede3b2c4e89f420c8c3c">`ALU_BCHG_BCLR_BSET_BTST</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span> <span class="keyword">// 97 LE</span>
|
<a name="l03298"></a>03298 <a class="code" href="ao68000_8v.html#aea6fee15f3d775b1a8d262490203c713">`ALU_SIMPLE_LONG_SUB</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
<a name="l03299"></a>03299 <span class="keyword">// byte</span>
|
<a name="l03299"></a>03299 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] - <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
<a name="l03300"></a>03300 <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b000</span> ) <span class="vhdlkeyword">begin</span>
|
<a name="l03300"></a>03300
|
<a name="l03301"></a>03301 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= ~(<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[ <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] ]);
|
<a name="l03301"></a>03301 <span class="keyword">// CCR not affected</span>
|
<a name="l03302"></a>03302 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>;
|
<a name="l03302"></a>03302 <span class="vhdlkeyword">end</span>
|
<a name="l03303"></a>03303 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[ <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] ] = (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b01</span>) ? ~(<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[ <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] ]) : (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b10</span>) ? <span class="vhdllogic">1'b0</span> : <span class="vhdllogic">1'b1</span>;
|
<a name="l03303"></a>03303
|
<a name="l03304"></a>03304 <span class="vhdlkeyword">end</span>
|
<a name="l03304"></a>03304 <a class="code" href="ao68000_8v.html#a5083d98f4b785fe7af85ba1114f678ff">`ALU_MOVE_TO_CCR_SR_RTE_RTR_STOP_LOGIC_TO_CCR_SR</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
<a name="l03305"></a>03305 <span class="keyword">// long</span>
|
<a name="l03305"></a>03305
|
<a name="l03306"></a>03306 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b000</span> ) <span class="vhdlkeyword">begin</span>
|
<a name="l03306"></a>03306 <span class="keyword">// MOVE TO SR,RTE,STOP,ORI to SR,ANDI to SR,EORI to SR</span>
|
<a name="l03307"></a>03307 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= ~(<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[ <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">0</span>] ]);
|
<a name="l03307"></a>03307 <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">8'b0100_0110</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0100_1110_0111_0011</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0100_1110_0111_0010</span> ||
|
<a name="l03308"></a>03308 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>;
|
<a name="l03308"></a>03308 <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_000_0_01_111100</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_001_0_01_111100</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_101_0_01_111100</span>
|
<a name="l03309"></a>03309 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[ <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">0</span>] ] = (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b01</span>) ? ~(<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[ <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">0</span>] ]) : (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b10</span>) ? <span class="vhdllogic">1'b0</span> : <span class="vhdllogic">1'b1</span>;
|
<a name="l03309"></a>03309 ) <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a> <= { <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>], <span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">13</span>], <span class="vhdllogic">2'b0</span>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">10</span>:<span class="vhdllogic">8</span>], <span class="vhdllogic">3'b0</span>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">0</span>] };
|
<a name="l03310"></a>03310 <span class="vhdlkeyword">end</span>
|
<a name="l03310"></a>03310 <span class="keyword">// MOVE TO CCR,RTR,ORI to CCR,ANDI to CCR,EORI to CCR</span>
|
<a name="l03311"></a>03311
|
<a name="l03311"></a>03311 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">8'b0100_0100</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0100_1110_0111_0111</span> ||
|
<a name="l03312"></a>03312 <span class="keyword">// C,V,N,X not affected</span>
|
<a name="l03312"></a>03312 <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_000_0_00_111100</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_001_0_00_111100</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_101_0_00_111100</span>
|
<a name="l03313"></a>03313 <span class="vhdlkeyword">end</span>
|
<a name="l03313"></a>03313 ) <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a> <= { <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">8</span>], <span class="vhdllogic">3'b0</span>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">0</span>] };
|
<a name="l03314"></a>03314
|
<a name="l03314"></a>03314 <span class="vhdlkeyword">end</span>
|
<a name="l03315"></a>03315 <a class="code" href="ao68000_8v.html#ac7de3ab6c8eec4381bde5e4f61b45761">`ALU_TAS</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
<a name="l03315"></a>03315
|
<a name="l03316"></a>03316 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <= { <span class="vhdllogic">1'b1</span>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">6</span>:<span class="vhdllogic">0</span>] };
|
<a name="l03316"></a>03316 <a class="code" href="ao68000_8v.html#ab6d6f774c41848f9c33c7b393620be2d">`ALU_SIMPLE_MOVE</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
<a name="l03317"></a>03317
|
<a name="l03317"></a>03317 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>;
|
<a name="l03318"></a>03318 <span class="keyword">// X not affected</span>
|
<a name="l03318"></a>03318
|
<a name="l03319"></a>03319 <span class="keyword">// C cleared</span>
|
<a name="l03319"></a>03319 <span class="keyword">// CCR not affected</span>
|
<a name="l03320"></a>03320 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <span class="vhdllogic">1'b0</span>;
|
<a name="l03320"></a>03320 <span class="vhdlkeyword">end</span>
|
<a name="l03321"></a>03321 <span class="keyword">// V cleared</span>
|
<a name="l03321"></a>03321
|
<a name="l03322"></a>03322 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>;
|
<a name="l03322"></a>03322 <a class="code" href="ao68000_8v.html#ac439a8b79bd4b213f0f33172bd5e5a73">`ALU_LINK_MOVE</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
<a name="l03323"></a>03323
|
<a name="l03323"></a>03323 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">3'b111</span>) <span class="vhdlkeyword">begin</span>
|
<a name="l03324"></a>03324 <span class="keyword">// N set</span>
|
<a name="l03324"></a>03324 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a> - <span class="vhdllogic">32'd4</span>;
|
<a name="l03325"></a>03325 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= (<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>] == <span class="vhdllogic">1'b1</span>);
|
<a name="l03325"></a>03325 <span class="vhdlkeyword">end</span>
|
<a name="l03326"></a>03326 <span class="keyword">// Z set</span>
|
<a name="l03326"></a>03326 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
<a name="l03327"></a>03327 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= (<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">8'b0</span>);
|
<a name="l03327"></a>03327 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>;
|
<a name="l03328"></a>03328 <span class="vhdlkeyword">end</span>
|
<a name="l03328"></a>03328 <span class="vhdlkeyword">end</span>
|
<a name="l03329"></a>03329
|
<a name="l03329"></a>03329
|
<a name="l03330"></a>03330
|
<a name="l03330"></a>03330 <span class="keyword">// CCR not affected</span>
|
<a name="l03331"></a>03331 <a class="code" href="ao68000_8v.html#a07c7e53af3f4995a167966ba18c2728f">`ALU_NEGX_CLR_NEG_NOT_NBCD_SWAP_EXT</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
<a name="l03331"></a>03331 <span class="vhdlkeyword">end</span>
|
<a name="l03332"></a>03332 <span class="keyword">// NEGX / CLR / NEG / NOT</span>
|
<a name="l03332"></a>03332
|
<a name="l03333"></a>03333 <span class="vhdlkeyword">if</span> ((<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0000</span>) || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0010</span>) || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0100</span>) || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0110</span>))
|
<a name="l03333"></a>03333 <span class="vhdlkeyword">endcase</span>
|
<a name="l03334"></a>03334 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> = <span class="vhdllogic">32'b0</span> - (<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] & {<span class="vhdllogic">32</span>{<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">10</span>] | ~<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">9</span>]}}) - ((<a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] & ~<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">10</span>] & ~<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">9</span>]) | (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">10</span>] & <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">9</span>]));
|
<a name="l03334"></a>03334 <span class="vhdlkeyword">end</span>
|
<a name="l03335"></a>03335 <span class="keyword">/*OPTIM</span>
|
<a name="l03335"></a>03335 <span class="vhdlkeyword">end</span>
|
<a name="l03336"></a>03336 <span class="keyword"> // NEGX</span>
|
<a name="l03336"></a>03336
|
<a name="l03337"></a>03337 <span class="keyword"> if( ir[11:8] == 4'b0000 ) result = 32'b0 - operand1[31:0] - sr[4];</span>
|
<a name="l03337"></a>03337 <span class="vhdlkeyword">endmodule</span>
|
<a name="l03338"></a>03338 <span class="keyword"> // CLR</span>
|
<a name="l03338"></a>03338
|
<a name="l03339"></a>03339 <span class="keyword"> else if (ir[11:8] == 4'b0010) result = 32'b0;</span>
|
<a name="l03339"></a>03339 <span class="keyword">/***********************************************************************************************************************</span>
|
<a name="l03340"></a>03340 <span class="keyword"> // NEG</span>
|
<a name="l03340"></a>03340 <span class="keyword"> Microcode branch</span>
|
<a name="l03341"></a>03341 <span class="keyword"> else if( ir[11:8] == 4'b0100 ) result = 32'b0 - operand1[31:0];</span>
|
<a name="l03341"></a>03341 <span class="keyword"> ***********************************************************************************************************************/</span>
|
<a name="l03342"></a>03342 <span class="keyword"> // NOT</span>
|
<a name="l03342"></a>03342
|
<a name="l03343"></a>03343 <span class="keyword"> else if( ir[11:8] == 4'b0110 ) result = ~operand1[31:0];</span>
|
<a name="l03343"></a>03343
|
<a name="l03344"></a>03344 <span class="keyword"> */</span>
|
<a name="l03352"></a><a class="code" href="classmicrocode__branch.html">03352</a> <span class="vhdlkeyword">module</span> <a class="code" href="classmicrocode__branch.html">microcode_branch</a>(
|
<a name="l03345"></a>03345 <span class="keyword">// NBCD</span>
|
<a name="l03353"></a><a class="code" href="classmicrocode__branch.html#aa97186c6a6c8f8229219bceb1750b753">03353</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmicrocode__branch.html#aa97186c6a6c8f8229219bceb1750b753">clock</a>,
|
<a name="l03346"></a>03346 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">6'b1000_00</span> ) <span class="vhdlkeyword">begin</span>
|
<a name="l03354"></a><a class="code" href="classmicrocode__branch.html#a446d61eb34eb480a38661d473bf25fd4">03354</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmicrocode__branch.html#a446d61eb34eb480a38661d473bf25fd4">reset_n</a>,
|
<a name="l03347"></a>03347
|
<a name="l03355"></a>03355
|
<a name="l03348"></a>03348 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] = <span class="vhdllogic">5'd25</span> - <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>];
|
<a name="l03356"></a><a class="code" href="classmicrocode__branch.html#a42e8abed644ad88712e3f12b88119b93">03356</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">4</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#a42e8abed644ad88712e3f12b88119b93">movem_loop</a>,
|
<a name="l03349"></a>03349 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] = (<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] > <span class="vhdllogic">4'd9</span>) ? (<span class="vhdllogic">5'd24</span> - <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>]) : (<span class="vhdllogic">5'd25</span> - <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>]);
|
<a name="l03357"></a><a class="code" href="classmicrocode__branch.html#abad84561ae17084ceb7d2a623b446a14">03357</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#abad84561ae17084ceb7d2a623b446a14">movem_reg</a>,
|
<a name="l03350"></a>03350
|
<a name="l03358"></a><a class="code" href="classmicrocode__branch.html#a44a7fbf19a4641fb5007ba59ea7867b2">03358</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#a44a7fbf19a4641fb5007ba59ea7867b2">operand2</a>,
|
<a name="l03351"></a>03351 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] == <span class="vhdllogic">1'b0</span> && <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">4'd9</span> && <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">4'd9</span>) <span class="vhdlkeyword">begin</span>
|
<a name="l03359"></a><a class="code" href="classmicrocode__branch.html#ae0d0b0c347c453aed25820eb4d5ede60">03359</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmicrocode__branch.html#ae0d0b0c347c453aed25820eb4d5ede60">alu_signal</a>,
|
<a name="l03352"></a>03352 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] = <span class="vhdllogic">4'd0</span>;
|
<a name="l03360"></a><a class="code" href="classmicrocode__branch.html#a6965faa1f8f535384a68703714d67d41">03360</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmicrocode__branch.html#a6965faa1f8f535384a68703714d67d41">alu_mult_div_ready</a>,
|
<a name="l03353"></a>03353 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] = <span class="vhdllogic">4'd0</span>;
|
<a name="l03361"></a><a class="code" href="classmicrocode__branch.html#a812465227c1ce82d3a227a04a5cc9a89">03361</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmicrocode__branch.html#a812465227c1ce82d3a227a04a5cc9a89">condition</a>,
|
<a name="l03354"></a>03354 <span class="vhdlkeyword">end</span>
|
<a name="l03362"></a><a class="code" href="classmicrocode__branch.html#a07ec962ad743b1c4988f5b0f6332f393">03362</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#a07ec962ad743b1c4988f5b0f6332f393">result</a>,
|
<a name="l03355"></a>03355 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] == <span class="vhdllogic">1'b0</span> && (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">4'd9</span> || <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">4'd15</span>)) <span class="vhdlkeyword">begin</span>
|
<a name="l03363"></a><a class="code" href="classmicrocode__branch.html#a8e3878b37a15cbe9f5ac25d9d0c50ff5">03363</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmicrocode__branch.html#a8e3878b37a15cbe9f5ac25d9d0c50ff5">overflow</a>,
|
<a name="l03356"></a>03356 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] = <span class="vhdllogic">4'd0</span>;
|
<a name="l03364"></a><a class="code" href="classmicrocode__branch.html#a76527514b31cb7de3a0f1f3a9b4fa039">03364</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmicrocode__branch.html#a76527514b31cb7de3a0f1f3a9b4fa039">stop_flag</a>,
|
<a name="l03357"></a>03357 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] = <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] + <span class="vhdllogic">4'd1</span>;
|
<a name="l03365"></a><a class="code" href="classmicrocode__branch.html#a66d21fc86ad1b8a3b3f72d78b9c96aef">03365</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#a66d21fc86ad1b8a3b3f72d78b9c96aef">ir</a>,
|
<a name="l03358"></a>03358 <span class="vhdlkeyword">end</span>
|
<a name="l03366"></a><a class="code" href="classmicrocode__branch.html#a96f331edcf8cb8bb65f80139b5248456">03366</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#a96f331edcf8cb8bb65f80139b5248456">decoder_trap</a>,
|
<a name="l03359"></a>03359 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
<a name="l03367"></a><a class="code" href="classmicrocode__branch.html#a909c52e94961a97edb894efc59ecae40">03367</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmicrocode__branch.html#a909c52e94961a97edb894efc59ecae40">trace_flag</a>,
|
<a name="l03360"></a>03360 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] + <span class="vhdllogic">4'd1</span>;
|
<a name="l03368"></a><a class="code" href="classmicrocode__branch.html#a1520537038c18470f595c0d2858431f3">03368</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmicrocode__branch.html#a1520537038c18470f595c0d2858431f3">group_0_flag</a>,
|
<a name="l03361"></a>03361 <span class="vhdlkeyword">end</span>
|
<a name="l03369"></a><a class="code" href="classmicrocode__branch.html#a474cb146bed7bdde681694c3f06a1106">03369</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#a474cb146bed7bdde681694c3f06a1106">interrupt_mask</a>,
|
<a name="l03362"></a>03362
|
<a name="l03370"></a>03370
|
<a name="l03363"></a>03363 <span class="keyword">//V undefined: unchanged</span>
|
<a name="l03371"></a><a class="code" href="classmicrocode__branch.html#a029e3e9219332863900f71a52816c7ac">03371</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#a029e3e9219332863900f71a52816c7ac">load_ea</a>,
|
<a name="l03364"></a>03364 <span class="keyword">//Z</span>
|
<a name="l03372"></a><a class="code" href="classmicrocode__branch.html#acd130168642a726f7de176682a42e3ad">03372</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#acd130168642a726f7de176682a42e3ad">perform_ea_read</a>,
|
<a name="l03365"></a>03365 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] & <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">`Z</a><span class="vhdlchar"></span>;
|
<a name="l03373"></a><a class="code" href="classmicrocode__branch.html#a6f20353ec8aea573354892ebe79e4aec">03373</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#a6f20353ec8aea573354892ebe79e4aec">perform_ea_write</a>,
|
<a name="l03366"></a>03366 <span class="keyword">//C,X</span>
|
<a name="l03374"></a><a class="code" href="classmicrocode__branch.html#a2bf9f1fb5125818e8eb47aa043e0a393">03374</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#a2bf9f1fb5125818e8eb47aa043e0a393">save_ea</a>,
|
<a name="l03367"></a>03367 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= (<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">8'd0</span> && <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] == <span class="vhdllogic">1'b0</span>) ? <span class="vhdllogic">1'b0</span> : <span class="vhdllogic">1'b1</span>;
|
<a name="l03375"></a><a class="code" href="classmicrocode__branch.html#a1493bf14db63cdb7d2ce8b2410b1c33b">03375</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#a1493bf14db63cdb7d2ce8b2410b1c33b">decoder_micropc</a>,
|
<a name="l03368"></a>03368 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= (<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">8'd0</span> && <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] == <span class="vhdllogic">1'b0</span>) ? <span class="vhdllogic">1'b0</span> : <span class="vhdllogic">1'b1</span>; <span class="keyword">//=C</span>
|
|
<a name="l03369"></a>03369 <span class="vhdlkeyword">end</span>
|
|
<a name="l03370"></a>03370 <span class="keyword">// SWAP</span>
|
|
<a name="l03371"></a>03371 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">6'b1000_01</span> ) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> = { <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>], <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">16</span>] };
|
|
<a name="l03372"></a>03372 <span class="keyword">// EXT byte to word</span>
|
|
<a name="l03373"></a>03373 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">6'b1000_10</span> ) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> = { <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">16</span>], {<span class="vhdllogic">8</span>{<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>]}}, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] };
|
|
<a name="l03374"></a>03374 <span class="keyword">// EXT word to long</span>
|
|
<a name="l03375"></a>03375 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">6'b1000_11</span> ) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> = { {<span class="vhdllogic">16</span>{<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>]}}, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] };
|
|
<a name="l03376"></a>03376
|
<a name="l03376"></a>03376
|
<a name="l03377"></a>03377 <span class="keyword">// N set if negative else clear</span>
|
<a name="l03377"></a><a class="code" href="classmicrocode__branch.html#aef8500b16e788430917ee03f003d10a9">03377</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmicrocode__branch.html#aef8500b16e788430917ee03f003d10a9">prefetch_ir_valid_32</a>,
|
<a name="l03378"></a>03378 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
<a name="l03378"></a><a class="code" href="classmicrocode__branch.html#ae627b4cdc5e73300a5166eb7636468ea">03378</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmicrocode__branch.html#ae627b4cdc5e73300a5166eb7636468ea">prefetch_ir_valid</a>,
|
<a name="l03379"></a>03379
|
<a name="l03379"></a><a class="code" href="classmicrocode__branch.html#abc45eb66161b645c69d4b6ad6457ff31">03379</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmicrocode__branch.html#abc45eb66161b645c69d4b6ad6457ff31">jmp_address_trap</a>,
|
<a name="l03380"></a>03380 <span class="keyword">// CLR,NOT,SWAP,EXT</span>
|
<a name="l03380"></a><a class="code" href="classmicrocode__branch.html#a9ba804e0f049ed633f01c611e248a587">03380</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmicrocode__branch.html#a9ba804e0f049ed633f01c611e248a587">jmp_bus_trap</a>,
|
<a name="l03381"></a>03381 <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0010</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0110</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">6'b1000_01</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">7</span>] == <span class="vhdllogic">5'b1000_1</span> ) <span class="vhdlkeyword">begin</span>
|
<a name="l03381"></a><a class="code" href="classmicrocode__branch.html#ab3eb1598fd8ff755ee7811485c4b9849">03381</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmicrocode__branch.html#ab3eb1598fd8ff755ee7811485c4b9849">finished</a>,
|
<a name="l03382"></a>03382 <span class="keyword">// X not affected</span>
|
<a name="l03382"></a>03382
|
<a name="l03383"></a>03383 <span class="keyword">// C,V cleared</span>
|
<a name="l03383"></a><a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">03383</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a>,
|
<a name="l03384"></a>03384 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <span class="vhdllogic">1'b0</span>;
|
<a name="l03384"></a><a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">03384</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a>,
|
<a name="l03385"></a>03385 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>;
|
<a name="l03385"></a><a class="code" href="classmicrocode__branch.html#a53df336945e1387fada5822142621f2f">03385</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#a53df336945e1387fada5822142621f2f">micro_pc</a>
|
<a name="l03386"></a>03386 <span class="keyword">// Z set</span>
|
<a name="l03386"></a>03386 );
|
<a name="l03387"></a>03387 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">`Z</a><span class="vhdlchar"></span>;
|
<a name="l03387"></a>03387
|
<a name="l03388"></a>03388 <span class="vhdlkeyword">end</span>
|
<a name="l03388"></a><a class="code" href="classmicrocode__branch.html#ad9bc2cb9966990b791c16ae418be756c">03388</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#ad9bc2cb9966990b791c16ae418be756c">micro_pc_0</a> = <span class="vhdllogic">9'd0</span>;
|
<a name="l03389"></a>03389 <span class="keyword">// NEGX</span>
|
<a name="l03389"></a><a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">03389</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a>;
|
<a name="l03390"></a>03390 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0000</span> ) <span class="vhdlkeyword">begin</span>
|
<a name="l03390"></a><a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">03390</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a>;
|
<a name="l03391"></a>03391 <span class="keyword">// C set if borrow</span>
|
<a name="l03391"></a><a class="code" href="classmicrocode__branch.html#a8d7713b0340f69c7eae6282373e3bf7b">03391</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#a8d7713b0340f69c7eae6282373e3bf7b">micro_pc_3</a>;
|
<a name="l03392"></a>03392 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> | <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
<a name="l03392"></a>03392
|
<a name="l03393"></a>03393 <span class="keyword">// X=C</span>
|
<a name="l03393"></a>03393 <span class="vhdlkeyword">assign</span> <a class="code" href="classmicrocode__branch.html#a53df336945e1387fada5822142621f2f">micro_pc</a> =
|
<a name="l03394"></a>03394 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> | <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
<a name="l03394"></a>03394 (<a class="code" href="classmicrocode__branch.html#a446d61eb34eb480a38661d473bf25fd4">reset_n</a> == <span class="vhdllogic">1'b0</span>) ? <span class="vhdllogic">9'd0</span> :
|
<a name="l03395"></a>03395 <span class="keyword">// V set if overflow</span>
|
<a name="l03395"></a>03395 (<a class="code" href="classmicrocode__branch.html#abc45eb66161b645c69d4b6ad6457ff31">jmp_address_trap</a> == <span class="vhdllogic">1'b1</span> || <a class="code" href="classmicrocode__branch.html#a9ba804e0f049ed633f01c611e248a587">jmp_bus_trap</a> == <span class="vhdllogic">1'b1</span>) ? <a class="code" href="ao68000_8v.html#ada4b6f4df06a5dcac3ec15d4c8f4d31e">`MICROPC_ADDRESS_BUS_TRAP</a><span class="vhdlchar"></span> :
|
<a name="l03396"></a>03396 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
<a name="l03396"></a>03396 ( (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#abdfc603db0ea3694052298e85fb6efad">`BRANCH_movem_loop</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a42e8abed644ad88712e3f12b88119b93">movem_loop</a> == <span class="vhdllogic">5'b10000</span>) ||
|
<a name="l03397"></a>03397 <span class="keyword">// Z cleared if nonzero else unchanged</span>
|
<a name="l03397"></a>03397 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#acc65cf5ec49ce78ecf98c956cd2de769">`BRANCH_movem_reg</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#abad84561ae17084ceb7d2a623b446a14">movem_reg</a>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">0</span>) ||
|
<a name="l03398"></a>03398 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] & <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">`Z</a><span class="vhdlchar"></span>;
|
<a name="l03398"></a>03398 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#aa0b5846a5e98be60da75608078377571">`BRANCH_operand2</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a44a7fbf19a4641fb5007ba59ea7867b2">operand2</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b0</span>) ||
|
<a name="l03399"></a>03399 <span class="vhdlkeyword">end</span>
|
<a name="l03399"></a>03399 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a3db021156e8171951f6b91c78bbb7e1f">`BRANCH_alu_signal</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#ae0d0b0c347c453aed25820eb4d5ede60">alu_signal</a> == <span class="vhdllogic">1'b0</span>) ||
|
<a name="l03400"></a>03400 <span class="keyword">// NEG</span>
|
<a name="l03400"></a>03400 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a62fe8e5939da15f9f391886fe174183a">`BRANCH_alu_mult_div_ready</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a6965faa1f8f535384a68703714d67d41">alu_mult_div_ready</a> == <span class="vhdllogic">1'b1</span>) ||
|
<a name="l03401"></a>03401 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0100</span> ) <span class="vhdlkeyword">begin</span>
|
<a name="l03401"></a>03401 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#af3158a11a9fc793d4aeead4195871507">`BRANCH_condition_0</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a812465227c1ce82d3a227a04a5cc9a89">condition</a> == <span class="vhdllogic">1'b0</span>) ||
|
<a name="l03402"></a>03402 <span class="keyword">// C clear if zero else set</span>
|
<a name="l03402"></a>03402 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a48d5a0127f3bc738b8503c0713b9fba9">`BRANCH_condition_1</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a812465227c1ce82d3a227a04a5cc9a89">condition</a> == <span class="vhdllogic">1'b1</span>) ||
|
<a name="l03403"></a>03403 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> | <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
<a name="l03403"></a>03403 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a0cbdc7b4e718d5cc690b435995bb7708">`BRANCH_result</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a07ec962ad743b1c4988f5b0f6332f393">result</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'hFFFF</span>) ||
|
<a name="l03404"></a>03404 <span class="keyword">// X=C</span>
|
<a name="l03404"></a>03404 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a3861f0d4bd11e996bda23577348e86f7">`BRANCH_V</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a8e3878b37a15cbe9f5ac25d9d0c50ff5">overflow</a> == <span class="vhdllogic">1'b0</span>) ||
|
<a name="l03405"></a>03405 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> | <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
<a name="l03405"></a>03405 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a5fb736520363d5359408ed4af63c6125">`BRANCH_movep_16</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a66d21fc86ad1b8a3b3f72d78b9c96aef">ir</a>[<span class="vhdllogic">6</span>] == <span class="vhdllogic">1'b0</span>) ||
|
<a name="l03406"></a>03406 <span class="keyword">// V set if overflow</span>
|
<a name="l03406"></a>03406 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a79ce1f7b2aa4e141d52316a04977ee60">`BRANCH_stop_flag_wait_ir_decode</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a76527514b31cb7de3a0f1f3a9b4fa039">stop_flag</a> == <span class="vhdllogic">1'b1</span>) ||
|
<a name="l03407"></a>03407 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
<a name="l03407"></a>03407 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a719e200160515b706ebab9fe1e18c8c7">`BRANCH_ir</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a66d21fc86ad1b8a3b3f72d78b9c96aef">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] != <span class="vhdllogic">8'b0</span>) ||
|
<a name="l03408"></a>03408 <span class="keyword">// Z set if zero else clear</span>
|
<a name="l03408"></a>03408 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#af396200d0e5941fe60e8d960f2e3aa91">`BRANCH_trace_flag_and_interrupt</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a909c52e94961a97edb894efc59ecae40">trace_flag</a> == <span class="vhdllogic">1'b0</span> && <a class="code" href="classmicrocode__branch.html#a474cb146bed7bdde681694c3f06a1106">interrupt_mask</a> != <span class="vhdllogic">3'b000</span>) ||
|
<a name="l03409"></a>03409 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">`Z</a><span class="vhdlchar"></span>;
|
<a name="l03409"></a>03409 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a63f967b1bbe9ad356e3ccbbb2924e03f">`BRANCH_group_0_flag</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a1520537038c18470f595c0d2858431f3">group_0_flag</a> == <span class="vhdllogic">1'b0</span>)
|
<a name="l03410"></a>03410 <span class="vhdlkeyword">end</span>
|
<a name="l03410"></a>03410 ) ? <a class="code" href="classmicrocode__branch.html#ad9bc2cb9966990b791c16ae418be756c">micro_pc_0</a> + { <span class="vhdllogic">5'd0</span>, <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> } :
|
<a name="l03411"></a>03411 <span class="vhdlkeyword">end</span>
|
<a name="l03411"></a>03411 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a79ce1f7b2aa4e141d52316a04977ee60">`BRANCH_stop_flag_wait_ir_decode</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#ae627b4cdc5e73300a5166eb7636468ea">prefetch_ir_valid</a> == <span class="vhdllogic">1'b1</span> && <a class="code" href="classmicrocode__branch.html#a96f331edcf8cb8bb65f80139b5248456">decoder_trap</a> == <span class="vhdllogic">8'd0</span>) ? <a class="code" href="classmicrocode__branch.html#a1493bf14db63cdb7d2ce8b2410b1c33b">decoder_micropc</a> :
|
<a name="l03412"></a>03412
|
<a name="l03412"></a>03412 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#af396200d0e5941fe60e8d960f2e3aa91">`BRANCH_trace_flag_and_interrupt</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a909c52e94961a97edb894efc59ecae40">trace_flag</a> == <span class="vhdllogic">1'b0</span> && <a class="code" href="classmicrocode__branch.html#a474cb146bed7bdde681694c3f06a1106">interrupt_mask</a> == <span class="vhdllogic">3'b000</span>) ? <a class="code" href="ao68000_8v.html#a1e7ad8f4b421f72f5bdea07bef35f864">`MICROPC_MAIN_LOOP</a><span class="vhdlchar"></span> :
|
<a name="l03413"></a>03413
|
<a name="l03413"></a>03413 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a1f24f0ad71fd4d2edd6ead5ef6c3056a">`BRANCH_procedure</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a7950509479648899370516cfa0221c43">`PROCEDURE_jump_to_main_loop</a><span class="vhdlchar"></span>) ? <a class="code" href="ao68000_8v.html#a1e7ad8f4b421f72f5bdea07bef35f864">`MICROPC_MAIN_LOOP</a><span class="vhdlchar"></span> :
|
<a name="l03414"></a>03414 <a class="code" href="ao68000_8v.html#a32c0e163ff437b07e40593ab59e42fe3">`ALU_SIMPLE_LONG_ADD</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
<a name="l03414"></a>03414 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a1f24f0ad71fd4d2edd6ead5ef6c3056a">`BRANCH_procedure</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a5c7af3686fb890de6242f973de1ee549">`PROCEDURE_call_load_ea</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a029e3e9219332863900f71a52816c7ac">load_ea</a> != <span class="vhdllogic">9'd0</span>) ? <a class="code" href="classmicrocode__branch.html#a029e3e9219332863900f71a52816c7ac">load_ea</a> :
|
<a name="l03415"></a>03415 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] + <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
<a name="l03415"></a>03415 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a1f24f0ad71fd4d2edd6ead5ef6c3056a">`BRANCH_procedure</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a698b04745cbbec22896235d5cfffac43">`PROCEDURE_call_perform_ea_read</a><span class="vhdlchar"></span>) ? <a class="code" href="classmicrocode__branch.html#acd130168642a726f7de176682a42e3ad">perform_ea_read</a> :
|
<a name="l03416"></a>03416
|
<a name="l03416"></a>03416 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a1f24f0ad71fd4d2edd6ead5ef6c3056a">`BRANCH_procedure</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#aa98c954da2ac9f709907c8c593b1439e">`PROCEDURE_call_perform_ea_write</a><span class="vhdlchar"></span>) ? <a class="code" href="classmicrocode__branch.html#a6f20353ec8aea573354892ebe79e4aec">perform_ea_write</a> :
|
<a name="l03417"></a>03417 <span class="keyword">// CCR not affected</span>
|
<a name="l03417"></a>03417 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a1f24f0ad71fd4d2edd6ead5ef6c3056a">`BRANCH_procedure</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a30022c5eb1821e27dd5c70d4affbc835">`PROCEDURE_call_save_ea</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a2bf9f1fb5125818e8eb47aa043e0a393">save_ea</a> != <span class="vhdllogic">9'd0</span>) ? <a class="code" href="classmicrocode__branch.html#a2bf9f1fb5125818e8eb47aa043e0a393">save_ea</a> :
|
<a name="l03418"></a>03418 <span class="vhdlkeyword">end</span>
|
<a name="l03418"></a>03418
|
<a name="l03419"></a>03419
|
<a name="l03419"></a>03419 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a1f24f0ad71fd4d2edd6ead5ef6c3056a">`BRANCH_procedure</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a403d3720f31ad5a5895778bee758fb55">`PROCEDURE_call_read</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a029e3e9219332863900f71a52816c7ac">load_ea</a> != <span class="vhdllogic">9'd0</span>) ? <a class="code" href="classmicrocode__branch.html#a029e3e9219332863900f71a52816c7ac">load_ea</a> :
|
<a name="l03420"></a>03420 <a class="code" href="ao68000_8v.html#aea6fee15f3d775b1a8d262490203c713">`ALU_SIMPLE_LONG_SUB</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
<a name="l03420"></a>03420 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a1f24f0ad71fd4d2edd6ead5ef6c3056a">`BRANCH_procedure</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a403d3720f31ad5a5895778bee758fb55">`PROCEDURE_call_read</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a029e3e9219332863900f71a52816c7ac">load_ea</a> == <span class="vhdllogic">9'd0</span>) ? <a class="code" href="classmicrocode__branch.html#acd130168642a726f7de176682a42e3ad">perform_ea_read</a> :
|
<a name="l03421"></a>03421 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] - <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
<a name="l03421"></a>03421
|
<a name="l03422"></a>03422
|
<a name="l03422"></a>03422 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a1f24f0ad71fd4d2edd6ead5ef6c3056a">`BRANCH_procedure</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a50af2007588b7a528b934ae7672b1214">`PROCEDURE_call_write</a><span class="vhdlchar"></span>) ? <a class="code" href="classmicrocode__branch.html#a6f20353ec8aea573354892ebe79e4aec">perform_ea_write</a> :
|
<a name="l03423"></a>03423 <span class="keyword">// CCR not affected</span>
|
<a name="l03423"></a>03423
|
<a name="l03424"></a>03424 <span class="vhdlkeyword">end</span>
|
<a name="l03424"></a>03424 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a1f24f0ad71fd4d2edd6ead5ef6c3056a">`BRANCH_procedure</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a2c67cc2747b67d04684855e14c2b9fbb">`PROCEDURE_call_trap</a><span class="vhdlchar"></span>) ? <a class="code" href="ao68000_8v.html#a80e45e303a1ebe180eeb15b47454e13f">`MICROPC_TRAP_ENTRY</a><span class="vhdlchar"></span> :
|
<a name="l03425"></a>03425
|
<a name="l03425"></a>03425 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a1f24f0ad71fd4d2edd6ead5ef6c3056a">`BRANCH_procedure</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#af842761d13933777546d76bd997e7494">`PROCEDURE_return</a><span class="vhdlchar"></span>) ? <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a> :
|
<a name="l03426"></a>03426 <a class="code" href="ao68000_8v.html#a5083d98f4b785fe7af85ba1114f678ff">`ALU_MOVE_TO_CCR_SR_RTE_RTR_STOP_LOGIC_TO_CCR_SR</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
<a name="l03426"></a>03426 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a1f24f0ad71fd4d2edd6ead5ef6c3056a">`BRANCH_procedure</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#ac74b95b43e6c95ed82036002767bc22c">`PROCEDURE_interrupt_mask</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a474cb146bed7bdde681694c3f06a1106">interrupt_mask</a> == <span class="vhdllogic">3'b000</span>) ? <a class="code" href="ao68000_8v.html#a1e7ad8f4b421f72f5bdea07bef35f864">`MICROPC_MAIN_LOOP</a><span class="vhdlchar"></span> :
|
<a name="l03427"></a>03427
|
<a name="l03427"></a>03427 ( (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a1f24f0ad71fd4d2edd6ead5ef6c3056a">`BRANCH_procedure</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a26a2f20a92ff8ab6f13d6633f3c9475c">`PROCEDURE_wait_finished</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#ab3eb1598fd8ff755ee7811485c4b9849">finished</a> == <span class="vhdllogic">1'b0</span>) ||
|
<a name="l03428"></a>03428 <span class="keyword">// MOVE TO SR,RTE,STOP,ORI to SR,ANDI to SR,EORI to SR</span>
|
<a name="l03428"></a>03428 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a1f24f0ad71fd4d2edd6ead5ef6c3056a">`BRANCH_procedure</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#aa072f73b12cd178a44f47980e1bb98cb">`PROCEDURE_wait_prefetch_valid</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#ae627b4cdc5e73300a5166eb7636468ea">prefetch_ir_valid</a> == <span class="vhdllogic">1'b0</span>) ||
|
<a name="l03429"></a>03429 <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">8'b0100_0110</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0100_1110_0111_0011</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0100_1110_0111_0010</span> ||
|
<a name="l03429"></a>03429 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a1f24f0ad71fd4d2edd6ead5ef6c3056a">`BRANCH_procedure</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a0ef2adec86a42dd30d78e9d259d828fd">`PROCEDURE_wait_prefetch_valid_32</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#aef8500b16e788430917ee03f003d10a9">prefetch_ir_valid_32</a> == <span class="vhdllogic">1'b0</span>) ||
|
<a name="l03430"></a>03430 <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_000_0_01_111100</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_001_0_01_111100</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_101_0_01_111100</span>
|
<a name="l03430"></a>03430 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a79ce1f7b2aa4e141d52316a04977ee60">`BRANCH_stop_flag_wait_ir_decode</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#ae627b4cdc5e73300a5166eb7636468ea">prefetch_ir_valid</a> == <span class="vhdllogic">1'b0</span>)
|
<a name="l03431"></a>03431 ) <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a> <= { <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>], <span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">13</span>], <span class="vhdllogic">2'b0</span>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">10</span>:<span class="vhdllogic">8</span>], <span class="vhdllogic">3'b0</span>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">0</span>] };
|
<a name="l03431"></a>03431 ) ? <a class="code" href="classmicrocode__branch.html#ad9bc2cb9966990b791c16ae418be756c">micro_pc_0</a> :
|
<a name="l03432"></a>03432 <span class="keyword">// MOVE TO CCR,RTR,ORI to CCR,ANDI to CCR,EORI to CCR</span>
|
<a name="l03432"></a>03432 <a class="code" href="classmicrocode__branch.html#ad9bc2cb9966990b791c16ae418be756c">micro_pc_0</a> + <span class="vhdllogic">9'd1</span>
|
<a name="l03433"></a>03433 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">8'b0100_0100</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0100_1110_0111_0111</span> ||
|
<a name="l03433"></a>03433 ;
|
<a name="l03434"></a>03434 <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_000_0_00_111100</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_001_0_00_111100</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_101_0_00_111100</span>
|
<a name="l03434"></a>03434
|
<a name="l03435"></a>03435 ) <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a> <= { <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">8</span>], <span class="vhdllogic">3'b0</span>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">0</span>] };
|
<a name="l03435"></a><a class="code" href="classmicrocode__branch.html#a5c48a82153e9796a3913029cde0cc182">03435</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classmicrocode__branch.html#aa97186c6a6c8f8229219bceb1750b753">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classmicrocode__branch.html#a446d61eb34eb480a38661d473bf25fd4">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l03436"></a>03436 <span class="vhdlkeyword">end</span>
|
<a name="l03436"></a>03436 <span class="vhdlkeyword">if</span>(<a class="code" href="classmicrocode__branch.html#a446d61eb34eb480a38661d473bf25fd4">reset_n</a> == <span class="vhdllogic">1'b0</span>) <a class="code" href="classmicrocode__branch.html#ad9bc2cb9966990b791c16ae418be756c">micro_pc_0</a> <= <span class="vhdllogic">9'd0</span>;
|
<a name="l03437"></a>03437
|
<a name="l03437"></a>03437 <span class="vhdlkeyword">else</span> <a class="code" href="classmicrocode__branch.html#ad9bc2cb9966990b791c16ae418be756c">micro_pc_0</a> <= <a class="code" href="classmicrocode__branch.html#a53df336945e1387fada5822142621f2f">micro_pc</a>;
|
<a name="l03438"></a>03438 <a class="code" href="ao68000_8v.html#ab6d6f774c41848f9c33c7b393620be2d">`ALU_SIMPLE_MOVE</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
<a name="l03438"></a>03438 <span class="vhdlkeyword">end</span>
|
<a name="l03439"></a>03439 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>;
|
<a name="l03439"></a>03439
|
<a name="l03440"></a>03440
|
<a name="l03440"></a><a class="code" href="classmicrocode__branch.html#a4e2c393980b78c66fbb22710e14a1cbb">03440</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classmicrocode__branch.html#aa97186c6a6c8f8229219bceb1750b753">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classmicrocode__branch.html#a446d61eb34eb480a38661d473bf25fd4">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
<a name="l03441"></a>03441 <span class="keyword">// CCR not affected</span>
|
<a name="l03441"></a>03441 <span class="vhdlkeyword">if</span>(<a class="code" href="classmicrocode__branch.html#a446d61eb34eb480a38661d473bf25fd4">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
<a name="l03442"></a>03442 <span class="vhdlkeyword">end</span>
|
<a name="l03442"></a>03442 <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a> <= <span class="vhdllogic">9'd0</span>;
|
<a name="l03443"></a>03443
|
<a name="l03443"></a>03443 <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a> <= <span class="vhdllogic">9'd0</span>;
|
<a name="l03444"></a>03444 <a class="code" href="ao68000_8v.html#ac439a8b79bd4b213f0f33172bd5e5a73">`ALU_LINK_MOVE</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
<a name="l03444"></a>03444 <a class="code" href="classmicrocode__branch.html#a8d7713b0340f69c7eae6282373e3bf7b">micro_pc_3</a> <= <span class="vhdllogic">9'd0</span>;
|
<a name="l03445"></a>03445 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">3'b111</span>) <span class="vhdlkeyword">begin</span>
|
<a name="l03445"></a>03445 <span class="vhdlkeyword">end</span>
|
<a name="l03446"></a>03446 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a> - <span class="vhdllogic">32'd4</span>;
|
<a name="l03446"></a>03446 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a79ce1f7b2aa4e141d52316a04977ee60">`BRANCH_stop_flag_wait_ir_decode</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#ae627b4cdc5e73300a5166eb7636468ea">prefetch_ir_valid</a> == <span class="vhdllogic">1'b1</span> && <a class="code" href="classmicrocode__branch.html#a96f331edcf8cb8bb65f80139b5248456">decoder_trap</a> == <span class="vhdllogic">8'd0</span>)
|
<a name="l03447"></a>03447 <span class="vhdlkeyword">end</span>
|
<a name="l03447"></a>03447 <span class="vhdlkeyword">begin</span>
|
<a name="l03448"></a>03448 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
<a name="l03448"></a>03448 <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a> <= <a class="code" href="classmicrocode__branch.html#ad9bc2cb9966990b791c16ae418be756c">micro_pc_0</a> + { <span class="vhdllogic">5'd0</span>, <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> };
|
<a name="l03449"></a>03449 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>;
|
<a name="l03449"></a>03449 <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a> <= <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a>;
|
<a name="l03450"></a>03450 <span class="vhdlkeyword">end</span>
|
<a name="l03450"></a>03450 <a class="code" href="classmicrocode__branch.html#a8d7713b0340f69c7eae6282373e3bf7b">micro_pc_3</a> <= <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a>;
|
<a name="l03451"></a>03451
|
<a name="l03451"></a>03451 <span class="vhdlkeyword">end</span>
|
<a name="l03452"></a>03452 <span class="keyword">// CCR not affected</span>
|
<a name="l03452"></a>03452 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a1f24f0ad71fd4d2edd6ead5ef6c3056a">`BRANCH_procedure</a><span class="vhdlchar"></span>) <span class="vhdlkeyword">begin</span>
|
<a name="l03453"></a>03453 <span class="vhdlkeyword">end</span>
|
<a name="l03453"></a>03453 <span class="vhdlkeyword">if</span>(<a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a403d3720f31ad5a5895778bee758fb55">`PROCEDURE_call_read</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a029e3e9219332863900f71a52816c7ac">load_ea</a> != <span class="vhdllogic">9'd0</span>) <span class="vhdlkeyword">begin</span>
|
<a name="l03454"></a>03454
|
<a name="l03454"></a>03454 <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a> <= <a class="code" href="classmicrocode__branch.html#acd130168642a726f7de176682a42e3ad">perform_ea_read</a>;
|
<a name="l03455"></a>03455 <span class="vhdlkeyword">endcase</span>
|
<a name="l03455"></a>03455 <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a> <= <a class="code" href="classmicrocode__branch.html#ad9bc2cb9966990b791c16ae418be756c">micro_pc_0</a> + <span class="vhdllogic">9'd1</span>;
|
<a name="l03456"></a>03456 <span class="vhdlkeyword">end</span>
|
<a name="l03456"></a>03456 <a class="code" href="classmicrocode__branch.html#a8d7713b0340f69c7eae6282373e3bf7b">micro_pc_3</a> <= <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a>;
|
<a name="l03457"></a>03457 <span class="vhdlkeyword">end</span>
|
<a name="l03457"></a>03457 <span class="vhdlkeyword">end</span>
|
<a name="l03458"></a>03458
|
<a name="l03458"></a>03458 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a403d3720f31ad5a5895778bee758fb55">`PROCEDURE_call_read</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a029e3e9219332863900f71a52816c7ac">load_ea</a> == <span class="vhdllogic">9'd0</span>) <span class="vhdlkeyword">begin</span>
|
<a name="l03459"></a>03459 <span class="vhdlkeyword">endmodule</span>
|
<a name="l03459"></a>03459 <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a> <= <a class="code" href="classmicrocode__branch.html#ad9bc2cb9966990b791c16ae418be756c">micro_pc_0</a> + <span class="vhdllogic">9'd1</span>;
|
<a name="l03460"></a>03460
|
<a name="l03460"></a>03460 <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a> <= <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a>;
|
<a name="l03461"></a>03461 <span class="keyword">/***********************************************************************************************************************</span>
|
<a name="l03461"></a>03461 <a class="code" href="classmicrocode__branch.html#a8d7713b0340f69c7eae6282373e3bf7b">micro_pc_3</a> <= <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a>;
|
<a name="l03462"></a>03462 <span class="keyword"> Microcode branch</span>
|
<a name="l03462"></a>03462 <span class="vhdlkeyword">end</span>
|
<a name="l03463"></a>03463 <span class="keyword"> ***********************************************************************************************************************/</span>
|
<a name="l03463"></a>03463 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a50af2007588b7a528b934ae7672b1214">`PROCEDURE_call_write</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a2bf9f1fb5125818e8eb47aa043e0a393">save_ea</a> != <span class="vhdllogic">9'd0</span>) <span class="vhdlkeyword">begin</span>
|
<a name="l03464"></a>03464
|
<a name="l03464"></a>03464 <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a> <= <a class="code" href="classmicrocode__branch.html#a2bf9f1fb5125818e8eb47aa043e0a393">save_ea</a>;
|
<a name="l03465"></a>03465
|
<a name="l03465"></a>03465 <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a> <= <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a>;
|
<a name="l03474"></a><a class="code" href="classmicrocode__branch.html">03474</a> <span class="vhdlkeyword">module</span> <a class="code" href="classmicrocode__branch.html">microcode_branch</a>(
|
<a name="l03466"></a>03466 <a class="code" href="classmicrocode__branch.html#a8d7713b0340f69c7eae6282373e3bf7b">micro_pc_3</a> <= <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a>;
|
<a name="l03475"></a><a class="code" href="classmicrocode__branch.html#aa97186c6a6c8f8229219bceb1750b753">03475</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmicrocode__branch.html#aa97186c6a6c8f8229219bceb1750b753">clock</a>,
|
<a name="l03467"></a>03467 <span class="vhdlkeyword">end</span>
|
<a name="l03476"></a><a class="code" href="classmicrocode__branch.html#a446d61eb34eb480a38661d473bf25fd4">03476</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmicrocode__branch.html#a446d61eb34eb480a38661d473bf25fd4">reset_n</a>,
|
<a name="l03468"></a>03468 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>((<a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a5c7af3686fb890de6242f973de1ee549">`PROCEDURE_call_load_ea</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a029e3e9219332863900f71a52816c7ac">load_ea</a> != <span class="vhdllogic">9'd0</span>) ||
|
<a name="l03477"></a>03477
|
<a name="l03469"></a>03469 (<a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a698b04745cbbec22896235d5cfffac43">`PROCEDURE_call_perform_ea_read</a><span class="vhdlchar"></span>) ||
|
<a name="l03478"></a><a class="code" href="classmicrocode__branch.html#a42e8abed644ad88712e3f12b88119b93">03478</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">4</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#a42e8abed644ad88712e3f12b88119b93">movem_loop</a>,
|
<a name="l03470"></a>03470 (<a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#aa98c954da2ac9f709907c8c593b1439e">`PROCEDURE_call_perform_ea_write</a><span class="vhdlchar"></span>) ||
|
<a name="l03479"></a><a class="code" href="classmicrocode__branch.html#abad84561ae17084ceb7d2a623b446a14">03479</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#abad84561ae17084ceb7d2a623b446a14">movem_reg</a>,
|
<a name="l03471"></a>03471 (<a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a30022c5eb1821e27dd5c70d4affbc835">`PROCEDURE_call_save_ea</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a2bf9f1fb5125818e8eb47aa043e0a393">save_ea</a> != <span class="vhdllogic">9'd0</span>) ||
|
<a name="l03480"></a><a class="code" href="classmicrocode__branch.html#a44a7fbf19a4641fb5007ba59ea7867b2">03480</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#a44a7fbf19a4641fb5007ba59ea7867b2">operand2</a>,
|
<a name="l03472"></a>03472 (<a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a2c67cc2747b67d04684855e14c2b9fbb">`PROCEDURE_call_trap</a><span class="vhdlchar"></span>) )
|
<a name="l03481"></a><a class="code" href="classmicrocode__branch.html#ae0d0b0c347c453aed25820eb4d5ede60">03481</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmicrocode__branch.html#ae0d0b0c347c453aed25820eb4d5ede60">alu_signal</a>,
|
<a name="l03473"></a>03473 <span class="vhdlkeyword">begin</span>
|
<a name="l03482"></a><a class="code" href="classmicrocode__branch.html#a6965faa1f8f535384a68703714d67d41">03482</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmicrocode__branch.html#a6965faa1f8f535384a68703714d67d41">alu_mult_div_ready</a>,
|
<a name="l03474"></a>03474 <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a> <= <a class="code" href="classmicrocode__branch.html#ad9bc2cb9966990b791c16ae418be756c">micro_pc_0</a> + <span class="vhdllogic">9'd1</span>;
|
<a name="l03483"></a><a class="code" href="classmicrocode__branch.html#a812465227c1ce82d3a227a04a5cc9a89">03483</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmicrocode__branch.html#a812465227c1ce82d3a227a04a5cc9a89">condition</a>,
|
<a name="l03475"></a>03475 <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a> <= <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a>;
|
<a name="l03484"></a><a class="code" href="classmicrocode__branch.html#a07ec962ad743b1c4988f5b0f6332f393">03484</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#a07ec962ad743b1c4988f5b0f6332f393">result</a>,
|
<a name="l03476"></a>03476 <a class="code" href="classmicrocode__branch.html#a8d7713b0340f69c7eae6282373e3bf7b">micro_pc_3</a> <= <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a>;
|
<a name="l03485"></a><a class="code" href="classmicrocode__branch.html#a8e3878b37a15cbe9f5ac25d9d0c50ff5">03485</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmicrocode__branch.html#a8e3878b37a15cbe9f5ac25d9d0c50ff5">overflow</a>,
|
<a name="l03477"></a>03477 <span class="vhdlkeyword">end</span>
|
<a name="l03486"></a><a class="code" href="classmicrocode__branch.html#a76527514b31cb7de3a0f1f3a9b4fa039">03486</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmicrocode__branch.html#a76527514b31cb7de3a0f1f3a9b4fa039">stop_flag</a>,
|
<a name="l03478"></a>03478 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#af842761d13933777546d76bd997e7494">`PROCEDURE_return</a><span class="vhdlchar"></span>) <span class="vhdlkeyword">begin</span>
|
<a name="l03487"></a><a class="code" href="classmicrocode__branch.html#a66d21fc86ad1b8a3b3f72d78b9c96aef">03487</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#a66d21fc86ad1b8a3b3f72d78b9c96aef">ir</a>,
|
<a name="l03479"></a>03479 <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a> <= <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a>;
|
<a name="l03488"></a><a class="code" href="classmicrocode__branch.html#a96f331edcf8cb8bb65f80139b5248456">03488</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#a96f331edcf8cb8bb65f80139b5248456">decoder_trap</a>,
|
<a name="l03480"></a>03480 <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a> <= <a class="code" href="classmicrocode__branch.html#a8d7713b0340f69c7eae6282373e3bf7b">micro_pc_3</a>;
|
<a name="l03489"></a><a class="code" href="classmicrocode__branch.html#a909c52e94961a97edb894efc59ecae40">03489</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmicrocode__branch.html#a909c52e94961a97edb894efc59ecae40">trace_flag</a>,
|
<a name="l03481"></a>03481 <a class="code" href="classmicrocode__branch.html#a8d7713b0340f69c7eae6282373e3bf7b">micro_pc_3</a> <= <span class="vhdllogic">9'd0</span>;
|
<a name="l03490"></a><a class="code" href="classmicrocode__branch.html#a1520537038c18470f595c0d2858431f3">03490</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmicrocode__branch.html#a1520537038c18470f595c0d2858431f3">group_0_flag</a>,
|
<a name="l03482"></a>03482 <span class="vhdlkeyword">end</span>
|
<a name="l03491"></a><a class="code" href="classmicrocode__branch.html#a474cb146bed7bdde681694c3f06a1106">03491</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#a474cb146bed7bdde681694c3f06a1106">interrupt_mask</a>,
|
<a name="l03483"></a>03483 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a318a0823db3c0aa8dfeae26f05495e5b">`PROCEDURE_push_micropc</a><span class="vhdlchar"></span>) <span class="vhdlkeyword">begin</span>
|
<a name="l03492"></a>03492
|
<a name="l03484"></a>03484 <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a> <= <a class="code" href="classmicrocode__branch.html#ad9bc2cb9966990b791c16ae418be756c">micro_pc_0</a>;
|
<a name="l03493"></a><a class="code" href="classmicrocode__branch.html#a029e3e9219332863900f71a52816c7ac">03493</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#a029e3e9219332863900f71a52816c7ac">load_ea</a>,
|
<a name="l03485"></a>03485 <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a> <= <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a>;
|
<a name="l03494"></a><a class="code" href="classmicrocode__branch.html#acd130168642a726f7de176682a42e3ad">03494</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#acd130168642a726f7de176682a42e3ad">perform_ea_read</a>,
|
<a name="l03486"></a>03486 <a class="code" href="classmicrocode__branch.html#a8d7713b0340f69c7eae6282373e3bf7b">micro_pc_3</a> <= <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a>;
|
<a name="l03495"></a><a class="code" href="classmicrocode__branch.html#a6f20353ec8aea573354892ebe79e4aec">03495</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#a6f20353ec8aea573354892ebe79e4aec">perform_ea_write</a>,
|
<a name="l03487"></a>03487 <span class="vhdlkeyword">end</span>
|
<a name="l03496"></a><a class="code" href="classmicrocode__branch.html#a2bf9f1fb5125818e8eb47aa043e0a393">03496</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#a2bf9f1fb5125818e8eb47aa043e0a393">save_ea</a>,
|
<a name="l03488"></a>03488 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#acfe58e669e77374120e6e534fc621316">`PROCEDURE_pop_micropc</a><span class="vhdlchar"></span>) <span class="vhdlkeyword">begin</span>
|
<a name="l03497"></a><a class="code" href="classmicrocode__branch.html#a1493bf14db63cdb7d2ce8b2410b1c33b">03497</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#a1493bf14db63cdb7d2ce8b2410b1c33b">decoder_micropc</a>,
|
<a name="l03489"></a>03489 <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a> <= <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a>;
|
<a name="l03498"></a>03498
|
<a name="l03490"></a>03490 <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a> <= <a class="code" href="classmicrocode__branch.html#a8d7713b0340f69c7eae6282373e3bf7b">micro_pc_3</a>;
|
<a name="l03499"></a><a class="code" href="classmicrocode__branch.html#aef8500b16e788430917ee03f003d10a9">03499</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmicrocode__branch.html#aef8500b16e788430917ee03f003d10a9">prefetch_ir_valid_32</a>,
|
<a name="l03491"></a>03491 <a class="code" href="classmicrocode__branch.html#a8d7713b0340f69c7eae6282373e3bf7b">micro_pc_3</a> <= <span class="vhdllogic">9'd0</span>;
|
<a name="l03500"></a><a class="code" href="classmicrocode__branch.html#ae627b4cdc5e73300a5166eb7636468ea">03500</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmicrocode__branch.html#ae627b4cdc5e73300a5166eb7636468ea">prefetch_ir_valid</a>,
|
<a name="l03492"></a>03492 <span class="vhdlkeyword">end</span>
|
<a name="l03501"></a><a class="code" href="classmicrocode__branch.html#abc45eb66161b645c69d4b6ad6457ff31">03501</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmicrocode__branch.html#abc45eb66161b645c69d4b6ad6457ff31">jmp_address_trap</a>,
|
<a name="l03493"></a>03493 <span class="vhdlkeyword">end</span>
|
<a name="l03502"></a><a class="code" href="classmicrocode__branch.html#a9ba804e0f049ed633f01c611e248a587">03502</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmicrocode__branch.html#a9ba804e0f049ed633f01c611e248a587">jmp_bus_trap</a>,
|
<a name="l03494"></a>03494 <span class="vhdlkeyword">end</span>
|
<a name="l03503"></a><a class="code" href="classmicrocode__branch.html#ab3eb1598fd8ff755ee7811485c4b9849">03503</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmicrocode__branch.html#ab3eb1598fd8ff755ee7811485c4b9849">finished</a>,
|
<a name="l03495"></a>03495
|
<a name="l03504"></a>03504
|
<a name="l03496"></a>03496 <span class="vhdlkeyword">endmodule</span>
|
<a name="l03505"></a><a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">03505</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a>,
|
|
<a name="l03506"></a><a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">03506</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a>,
|
|
<a name="l03507"></a><a class="code" href="classmicrocode__branch.html#a53df336945e1387fada5822142621f2f">03507</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#a53df336945e1387fada5822142621f2f">micro_pc</a>
|
|
<a name="l03508"></a>03508 );
|
|
<a name="l03509"></a>03509
|
|
<a name="l03510"></a><a class="code" href="classmicrocode__branch.html#ad9bc2cb9966990b791c16ae418be756c">03510</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#ad9bc2cb9966990b791c16ae418be756c">micro_pc_0</a> = <span class="vhdllogic">9'd0</span>;
|
|
<a name="l03511"></a><a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">03511</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a>;
|
|
<a name="l03512"></a><a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">03512</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a>;
|
|
<a name="l03513"></a><a class="code" href="classmicrocode__branch.html#a8d7713b0340f69c7eae6282373e3bf7b">03513</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#a8d7713b0340f69c7eae6282373e3bf7b">micro_pc_3</a>;
|
|
<a name="l03514"></a>03514
|
|
<a name="l03515"></a>03515 <span class="vhdlkeyword">assign</span> <a class="code" href="classmicrocode__branch.html#a53df336945e1387fada5822142621f2f">micro_pc</a> =
|
|
<a name="l03516"></a>03516 (<a class="code" href="classmicrocode__branch.html#a446d61eb34eb480a38661d473bf25fd4">reset_n</a> == <span class="vhdllogic">1'b0</span>) ? <span class="vhdllogic">9'd0</span> :
|
|
<a name="l03517"></a>03517 (<a class="code" href="classmicrocode__branch.html#abc45eb66161b645c69d4b6ad6457ff31">jmp_address_trap</a> == <span class="vhdllogic">1'b1</span> || <a class="code" href="classmicrocode__branch.html#a9ba804e0f049ed633f01c611e248a587">jmp_bus_trap</a> == <span class="vhdllogic">1'b1</span>) ? <a class="code" href="ao68000_8v.html#ada4b6f4df06a5dcac3ec15d4c8f4d31e">`MICROPC_ADDRESS_BUS_TRAP</a><span class="vhdlchar"></span> :
|
|
<a name="l03518"></a>03518 ( (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#abdfc603db0ea3694052298e85fb6efad">`BRANCH_movem_loop</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a42e8abed644ad88712e3f12b88119b93">movem_loop</a> == <span class="vhdllogic">5'b10000</span>) ||
|
|
<a name="l03519"></a>03519 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#acc65cf5ec49ce78ecf98c956cd2de769">`BRANCH_movem_reg</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#abad84561ae17084ceb7d2a623b446a14">movem_reg</a>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">0</span>) ||
|
|
<a name="l03520"></a>03520 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#aa0b5846a5e98be60da75608078377571">`BRANCH_operand2</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a44a7fbf19a4641fb5007ba59ea7867b2">operand2</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b0</span>) ||
|
|
<a name="l03521"></a>03521 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a3db021156e8171951f6b91c78bbb7e1f">`BRANCH_alu_signal</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#ae0d0b0c347c453aed25820eb4d5ede60">alu_signal</a> == <span class="vhdllogic">1'b0</span>) ||
|
|
<a name="l03522"></a>03522 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a62fe8e5939da15f9f391886fe174183a">`BRANCH_alu_mult_div_ready</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a6965faa1f8f535384a68703714d67d41">alu_mult_div_ready</a> == <span class="vhdllogic">1'b1</span>) ||
|
|
<a name="l03523"></a>03523 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#af3158a11a9fc793d4aeead4195871507">`BRANCH_condition_0</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a812465227c1ce82d3a227a04a5cc9a89">condition</a> == <span class="vhdllogic">1'b0</span>) ||
|
|
<a name="l03524"></a>03524 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a48d5a0127f3bc738b8503c0713b9fba9">`BRANCH_condition_1</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a812465227c1ce82d3a227a04a5cc9a89">condition</a> == <span class="vhdllogic">1'b1</span>) ||
|
|
<a name="l03525"></a>03525 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a0cbdc7b4e718d5cc690b435995bb7708">`BRANCH_result</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a07ec962ad743b1c4988f5b0f6332f393">result</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'hFFFF</span>) ||
|
|
<a name="l03526"></a>03526 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a3861f0d4bd11e996bda23577348e86f7">`BRANCH_V</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a8e3878b37a15cbe9f5ac25d9d0c50ff5">overflow</a> == <span class="vhdllogic">1'b0</span>) ||
|
|
<a name="l03527"></a>03527 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a5fb736520363d5359408ed4af63c6125">`BRANCH_movep_16</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a66d21fc86ad1b8a3b3f72d78b9c96aef">ir</a>[<span class="vhdllogic">6</span>] == <span class="vhdllogic">1'b0</span>) ||
|
|
<a name="l03528"></a>03528 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a79ce1f7b2aa4e141d52316a04977ee60">`BRANCH_stop_flag_wait_ir_decode</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a76527514b31cb7de3a0f1f3a9b4fa039">stop_flag</a> == <span class="vhdllogic">1'b1</span>) ||
|
|
<a name="l03529"></a>03529 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a719e200160515b706ebab9fe1e18c8c7">`BRANCH_ir</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a66d21fc86ad1b8a3b3f72d78b9c96aef">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] != <span class="vhdllogic">8'b0</span>) ||
|
|
<a name="l03530"></a>03530 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#af396200d0e5941fe60e8d960f2e3aa91">`BRANCH_trace_flag_and_interrupt</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a909c52e94961a97edb894efc59ecae40">trace_flag</a> == <span class="vhdllogic">1'b0</span> && <a class="code" href="classmicrocode__branch.html#a474cb146bed7bdde681694c3f06a1106">interrupt_mask</a> != <span class="vhdllogic">3'b000</span>) ||
|
|
<a name="l03531"></a>03531 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a63f967b1bbe9ad356e3ccbbb2924e03f">`BRANCH_group_0_flag</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a1520537038c18470f595c0d2858431f3">group_0_flag</a> == <span class="vhdllogic">1'b0</span>)
|
|
<a name="l03532"></a>03532 ) ? <a class="code" href="classmicrocode__branch.html#ad9bc2cb9966990b791c16ae418be756c">micro_pc_0</a> + { <span class="vhdllogic">5'd0</span>, <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> } :
|
|
<a name="l03533"></a>03533 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a79ce1f7b2aa4e141d52316a04977ee60">`BRANCH_stop_flag_wait_ir_decode</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#ae627b4cdc5e73300a5166eb7636468ea">prefetch_ir_valid</a> == <span class="vhdllogic">1'b1</span> && <a class="code" href="classmicrocode__branch.html#a96f331edcf8cb8bb65f80139b5248456">decoder_trap</a> == <span class="vhdllogic">8'd0</span>) ? <a class="code" href="classmicrocode__branch.html#a1493bf14db63cdb7d2ce8b2410b1c33b">decoder_micropc</a> :
|
|
<a name="l03534"></a>03534 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#af396200d0e5941fe60e8d960f2e3aa91">`BRANCH_trace_flag_and_interrupt</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a909c52e94961a97edb894efc59ecae40">trace_flag</a> == <span class="vhdllogic">1'b0</span> && <a class="code" href="classmicrocode__branch.html#a474cb146bed7bdde681694c3f06a1106">interrupt_mask</a> == <span class="vhdllogic">3'b000</span>) ? <a class="code" href="ao68000_8v.html#a1e7ad8f4b421f72f5bdea07bef35f864">`MICROPC_MAIN_LOOP</a><span class="vhdlchar"></span> :
|
|
<a name="l03535"></a>03535 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a1f24f0ad71fd4d2edd6ead5ef6c3056a">`BRANCH_procedure</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a7950509479648899370516cfa0221c43">`PROCEDURE_jump_to_main_loop</a><span class="vhdlchar"></span>) ? <a class="code" href="ao68000_8v.html#a1e7ad8f4b421f72f5bdea07bef35f864">`MICROPC_MAIN_LOOP</a><span class="vhdlchar"></span> :
|
|
<a name="l03536"></a>03536 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a1f24f0ad71fd4d2edd6ead5ef6c3056a">`BRANCH_procedure</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a5c7af3686fb890de6242f973de1ee549">`PROCEDURE_call_load_ea</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a029e3e9219332863900f71a52816c7ac">load_ea</a> != <span class="vhdllogic">9'd0</span>) ? <a class="code" href="classmicrocode__branch.html#a029e3e9219332863900f71a52816c7ac">load_ea</a> :
|
|
<a name="l03537"></a>03537 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a1f24f0ad71fd4d2edd6ead5ef6c3056a">`BRANCH_procedure</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a698b04745cbbec22896235d5cfffac43">`PROCEDURE_call_perform_ea_read</a><span class="vhdlchar"></span>) ? <a class="code" href="classmicrocode__branch.html#acd130168642a726f7de176682a42e3ad">perform_ea_read</a> :
|
|
<a name="l03538"></a>03538 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a1f24f0ad71fd4d2edd6ead5ef6c3056a">`BRANCH_procedure</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#aa98c954da2ac9f709907c8c593b1439e">`PROCEDURE_call_perform_ea_write</a><span class="vhdlchar"></span>) ? <a class="code" href="classmicrocode__branch.html#a6f20353ec8aea573354892ebe79e4aec">perform_ea_write</a> :
|
|
<a name="l03539"></a>03539 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a1f24f0ad71fd4d2edd6ead5ef6c3056a">`BRANCH_procedure</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a30022c5eb1821e27dd5c70d4affbc835">`PROCEDURE_call_save_ea</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a2bf9f1fb5125818e8eb47aa043e0a393">save_ea</a> != <span class="vhdllogic">9'd0</span>) ? <a class="code" href="classmicrocode__branch.html#a2bf9f1fb5125818e8eb47aa043e0a393">save_ea</a> :
|
|
<a name="l03540"></a>03540
|
|
<a name="l03541"></a>03541 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a1f24f0ad71fd4d2edd6ead5ef6c3056a">`BRANCH_procedure</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a403d3720f31ad5a5895778bee758fb55">`PROCEDURE_call_read</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a029e3e9219332863900f71a52816c7ac">load_ea</a> != <span class="vhdllogic">9'd0</span>) ? <a class="code" href="classmicrocode__branch.html#a029e3e9219332863900f71a52816c7ac">load_ea</a> :
|
|
<a name="l03542"></a>03542 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a1f24f0ad71fd4d2edd6ead5ef6c3056a">`BRANCH_procedure</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a403d3720f31ad5a5895778bee758fb55">`PROCEDURE_call_read</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a029e3e9219332863900f71a52816c7ac">load_ea</a> == <span class="vhdllogic">9'd0</span>) ? <a class="code" href="classmicrocode__branch.html#acd130168642a726f7de176682a42e3ad">perform_ea_read</a> :
|
|
<a name="l03543"></a>03543
|
|
<a name="l03544"></a>03544 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a1f24f0ad71fd4d2edd6ead5ef6c3056a">`BRANCH_procedure</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a50af2007588b7a528b934ae7672b1214">`PROCEDURE_call_write</a><span class="vhdlchar"></span>) ? <a class="code" href="classmicrocode__branch.html#a6f20353ec8aea573354892ebe79e4aec">perform_ea_write</a> :
|
|
<a name="l03545"></a>03545
|
|
<a name="l03546"></a>03546 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a1f24f0ad71fd4d2edd6ead5ef6c3056a">`BRANCH_procedure</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a2c67cc2747b67d04684855e14c2b9fbb">`PROCEDURE_call_trap</a><span class="vhdlchar"></span>) ? <a class="code" href="ao68000_8v.html#a80e45e303a1ebe180eeb15b47454e13f">`MICROPC_TRAP_ENTRY</a><span class="vhdlchar"></span> :
|
|
<a name="l03547"></a>03547 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a1f24f0ad71fd4d2edd6ead5ef6c3056a">`BRANCH_procedure</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#af842761d13933777546d76bd997e7494">`PROCEDURE_return</a><span class="vhdlchar"></span>) ? <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a> :
|
|
<a name="l03548"></a>03548 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a1f24f0ad71fd4d2edd6ead5ef6c3056a">`BRANCH_procedure</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#ac74b95b43e6c95ed82036002767bc22c">`PROCEDURE_interrupt_mask</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a474cb146bed7bdde681694c3f06a1106">interrupt_mask</a> == <span class="vhdllogic">3'b000</span>) ? <a class="code" href="ao68000_8v.html#a1e7ad8f4b421f72f5bdea07bef35f864">`MICROPC_MAIN_LOOP</a><span class="vhdlchar"></span> :
|
|
<a name="l03549"></a>03549 ( (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a1f24f0ad71fd4d2edd6ead5ef6c3056a">`BRANCH_procedure</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a26a2f20a92ff8ab6f13d6633f3c9475c">`PROCEDURE_wait_finished</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#ab3eb1598fd8ff755ee7811485c4b9849">finished</a> == <span class="vhdllogic">1'b0</span>) ||
|
|
<a name="l03550"></a>03550 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a1f24f0ad71fd4d2edd6ead5ef6c3056a">`BRANCH_procedure</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#aa072f73b12cd178a44f47980e1bb98cb">`PROCEDURE_wait_prefetch_valid</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#ae627b4cdc5e73300a5166eb7636468ea">prefetch_ir_valid</a> == <span class="vhdllogic">1'b0</span>) ||
|
|
<a name="l03551"></a>03551 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a1f24f0ad71fd4d2edd6ead5ef6c3056a">`BRANCH_procedure</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a0ef2adec86a42dd30d78e9d259d828fd">`PROCEDURE_wait_prefetch_valid_32</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#aef8500b16e788430917ee03f003d10a9">prefetch_ir_valid_32</a> == <span class="vhdllogic">1'b0</span>) ||
|
|
<a name="l03552"></a>03552 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a79ce1f7b2aa4e141d52316a04977ee60">`BRANCH_stop_flag_wait_ir_decode</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#ae627b4cdc5e73300a5166eb7636468ea">prefetch_ir_valid</a> == <span class="vhdllogic">1'b0</span>)
|
|
<a name="l03553"></a>03553 ) ? <a class="code" href="classmicrocode__branch.html#ad9bc2cb9966990b791c16ae418be756c">micro_pc_0</a> :
|
|
<a name="l03554"></a>03554 <a class="code" href="classmicrocode__branch.html#ad9bc2cb9966990b791c16ae418be756c">micro_pc_0</a> + <span class="vhdllogic">9'd1</span>
|
|
<a name="l03555"></a>03555 ;
|
|
<a name="l03556"></a>03556
|
|
<a name="l03557"></a><a class="code" href="classmicrocode__branch.html#a5c48a82153e9796a3913029cde0cc182">03557</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classmicrocode__branch.html#aa97186c6a6c8f8229219bceb1750b753">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classmicrocode__branch.html#a446d61eb34eb480a38661d473bf25fd4">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
|
<a name="l03558"></a>03558 <span class="vhdlkeyword">if</span>(<a class="code" href="classmicrocode__branch.html#a446d61eb34eb480a38661d473bf25fd4">reset_n</a> == <span class="vhdllogic">1'b0</span>) <a class="code" href="classmicrocode__branch.html#ad9bc2cb9966990b791c16ae418be756c">micro_pc_0</a> <= <span class="vhdllogic">9'd0</span>;
|
|
<a name="l03559"></a>03559 <span class="vhdlkeyword">else</span> <a class="code" href="classmicrocode__branch.html#ad9bc2cb9966990b791c16ae418be756c">micro_pc_0</a> <= <a class="code" href="classmicrocode__branch.html#a53df336945e1387fada5822142621f2f">micro_pc</a>;
|
|
<a name="l03560"></a>03560 <span class="vhdlkeyword">end</span>
|
|
<a name="l03561"></a>03561
|
|
<a name="l03562"></a><a class="code" href="classmicrocode__branch.html#a4e2c393980b78c66fbb22710e14a1cbb">03562</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classmicrocode__branch.html#aa97186c6a6c8f8229219bceb1750b753">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classmicrocode__branch.html#a446d61eb34eb480a38661d473bf25fd4">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
|
<a name="l03563"></a>03563 <span class="vhdlkeyword">if</span>(<a class="code" href="classmicrocode__branch.html#a446d61eb34eb480a38661d473bf25fd4">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
|
<a name="l03564"></a>03564 <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a> <= <span class="vhdllogic">9'd0</span>;
|
|
<a name="l03565"></a>03565 <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a> <= <span class="vhdllogic">9'd0</span>;
|
|
<a name="l03566"></a>03566 <a class="code" href="classmicrocode__branch.html#a8d7713b0340f69c7eae6282373e3bf7b">micro_pc_3</a> <= <span class="vhdllogic">9'd0</span>;
|
|
<a name="l03567"></a>03567 <span class="vhdlkeyword">end</span>
|
|
<a name="l03568"></a>03568 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a79ce1f7b2aa4e141d52316a04977ee60">`BRANCH_stop_flag_wait_ir_decode</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#ae627b4cdc5e73300a5166eb7636468ea">prefetch_ir_valid</a> == <span class="vhdllogic">1'b1</span> && <a class="code" href="classmicrocode__branch.html#a96f331edcf8cb8bb65f80139b5248456">decoder_trap</a> == <span class="vhdllogic">8'd0</span>)
|
|
<a name="l03569"></a>03569 <span class="vhdlkeyword">begin</span>
|
|
<a name="l03570"></a>03570 <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a> <= <a class="code" href="classmicrocode__branch.html#ad9bc2cb9966990b791c16ae418be756c">micro_pc_0</a> + { <span class="vhdllogic">5'd0</span>, <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> };
|
|
<a name="l03571"></a>03571 <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a> <= <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a>;
|
|
<a name="l03572"></a>03572 <a class="code" href="classmicrocode__branch.html#a8d7713b0340f69c7eae6282373e3bf7b">micro_pc_3</a> <= <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a>;
|
|
<a name="l03573"></a>03573 <span class="vhdlkeyword">end</span>
|
|
<a name="l03574"></a>03574 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a1f24f0ad71fd4d2edd6ead5ef6c3056a">`BRANCH_procedure</a><span class="vhdlchar"></span>) <span class="vhdlkeyword">begin</span>
|
|
<a name="l03575"></a>03575 <span class="vhdlkeyword">if</span>(<a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a403d3720f31ad5a5895778bee758fb55">`PROCEDURE_call_read</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a029e3e9219332863900f71a52816c7ac">load_ea</a> != <span class="vhdllogic">9'd0</span>) <span class="vhdlkeyword">begin</span>
|
|
<a name="l03576"></a>03576 <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a> <= <a class="code" href="classmicrocode__branch.html#acd130168642a726f7de176682a42e3ad">perform_ea_read</a>;
|
|
<a name="l03577"></a>03577 <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a> <= <a class="code" href="classmicrocode__branch.html#ad9bc2cb9966990b791c16ae418be756c">micro_pc_0</a> + <span class="vhdllogic">9'd1</span>;
|
|
<a name="l03578"></a>03578 <a class="code" href="classmicrocode__branch.html#a8d7713b0340f69c7eae6282373e3bf7b">micro_pc_3</a> <= <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a>;
|
|
<a name="l03579"></a>03579 <span class="vhdlkeyword">end</span>
|
|
<a name="l03580"></a>03580 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a403d3720f31ad5a5895778bee758fb55">`PROCEDURE_call_read</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a029e3e9219332863900f71a52816c7ac">load_ea</a> == <span class="vhdllogic">9'd0</span>) <span class="vhdlkeyword">begin</span>
|
|
<a name="l03581"></a>03581 <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a> <= <a class="code" href="classmicrocode__branch.html#ad9bc2cb9966990b791c16ae418be756c">micro_pc_0</a> + <span class="vhdllogic">9'd1</span>;
|
|
<a name="l03582"></a>03582 <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a> <= <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a>;
|
|
<a name="l03583"></a>03583 <a class="code" href="classmicrocode__branch.html#a8d7713b0340f69c7eae6282373e3bf7b">micro_pc_3</a> <= <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a>;
|
|
<a name="l03584"></a>03584 <span class="vhdlkeyword">end</span>
|
|
<a name="l03585"></a>03585 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a50af2007588b7a528b934ae7672b1214">`PROCEDURE_call_write</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a2bf9f1fb5125818e8eb47aa043e0a393">save_ea</a> != <span class="vhdllogic">9'd0</span>) <span class="vhdlkeyword">begin</span>
|
|
<a name="l03586"></a>03586 <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a> <= <a class="code" href="classmicrocode__branch.html#a2bf9f1fb5125818e8eb47aa043e0a393">save_ea</a>;
|
|
<a name="l03587"></a>03587 <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a> <= <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a>;
|
|
<a name="l03588"></a>03588 <a class="code" href="classmicrocode__branch.html#a8d7713b0340f69c7eae6282373e3bf7b">micro_pc_3</a> <= <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a>;
|
|
<a name="l03589"></a>03589 <span class="vhdlkeyword">end</span>
|
|
<a name="l03590"></a>03590 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>((<a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a5c7af3686fb890de6242f973de1ee549">`PROCEDURE_call_load_ea</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a029e3e9219332863900f71a52816c7ac">load_ea</a> != <span class="vhdllogic">9'd0</span>) ||
|
|
<a name="l03591"></a>03591 (<a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a698b04745cbbec22896235d5cfffac43">`PROCEDURE_call_perform_ea_read</a><span class="vhdlchar"></span>) ||
|
|
<a name="l03592"></a>03592 (<a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#aa98c954da2ac9f709907c8c593b1439e">`PROCEDURE_call_perform_ea_write</a><span class="vhdlchar"></span>) ||
|
|
<a name="l03593"></a>03593 (<a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a30022c5eb1821e27dd5c70d4affbc835">`PROCEDURE_call_save_ea</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a2bf9f1fb5125818e8eb47aa043e0a393">save_ea</a> != <span class="vhdllogic">9'd0</span>) ||
|
|
<a name="l03594"></a>03594 (<a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a2c67cc2747b67d04684855e14c2b9fbb">`PROCEDURE_call_trap</a><span class="vhdlchar"></span>) )
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|
<a name="l03595"></a>03595 <span class="vhdlkeyword">begin</span>
|
|
<a name="l03596"></a>03596 <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a> <= <a class="code" href="classmicrocode__branch.html#ad9bc2cb9966990b791c16ae418be756c">micro_pc_0</a> + <span class="vhdllogic">9'd1</span>;
|
|
<a name="l03597"></a>03597 <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a> <= <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a>;
|
|
<a name="l03598"></a>03598 <a class="code" href="classmicrocode__branch.html#a8d7713b0340f69c7eae6282373e3bf7b">micro_pc_3</a> <= <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a>;
|
|
<a name="l03599"></a>03599 <span class="vhdlkeyword">end</span>
|
|
<a name="l03600"></a>03600 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#af842761d13933777546d76bd997e7494">`PROCEDURE_return</a><span class="vhdlchar"></span>) <span class="vhdlkeyword">begin</span>
|
|
<a name="l03601"></a>03601 <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a> <= <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a>;
|
|
<a name="l03602"></a>03602 <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a> <= <a class="code" href="classmicrocode__branch.html#a8d7713b0340f69c7eae6282373e3bf7b">micro_pc_3</a>;
|
|
<a name="l03603"></a>03603 <a class="code" href="classmicrocode__branch.html#a8d7713b0340f69c7eae6282373e3bf7b">micro_pc_3</a> <= <span class="vhdllogic">9'd0</span>;
|
|
<a name="l03604"></a>03604 <span class="vhdlkeyword">end</span>
|
|
<a name="l03605"></a>03605 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a318a0823db3c0aa8dfeae26f05495e5b">`PROCEDURE_push_micropc</a><span class="vhdlchar"></span>) <span class="vhdlkeyword">begin</span>
|
|
<a name="l03606"></a>03606 <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a> <= <a class="code" href="classmicrocode__branch.html#ad9bc2cb9966990b791c16ae418be756c">micro_pc_0</a>;
|
|
<a name="l03607"></a>03607 <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a> <= <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a>;
|
|
<a name="l03608"></a>03608 <a class="code" href="classmicrocode__branch.html#a8d7713b0340f69c7eae6282373e3bf7b">micro_pc_3</a> <= <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a>;
|
|
<a name="l03609"></a>03609 <span class="vhdlkeyword">end</span>
|
|
<a name="l03610"></a>03610 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#acfe58e669e77374120e6e534fc621316">`PROCEDURE_pop_micropc</a><span class="vhdlchar"></span>) <span class="vhdlkeyword">begin</span>
|
|
<a name="l03611"></a>03611 <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a> <= <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a>;
|
|
<a name="l03612"></a>03612 <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a> <= <a class="code" href="classmicrocode__branch.html#a8d7713b0340f69c7eae6282373e3bf7b">micro_pc_3</a>;
|
|
<a name="l03613"></a>03613 <a class="code" href="classmicrocode__branch.html#a8d7713b0340f69c7eae6282373e3bf7b">micro_pc_3</a> <= <span class="vhdllogic">9'd0</span>;
|
|
<a name="l03614"></a>03614 <span class="vhdlkeyword">end</span>
|
|
<a name="l03615"></a>03615 <span class="vhdlkeyword">end</span>
|
|
<a name="l03616"></a>03616 <span class="vhdlkeyword">end</span>
|
|
<a name="l03617"></a>03617
|
|
<a name="l03618"></a>03618 <span class="vhdlkeyword">endmodule</span>
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|
</pre></div></div>
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</pre></div></div>
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</div>
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</div>
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<hr class="footer"/><address class="footer"><small>Generated on Sat Jan 15 2011 16:45:29 for ao68000 by 
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<hr class="footer"/><address class="footer"><small>Generated on Sat Jan 15 2011 16:54:37 for ao68000 by 
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<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.2 </small></address>
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<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.2 </small></address>
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