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<h3>Features</h3>
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<h3>Features</h3>
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<ul>
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<ul>
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<li>CISC processor with microcode,</li>
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<li>CISC processor with microcode,</li>
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<li>WISHBONE revision B.3 compatible MASTER interface,</li>
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<li>WISHBONE revision B.3 compatible MASTER interface,</li>
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<li>Not cycle exact with the MC68000, some instructions take more cycles to complete, some less,</li>
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<li>Not cycle exact with the MC68000, some instructions take more cycles to complete, some less,</li>
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<li>Uses about 4750 LE on Altera Cyclone II and about 45600 bits of RAM for microcode,</li>
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<li>Uses about 4810 LE on Altera Cyclone II and about 45600 bits of RAM for microcode,</li>
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<li>Tested against the WinUAE M68000 software emulator. Every 16-bit instruction was tested with random register contents and RAM contents (<a class="el" href="page_verification.html">Processor verification</a>). The result of execution was compared,</li>
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<li>Tested against the WinUAE M68000 software emulator. Every 16-bit instruction was tested with random register contents and RAM contents (<a class="el" href="page_verification.html">Processor verification</a>). The result of execution was compared,</li>
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<li>Contains a simple prefetch which is capable of holding up to 5 16-bit instruction words,</li>
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<li>Contains a simple prefetch which is capable of holding up to 5 16-bit instruction words,</li>
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<li>Documentation generated by Doxygen (www.doxygen.org) with doxverilog patch (<a href="http://developer.berlios.de/projects/doxverilog/">http://developer.berlios.de/projects/doxverilog/</a>). The specification is automatically extracted from the Doxygen HTML output.</li>
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<li>Documentation generated by Doxygen (www.doxygen.org) with doxverilog patch (<a href="http://developer.berlios.de/projects/doxverilog/">http://developer.berlios.de/projects/doxverilog/</a>). The specification is automatically extracted from the Doxygen HTML output.</li>
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</ul>
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</ul>
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<h3>WISHBONE compatibility</h3>
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<h3>WISHBONE compatibility</h3>
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| Line 50... |
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<li>WISHBONE data port size: 32-bit,</li>
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<li>WISHBONE data port size: 32-bit,</li>
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<li>Data port granularity: 8-bits,</li>
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<li>Data port granularity: 8-bits,</li>
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<li>Data port maximum operand size: 32-bits,</li>
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<li>Data port maximum operand size: 32-bits,</li>
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<li>Data transfer ordering: BIG ENDIAN,</li>
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<li>Data transfer ordering: BIG ENDIAN,</li>
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<li>Data transfer sequencing: UNDEFINED,</li>
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<li>Data transfer sequencing: UNDEFINED,</li>
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<li>Constraints on <code>CLK_I</code> signal: described in <a class="el" href="page_spec_clocks.html">Clocks</a>, maximum frequency: about 82 MHz.</li>
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<li>Constraints on <code>CLK_I</code> signal: described in <a class="el" href="page_spec_clocks.html">Clocks</a>, maximum frequency: about 90 MHz.</li>
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</ul>
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</ul>
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<h3>Use</h3>
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<h3>Use</h3>
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<ul>
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<ul>
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<li>The <a class="el" href="classao68000.html" title="ao68000 top level module.">ao68000</a> is used as the processor for the OpenCores aoOCS project - Wishbone Amiga OCS SoC(<a href="http://opencores.org/project,aoocs">http://opencores.org/project,aoocs</a>).</li>
|
<li>The <a class="el" href="classao68000.html" title="ao68000 top level module.">ao68000</a> is used as the processor for the OpenCores aoOCS project - Wishbone Amiga OCS SoC(<a href="http://opencores.org/project,aoocs">http://opencores.org/project,aoocs</a>).</li>
|
<li>It can also be used as a processor in a System-on-Chip booting Linux kernel version 2.6.33.1 up to <code>init</code> program lookup (<a class="el" href="page_soc_linux.html">System-on-Chip example with ao68000 running Linux</a>).</li>
|
<li>It can also be used as a processor in a System-on-Chip booting Linux kernel version 2.6.33.1 up to <code>init</code> program lookup (<a class="el" href="page_soc_linux.html">System-on-Chip example with ao68000 running Linux</a>).</li>
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| Line 100... |
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<ul>
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<ul>
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<li><b><a class="el" href="classao68000.html" title="ao68000 top level module.">ao68000</a></b> - the <a class="el" href="classao68000.html" title="ao68000 top level module.">ao68000</a> IP Core processor,</li>
|
<li><b><a class="el" href="classao68000.html" title="ao68000 top level module.">ao68000</a></b> - the <a class="el" href="classao68000.html" title="ao68000 top level module.">ao68000</a> IP Core processor,</li>
|
<li><b>MC68000</b> - the original Motorola MC68000 processor. </li>
|
<li><b>MC68000</b> - the original Motorola MC68000 processor. </li>
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</ul>
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</ul>
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</div>
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</div>
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<hr class="footer"/><address class="footer"><small>Generated on Sat Jan 15 2011 22:20:15 for ao68000 by 
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<hr class="footer"/><address class="footer"><small>Generated on Sun Jan 16 2011 11:00:03 for ao68000 by 
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<a href="http://www.doxygen.org/index.html">
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<a href="http://www.doxygen.org/index.html">
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<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.2 </small></address>
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<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.2 </small></address>
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</body>
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</body>
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</html>
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</html>
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