| Line 76... |
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* <table width=100%>
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* <table width=100%>
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* <tr style="background: #CCCCCC; font-weight: bold;">
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* <tr style="background: #CCCCCC; font-weight: bold;">
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* <td>Rev. </td><td>Date </td><td>Author </td><td>Description </td></tr>
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* <td>Rev. </td><td>Date </td><td>Author </td><td>Description </td></tr>
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* <tr><td>1.0 </td><td>28.03.2010 </td><td>Aleksander Osman </td><td>First Draft </td></tr>
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* <tr><td>1.0 </td><td>28.03.2010 </td><td>Aleksander Osman </td><td>First Draft </td></tr>
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* <tr><td>1.1 </td><td>11.12.2010 </td><td>Aleksander Osman </td><td>DBcc opcode microcode fix. Wishbone SEL signal fix. Project directory structure simplification.</td></tr>
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* <tr><td>1.1 </td><td>11.12.2010 </td><td>Aleksander Osman </td><td>DBcc opcode microcode fix. Wishbone SEL signal fix. Project directory structure simplification.</td></tr>
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* <tr><td>1.2 </td><td>15.01.2011 </td><td>Aleksander Osman, Frederic Requin</td><td>Core area optimization: biggest gain in ALU multiplication and division reimplementation.</td></tr>
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* </table>
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* </table>
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*/
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*/
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|
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/*! \page page_spec_introduction Introduction
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/*! \page page_spec_introduction Introduction
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*
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*
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| Line 87... |
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*
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*
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* <h3>Features</h3>
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* <h3>Features</h3>
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* - CISC processor with microcode,
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* - CISC processor with microcode,
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* - WISHBONE revision B.3 compatible MASTER interface,
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* - WISHBONE revision B.3 compatible MASTER interface,
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* - Not cycle exact with the MC68000, some instructions take more cycles to complete, some less,
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* - Not cycle exact with the MC68000, some instructions take more cycles to complete, some less,
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* - Uses about 7500 LE on Altera Cyclone II and about 45000 bits of RAM for microcode,
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* - Uses about 4925 LE on Altera Cyclone II and about 45600 bits of RAM for microcode,
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* - Tested against the WinUAE M68000 software emulator. Every 16-bit instruction was tested with random register contents and RAM contents
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* - Tested against the WinUAE M68000 software emulator. Every 16-bit instruction was tested with random register contents and RAM contents
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* (\ref page_verification). The result of execution was compared,
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* (\ref page_verification). The result of execution was compared,
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* - Runs Linux kernel version 2.6.33.1 up to init process lookup (\ref page_soc_linux),
|
|
* - Contains a simple prefetch which is capable of holding up to 5 16-bit instruction words,
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* - Contains a simple prefetch which is capable of holding up to 5 16-bit instruction words,
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* - Documentation generated by Doxygen (www.doxygen.org) with doxverilog patch (http://developer.berlios.de/projects/doxverilog/). The specification
|
* - Documentation generated by Doxygen (www.doxygen.org) with doxverilog patch (http://developer.berlios.de/projects/doxverilog/). The specification
|
* is automatically extracted from the Doxygen HTML output.
|
* is automatically extracted from the Doxygen HTML output.
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*
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*
|
* <h3>WISHBONE compatibility</h3>
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* <h3>WISHBONE compatibility</h3>
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| Line 108... |
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* - WISHBONE data port size: 32-bit,
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* - WISHBONE data port size: 32-bit,
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* - Data port granularity: 8-bits,
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* - Data port granularity: 8-bits,
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* - Data port maximum operand size: 32-bits,
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* - Data port maximum operand size: 32-bits,
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* - Data transfer ordering: BIG ENDIAN,
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* - Data transfer ordering: BIG ENDIAN,
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* - Data transfer sequencing: UNDEFINED,
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* - Data transfer sequencing: UNDEFINED,
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* - Constraints on <tt>CLK_I</tt> signal: described in \ref page_spec_clocks, maximum frequency: about 70 MHz.
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* - Constraints on <tt>CLK_I</tt> signal: described in \ref page_spec_clocks, maximum frequency: about 64 MHz.
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*
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*
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* <h3>Use</h3>
|
* <h3>Use</h3>
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* The ao68000 can be used as an processor in a System-on-Chip booting Linux kernel up to <tt>init</tt> program lookup (\ref page_soc_linux).
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* - The ao68000 is used as the processor for the OpenCores aoOCS project - Wishbone Amiga OCS SoC(http://opencores.org/project,aoocs).
|
|
* - It can also be used as a processor in a System-on-Chip booting Linux kernel version 2.6.33.1 up to <tt>init</tt> program lookup (\ref page_soc_linux).
|
*
|
*
|
* <h3>Similar projects</h3>
|
* <h3>Similar projects</h3>
|
* Other free soft-core implementations of M68000 microprocessor include:
|
* Other free soft-core implementations of M68000 microprocessor include:
|
* - OpenCores TG68 (http://www.opencores.org/project,tg68) - runs Amiga software, used as part of the Minimig Core,
|
* - OpenCores TG68 (http://www.opencores.org/project,tg68) - runs Amiga software, used as part of the Minimig Core,
|
* - Suska Atari VHDL WF_68K00_IP Core (http://www.experiment-s.de/en) - runs Atari software,
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* - Suska Atari VHDL WF_68K00_IP Core (http://www.experiment-s.de/en) - runs Atari software,
|
| Line 123... |
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* - OpenCores ae68 (http://www.opencores.org/project,ae68) - no files uploaded as of 27.03.2010.
|
* - OpenCores ae68 (http://www.opencores.org/project,ae68) - no files uploaded as of 27.03.2010.
|
*
|
*
|
* <h3>Limitations</h3>
|
* <h3>Limitations</h3>
|
* - Microcode not optimized: some instructions take more cycles to execute than the original MC68000,
|
* - Microcode not optimized: some instructions take more cycles to execute than the original MC68000,
|
* - TRACE not tested,
|
* - TRACE not tested,
|
* - The core is large compared to other implementations.
|
* - The core is still large compared to other implementations.
|
*
|
*
|
* <h3>TODO</h3>
|
* <h3>TODO</h3>
|
* - Optimize the microcode and count the exact cycle count for every instruction,
|
* - Optimize the desgin and microcode,
|
|
* - Count the exact cycle count for every instruction,
|
* - Test TRACE,
|
* - Test TRACE,
|
* - Run WISHBONE verification models,
|
* - Write more documentation.
|
* - More documentation of the ao68000 module: signal description, operation, FSM in <tt>bus_control</tt>,
|
|
* - Describe changes done in WinUAE sources (copy from ao.c),
|
|
* - Describe microcode words and subprocedures,
|
|
* - Document the <tt>soc_for_linux</tt> modules,
|
|
* - Prepare scripts for VATS: run_sim -r -> regresion test,
|
|
* - Use memories from OpenCore common.
|
|
*
|
*
|
* <h3>Status</h3>
|
* <h3>Status</h3>
|
* - Tested with WinUAE software MC68000 emulator,
|
* - April 2010: Tested with WinUAE software MC68000 emulator,
|
* - Booted Linux kernel up to <tt>init</tt> process lookup.
|
* - April 2010: Booted Linux kernel up to <tt>init</tt> process lookup,
|
|
* - December 2010: Runs as a processor in OpenCores aoOCS project,
|
|
* - January 2011: Core area optimization by over 33% (Thanks to Frederic Requin).
|
*
|
*
|
* <h3>Requirements</h3>
|
* <h3>Requirements</h3>
|
* - Icarus Verilog simulator (http://www.icarus.com/eda/verilog/) is required to compile the <tt>tb_ao68000</tt> testbench/wrapper,
|
* - Icarus Verilog simulator (http://www.icarus.com/eda/verilog/) is required to compile the <tt>tb_ao68000</tt> testbench/wrapper,
|
* - Access to Altera Quartus II instalation directory (directory eda/sim_lib/) is required to compile the <tt>tb_ao68000</tt> testbench/wrapper,
|
* - Access to Altera Quartus II instalation directory (directory eda/sim_lib/) is required to compile the <tt>tb_ao68000</tt> testbench/wrapper,
|
* - GCC (http://gcc.gnu.org) is required to compile the WinUAE MC68000 software emulator,
|
* - GCC (http://gcc.gnu.org) is required to compile the WinUAE MC68000 software emulator,
|
| Line 372... |
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* <tr style="background: #CCCCCC; font-weight: bold;">
|
* <tr style="background: #CCCCCC; font-weight: bold;">
|
* <td rowspan=2>Name</td><td rowspan=2>Source</td><td colspan=3>Rates (MHz)</td><td rowspan=2>Remarks</td><td rowspan=2>Description</td></tr>
|
* <td rowspan=2>Name</td><td rowspan=2>Source</td><td colspan=3>Rates (MHz)</td><td rowspan=2>Remarks</td><td rowspan=2>Description</td></tr>
|
* <tr style="background: #CCCCCC; font-weight: bold;">
|
* <tr style="background: #CCCCCC; font-weight: bold;">
|
* <td>Max</td><td>Min</td><td>Resolution</td></tr>
|
* <td>Max</td><td>Min</td><td>Resolution</td></tr>
|
*
|
*
|
* <tr><td>CLK_I</td><td>Input Port</td><td>70</td><td>-</td><td>-</td><td>-</td><td>System clock.</td></tr>
|
* <tr><td>CLK_I</td><td>Input Port</td><td>64</td><td>-</td><td>-</td><td>-</td><td>System clock.</td></tr>
|
* </table>
|
* </table>
|
*/
|
*/
|
|
|
/*! \page page_spec_ports IO Ports
|
/*! \page page_spec_ports IO Ports
|
* <h3>WISHBONE IO Ports</h3>
|
* <h3>WISHBONE IO Ports</h3>
|
