| Line 88... |
Line 88... |
*
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*
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* <h3>Features</h3>
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* <h3>Features</h3>
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* - CISC processor with microcode,
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* - CISC processor with microcode,
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* - WISHBONE revision B.3 compatible MASTER interface,
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* - WISHBONE revision B.3 compatible MASTER interface,
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* - Not cycle exact with the MC68000, some instructions take more cycles to complete, some less,
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* - Not cycle exact with the MC68000, some instructions take more cycles to complete, some less,
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* - Uses about 4925 LE on Altera Cyclone II and about 45600 bits of RAM for microcode,
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* - Uses about 4750 LE on Altera Cyclone II and about 45600 bits of RAM for microcode,
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* - Tested against the WinUAE M68000 software emulator. Every 16-bit instruction was tested with random register contents and RAM contents
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* - Tested against the WinUAE M68000 software emulator. Every 16-bit instruction was tested with random register contents and RAM contents
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* (\ref page_verification). The result of execution was compared,
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* (\ref page_verification). The result of execution was compared,
|
* - Contains a simple prefetch which is capable of holding up to 5 16-bit instruction words,
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* - Contains a simple prefetch which is capable of holding up to 5 16-bit instruction words,
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* - Documentation generated by Doxygen (www.doxygen.org) with doxverilog patch (http://developer.berlios.de/projects/doxverilog/). The specification
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* - Documentation generated by Doxygen (www.doxygen.org) with doxverilog patch (http://developer.berlios.de/projects/doxverilog/). The specification
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* is automatically extracted from the Doxygen HTML output.
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* is automatically extracted from the Doxygen HTML output.
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| Line 108... |
Line 108... |
* - WISHBONE data port size: 32-bit,
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* - WISHBONE data port size: 32-bit,
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* - Data port granularity: 8-bits,
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* - Data port granularity: 8-bits,
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* - Data port maximum operand size: 32-bits,
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* - Data port maximum operand size: 32-bits,
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* - Data transfer ordering: BIG ENDIAN,
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* - Data transfer ordering: BIG ENDIAN,
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* - Data transfer sequencing: UNDEFINED,
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* - Data transfer sequencing: UNDEFINED,
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* - Constraints on <tt>CLK_I</tt> signal: described in \ref page_spec_clocks, maximum frequency: about 64 MHz.
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* - Constraints on <tt>CLK_I</tt> signal: described in \ref page_spec_clocks, maximum frequency: about 82 MHz.
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*
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*
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* <h3>Use</h3>
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* <h3>Use</h3>
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* - The ao68000 is used as the processor for the OpenCores aoOCS project - Wishbone Amiga OCS SoC(http://opencores.org/project,aoocs).
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* - The ao68000 is used as the processor for the OpenCores aoOCS project - Wishbone Amiga OCS SoC(http://opencores.org/project,aoocs).
|
* - It can also be used as a processor in a System-on-Chip booting Linux kernel version 2.6.33.1 up to <tt>init</tt> program lookup (\ref page_soc_linux).
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* - It can also be used as a processor in a System-on-Chip booting Linux kernel version 2.6.33.1 up to <tt>init</tt> program lookup (\ref page_soc_linux).
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*
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*
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| Line 370... |
Line 370... |
* <tr style="background: #CCCCCC; font-weight: bold;">
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* <tr style="background: #CCCCCC; font-weight: bold;">
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* <td rowspan=2>Name</td><td rowspan=2>Source</td><td colspan=3>Rates (MHz)</td><td rowspan=2>Remarks</td><td rowspan=2>Description</td></tr>
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* <td rowspan=2>Name</td><td rowspan=2>Source</td><td colspan=3>Rates (MHz)</td><td rowspan=2>Remarks</td><td rowspan=2>Description</td></tr>
|
* <tr style="background: #CCCCCC; font-weight: bold;">
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* <tr style="background: #CCCCCC; font-weight: bold;">
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* <td>Max</td><td>Min</td><td>Resolution</td></tr>
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* <td>Max</td><td>Min</td><td>Resolution</td></tr>
|
*
|
*
|
* <tr><td>CLK_I</td><td>Input Port</td><td>64</td><td>-</td><td>-</td><td>-</td><td>System clock.</td></tr>
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* <tr><td>CLK_I</td><td>Input Port</td><td>82</td><td>-</td><td>-</td><td>-</td><td>System clock.</td></tr>
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* </table>
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* </table>
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*/
|
*/
|
|
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/*! \page page_spec_ports IO Ports
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/*! \page page_spec_ports IO Ports
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* <h3>WISHBONE IO Ports</h3>
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* <h3>WISHBONE IO Ports</h3>
|
