| Line 494... |
Line 494... |
wire [1:0] pc_change;
|
wire [1:0] pc_change;
|
wire prefetch_ir_valid_32;
|
wire prefetch_ir_valid_32;
|
wire [3:0] ea_type;
|
wire [3:0] ea_type;
|
wire [2:0] ea_mod;
|
wire [2:0] ea_mod;
|
wire [2:0] ea_reg;
|
wire [2:0] ea_reg;
|
|
wire [17:0] decoder_alu;
|
|
wire [17:0] decoder_alu_reg;
|
|
|
bus_control bus_control_m(
|
bus_control bus_control_m(
|
.CLK_I (CLK_I),
|
.CLK_I (CLK_I),
|
.reset_n (reset_n),
|
.reset_n (reset_n),
|
.CYC_O (CYC_O),
|
.CYC_O (CYC_O),
|
| Line 625... |
Line 627... |
.An_address (An_address),
|
.An_address (An_address),
|
.An_address_control (`MICRO_DATA_an_address),
|
.An_address_control (`MICRO_DATA_an_address),
|
.An_input (An_input),
|
.An_input (An_input),
|
.An_input_control (`MICRO_DATA_an_input),
|
.An_input_control (`MICRO_DATA_an_input),
|
.Dn_address (Dn_address),
|
.Dn_address (Dn_address),
|
.Dn_address_control (`MICRO_DATA_dn_address)
|
.Dn_address_control (`MICRO_DATA_dn_address),
|
|
.decoder_alu (decoder_alu),
|
|
.decoder_alu_reg (decoder_alu_reg)
|
);
|
);
|
|
|
memory_registers memory_registers_m(
|
memory_registers memory_registers_m(
|
.clock (CLK_I),
|
.clock (CLK_I),
|
.reset_n (reset_n),
|
.reset_n (reset_n),
|
| Line 652... |
Line 656... |
.reset_n (reset_n),
|
.reset_n (reset_n),
|
.supervisor (sr[13]),
|
.supervisor (sr[13]),
|
.ir (prefetch_ir[79:64]),
|
.ir (prefetch_ir[79:64]),
|
.decoder_trap (decoder_trap),
|
.decoder_trap (decoder_trap),
|
.decoder_micropc (decoder_micropc),
|
.decoder_micropc (decoder_micropc),
|
|
.decoder_alu (decoder_alu),
|
|
|
.load_ea (load_ea),
|
.load_ea (load_ea),
|
.perform_ea_read (perform_ea_read),
|
.perform_ea_read (perform_ea_read),
|
.perform_ea_write (perform_ea_write),
|
.perform_ea_write (perform_ea_write),
|
.save_ea (save_ea),
|
.save_ea (save_ea),
|
| Line 682... |
Line 687... |
.interrupt_mask (interrupt_mask),
|
.interrupt_mask (interrupt_mask),
|
.alu_control (`MICRO_DATA_alu),
|
.alu_control (`MICRO_DATA_alu),
|
.sr (sr),
|
.sr (sr),
|
.result (result),
|
.result (result),
|
.alu_signal (alu_signal),
|
.alu_signal (alu_signal),
|
.alu_mult_div_ready (alu_mult_div_ready)
|
.alu_mult_div_ready (alu_mult_div_ready),
|
|
.decoder_alu_reg (decoder_alu_reg)
|
);
|
);
|
|
|
microcode_branch microcode_branch_m(
|
microcode_branch microcode_branch_m(
|
.clock (CLK_I),
|
.clock (CLK_I),
|
.reset_n (reset_n),
|
.reset_n (reset_n),
|
| Line 1726... |
Line 1732... |
|
|
output [31:0] An_input,
|
output [31:0] An_input,
|
input [1:0] An_input_control,
|
input [1:0] An_input_control,
|
|
|
output [2:0] Dn_address,
|
output [2:0] Dn_address,
|
input Dn_address_control
|
input Dn_address_control,
|
|
|
|
input [17:0] decoder_alu,
|
|
output reg [17:0] decoder_alu_reg
|
);
|
);
|
|
|
reg [31:0] pc_valid;
|
reg [31:0] pc_valid;
|
|
|
// pc_change connected
|
// pc_change connected
|
| Line 1914... |
Line 1923... |
else if(ir_control == `IR_LOAD_WHEN_PREFETCH_VALID && prefetch_ir_valid == 1'b1 && stop_flag == 1'b0)
|
else if(ir_control == `IR_LOAD_WHEN_PREFETCH_VALID && prefetch_ir_valid == 1'b1 && stop_flag == 1'b0)
|
ir <= prefetch_ir[79:64];
|
ir <= prefetch_ir[79:64];
|
end
|
end
|
|
|
always @(posedge clock or negedge reset_n) begin
|
always @(posedge clock or negedge reset_n) begin
|
|
if(reset_n == 1'b0) decoder_alu_reg <= 18'b0;
|
|
else if(ir_control == `IR_LOAD_WHEN_PREFETCH_VALID && prefetch_ir_valid == 1'b1 && stop_flag == 1'b0)
|
|
decoder_alu_reg <= decoder_alu;
|
|
end
|
|
|
|
always @(posedge clock or negedge reset_n) begin
|
if(reset_n == 1'b0) trap <= 8'd0;
|
if(reset_n == 1'b0) trap <= 8'd0;
|
else if(trap_control == `TRAP_ILLEGAL_INSTR) trap <= 8'd4;
|
else if(trap_control == `TRAP_ILLEGAL_INSTR) trap <= 8'd4;
|
else if(trap_control == `TRAP_DIV_BY_ZERO) trap <= 8'd5;
|
else if(trap_control == `TRAP_DIV_BY_ZERO) trap <= 8'd5;
|
else if(trap_control == `TRAP_CHK) trap <= 8'd6;
|
else if(trap_control == `TRAP_CHK) trap <= 8'd6;
|
else if(trap_control == `TRAP_TRAPV) trap <= 8'd7;
|
else if(trap_control == `TRAP_TRAPV) trap <= 8'd7;
|
| Line 2148... |
Line 2163... |
input [15:0] ir,
|
input [15:0] ir,
|
|
|
// zero: no trap
|
// zero: no trap
|
output [7:0] decoder_trap,
|
output [7:0] decoder_trap,
|
output [8:0] decoder_micropc,
|
output [8:0] decoder_micropc,
|
|
output [17:0] decoder_alu,
|
|
|
output [8:0] save_ea,
|
output [8:0] save_ea,
|
output [8:0] perform_ea_write,
|
output [8:0] perform_ea_write,
|
output [8:0] perform_ea_read,
|
output [8:0] perform_ea_read,
|
output [8:0] load_ea,
|
output [8:0] load_ea,
|
| Line 2497... |
Line 2513... |
)) ? `MICROPC_SAVE_EA_minus_An // -(An)
|
)) ? `MICROPC_SAVE_EA_minus_An // -(An)
|
:
|
:
|
9'd0 // no ea needed
|
9'd0 // no ea needed
|
;
|
;
|
|
|
|
// ALU decoding optimization
|
|
// Thanks to Frederic Requin
|
|
// not used: 7, 13, 17
|
|
assign decoder_alu[0] = ((ir[15:12] == 4'b0000 && ir[11:9] == 3'b000) // OR
|
|
|| (ir[15:12] == 4'b1000));
|
|
assign decoder_alu[1] = ((ir[15:12] == 4'b0000 && ir[11:9] == 3'b001) // AND
|
|
|| (ir[15:12] == 4'b1100));
|
|
assign decoder_alu[2] = ((ir[15:12] == 4'b0000 && ir[11:9] == 3'b101) // EOR
|
|
|| (ir[15:12] == 4'b1011 && (ir[8:7] == 2'b10 || ir[8:6] == 3'b110) && ir[5:3] != 3'b001));
|
|
assign decoder_alu[3] = ((ir[15:12] == 4'b0000 && ir[11:9] == 3'b011) // ADD
|
|
|| (ir[15:12] == 4'b1101)
|
|
|| (ir[15:12] == 4'b0101 && ir[8] == 1'b0));
|
|
assign decoder_alu[4] = ((ir[15:12] == 4'b0000 && ir[11:9] == 3'b010) // SUB
|
|
|| (ir[15:12] == 4'b1001)
|
|
|| (ir[15:12] == 4'b0101 && ir[8] == 1'b1));
|
|
assign decoder_alu[5] = ((ir[15:12] == 4'b0000 && ir[11:9] == 3'b110) // CMP
|
|
|| (ir[15:12] == 4'b1011 && (ir[8:7] == 2'b10 || ir[8:6] == 3'b110) && ir[5:3] == 3'b001)
|
|
|| (ir[15:12] == 4'b1011 && (ir[8:7] == 2'b00 || ir[8:6] == 3'b010)));
|
|
assign decoder_alu[6] = ((ir[15:12] == 4'b1101) // ADDA,ADDQ
|
|
|| (ir[15:12] == 4'b0101 && ir[8] == 1'b0));
|
|
assign decoder_alu[7] = ((ir[15:12] == 4'b1001) // SUBA,CMPA,SUBQ
|
|
|| (ir[15:12] == 4'b1011)
|
|
|| (ir[15:12] == 4'b0101 && ir[8] == 1'b1));
|
|
assign decoder_alu[8] = (((ir[7:6] == 2'b11 && ir[10:9] == 2'b00) // ASL
|
|
|| (ir[7:6] != 2'b11 && ir[4:3] == 2'b00)) && ir[8] == 1'b1);
|
|
assign decoder_alu[9] = (((ir[7:6] == 2'b11 && ir[10:9] == 2'b01) // LSL
|
|
|| (ir[7:6] != 2'b11 && ir[4:3] == 2'b01)) && ir[8] == 1'b1);
|
|
assign decoder_alu[10] = (((ir[7:6] == 2'b11 && ir[10:9] == 2'b11) // ROL
|
|
|| (ir[7:6] != 2'b11 && ir[4:3] == 2'b11)) && ir[8] == 1'b1);
|
|
assign decoder_alu[11] = (((ir[7:6] == 2'b11 && ir[10:9] == 2'b10) // ROXL
|
|
|| (ir[7:6] != 2'b11 && ir[4:3] == 2'b10)) && ir[8] == 1'b1);
|
|
assign decoder_alu[12] = (((ir[7:6] == 2'b11 && ir[10:9] == 2'b00) // ASR
|
|
|| (ir[7:6] != 2'b11 && ir[4:3] == 2'b00)) && ir[8] == 1'b0);
|
|
assign decoder_alu[13] = (((ir[7:6] == 2'b11 && ir[10:9] == 2'b01) // LSR
|
|
|| (ir[7:6] != 2'b11 && ir[4:3] == 2'b01)) && ir[8] == 1'b0);
|
|
assign decoder_alu[14] = (((ir[7:6] == 2'b11 && ir[10:9] == 2'b11) // ROR
|
|
|| (ir[7:6] != 2'b11 && ir[4:3] == 2'b11)) && ir[8] == 1'b0);
|
|
assign decoder_alu[15] = (((ir[7:6] == 2'b11 && ir[10:9] == 2'b10) // ROXR
|
|
|| (ir[7:6] != 2'b11 && ir[4:3] == 2'b10)) && ir[8] == 1'b0);
|
|
assign decoder_alu[16] = ((ir[15:8] == 8'b0100_0110) // SR operations
|
|
|| (ir[15:0] == 16'b0100_1110_0111_0011)
|
|
|| (ir[15:0] == 16'b0100_1110_0111_0010)
|
|
|| (ir[15:0] == 16'b0000_000_0_01_111100)
|
|
|| (ir[15:0] == 16'b0000_001_0_01_111100)
|
|
|| (ir[15:0] == 16'b0000_101_0_01_111100));
|
|
assign decoder_alu[17] = ((ir[15:8] == 8'b0100_0100) // CCR operations
|
|
|| (ir[15:0] == 16'b0100_1110_0111_0111)
|
|
|| (ir[15:0] == 16'b0000_000_0_00_111100)
|
|
|| (ir[15:0] == 16'b0000_001_0_00_111100)
|
|
|| (ir[15:0] == 16'b0000_101_0_00_111100));
|
|
|
endmodule
|
endmodule
|
|
|
/***********************************************************************************************************************
|
/***********************************************************************************************************************
|
* Condition
|
* Condition
|
**********************************************************************************************************************/
|
**********************************************************************************************************************/
|
| Line 2574... |
Line 2641... |
|
|
output reg [15:0] sr,
|
output reg [15:0] sr,
|
output reg [31:0] result,
|
output reg [31:0] result,
|
|
|
output reg alu_signal,
|
output reg alu_signal,
|
output alu_mult_div_ready
|
output alu_mult_div_ready,
|
|
input [17:0] decoder_alu_reg
|
);
|
);
|
|
|
//****************************************************** Altera-specific multiplication and division modules START
|
//****************************************************** Altera-specific multiplication and division modules START
|
/* Multiplication and division modules.
|
/* Multiplication and division modules.
|
*
|
*
|
| Line 2695... |
Line 2763... |
// ALU operations
|
// ALU operations
|
|
|
reg [2:0] interrupt_mask_copy;
|
reg [2:0] interrupt_mask_copy;
|
reg was_interrupt;
|
reg was_interrupt;
|
|
|
|
// Bit being shifted left
|
|
wire lbit = (`Dm & decoder_alu_reg[10]) | (sr[4] & decoder_alu_reg[11]);
|
|
// Bit being shifted right
|
|
wire rbit = (`Dm & decoder_alu_reg[12]) | (operand1[0] & decoder_alu_reg[14]) | (sr[4] & decoder_alu_reg[15]);
|
|
|
always @(posedge clock or negedge reset_n) begin
|
always @(posedge clock or negedge reset_n) begin
|
if(reset_n == 1'b0) begin
|
if(reset_n == 1'b0) begin
|
sr <= { 1'b0, 1'b0, 1'b1, 2'b0, 3'b111, 8'b0 };
|
sr <= { 1'b0, 1'b0, 1'b1, 2'b0, 3'b111, 8'b0 };
|
result <= 32'd0;
|
result <= 32'd0;
|
alu_signal <= 1'b0;
|
alu_signal <= 1'b0;
|
| Line 2759... |
Line 2832... |
`ALU_MOVEP_R2M_4: begin
|
`ALU_MOVEP_R2M_4: begin
|
result[7:0] <= operand1[7:0];
|
result[7:0] <= operand1[7:0];
|
// CCR: no change
|
// CCR: no change
|
end
|
end
|
|
|
|
|
|
|
`ALU_SIGN_EXTEND: begin
|
`ALU_SIGN_EXTEND: begin
|
// move operand1 with sign-extension to result
|
// move operand1 with sign-extension to result
|
if(size[1] == 1'b1) begin
|
if(size[1] == 1'b1) begin
|
result <= { {16{operand1[15]}}, operand1[15:0] };
|
result <= { {16{operand1[15]}}, operand1[15:0] };
|
end
|
end
|
| Line 2775... |
Line 2846... |
end
|
end
|
|
|
`ALU_ARITHMETIC_LOGIC: begin
|
`ALU_ARITHMETIC_LOGIC: begin
|
|
|
// OR,OR to mem,OR to Dn
|
// OR,OR to mem,OR to Dn
|
if( (ir[15:12] == 4'b0000 && ir[11:9] == 3'b000) ||
|
if(decoder_alu_reg[0]) result[31:0] = operand1[31:0] | operand2[31:0];
|
(ir[15:12] == 4'b1000)
|
|
) result[31:0] = operand1[31:0] | operand2[31:0];
|
|
// AND,AND to mem,AND to Dn
|
// AND,AND to mem,AND to Dn
|
else if( (ir[15:12] == 4'b0000 && ir[11:9] == 3'b001) ||
|
else if(decoder_alu_reg[1]) result[31:0] = operand1[31:0] & operand2[31:0];
|
(ir[15:12] == 4'b1100)
|
|
) result[31:0] = operand1[31:0] & operand2[31:0];
|
|
// EORI,EOR
|
// EORI,EOR
|
else if( (ir[15:12] == 4'b0000 && ir[11:9] == 3'b101) ||
|
else if(decoder_alu_reg[2]) result[31:0] = operand1[31:0] ^ operand2[31:0];
|
(ir[15:12] == 4'b1011 && (ir[8:6] == 3'b100 || ir[8:6] == 3'b101 || ir[8:6] == 3'b110) && ir[5:3] != 3'b001)
|
|
) result[31:0] = operand1[31:0] ^ operand2[31:0];
|
|
// ADD,ADD to mem,ADD to Dn,ADDQ
|
// ADD,ADD to mem,ADD to Dn,ADDQ
|
else if( (ir[15:12] == 4'b0000 && ir[11:9] == 3'b011) ||
|
else if(decoder_alu_reg[3]) result[31:0] = operand1[31:0] + operand2[31:0];
|
(ir[15:12] == 4'b1101) ||
|
|
(ir[15:12] == 4'b0101 && ir[8] == 1'b0)
|
|
) result[31:0] = operand1[31:0] + operand2[31:0];
|
|
// SUBI,CMPI,CMPM,SUB to mem,SUB to Dn,CMP,SUBQ
|
// SUBI,CMPI,CMPM,SUB to mem,SUB to Dn,CMP,SUBQ
|
else if( (ir[15:12] == 4'b0000 && ir[11:9] == 3'b010) ||
|
else if(decoder_alu_reg[4] | decoder_alu_reg[5]) result[31:0] = operand1[31:0] - operand2[31:0];
|
(ir[15:12] == 4'b0000 && ir[11:9] == 3'b110) ||
|
|
(ir[15:12] == 4'b1011 && (ir[8:6] == 3'b100 || ir[8:6] == 3'b101 || ir[8:6] == 3'b110) && ir[5:3] == 3'b001) ||
|
|
(ir[15:12] == 4'b1001) ||
|
|
(ir[15:12] == 4'b1011 && (ir[8:6] == 3'b000 || ir[8:6] == 3'b001 || ir[8:6] == 3'b010)) ||
|
|
(ir[15:12] == 4'b0101 && ir[8] == 1'b1)
|
|
) result[31:0] = operand1[31:0] - operand2[31:0];
|
|
|
|
// Z
|
// Z
|
sr[2] <= `Z;
|
sr[2] <= `Z;
|
// N
|
// N
|
sr[3] <= `Rm;
|
sr[3] <= `Rm;
|
|
|
// CMPI,CMPM,CMP
|
// CMPI,CMPM,CMP
|
if( (ir[15:12] == 4'b0000 && ir[11:9] == 3'b110) ||
|
if(decoder_alu_reg[5]) begin
|
(ir[15:12] == 4'b1011 && (ir[8:6] == 3'b100 || ir[8:6] == 3'b101 || ir[8:6] == 3'b110) && ir[5:3] == 3'b001) ||
|
|
(ir[15:12] == 4'b1011 && (ir[8:6] == 3'b000 || ir[8:6] == 3'b001 || ir[8:6] == 3'b010))
|
|
) begin
|
|
// C,V
|
// C,V
|
sr[0] <= (`Sm & ~`Dm) | (`Rm & ~`Dm) | (`Sm & `Rm);
|
sr[0] <= (`Sm & ~`Dm) | (`Rm & ~`Dm) | (`Sm & `Rm);
|
sr[1] <= (~`Sm & `Dm & ~`Rm) | (`Sm & ~`Dm & `Rm);
|
sr[1] <= (~`Sm & `Dm & ~`Rm) | (`Sm & ~`Dm & `Rm);
|
// X not affected
|
// X not affected
|
end
|
end
|
// ADDI,ADD to mem,ADD to Dn,ADDQ
|
// ADDI,ADD to mem,ADD to Dn,ADDQ
|
else if( (ir[15:12] == 4'b0000 && ir[11:9] == 3'b011) ||
|
else if(decoder_alu_reg[3]) begin
|
(ir[15:12] == 4'b1101) ||
|
|
(ir[15:12] == 4'b0101 && ir[8] == 1'b0)
|
|
) begin
|
|
// C,X,V
|
// C,X,V
|
sr[0] <= (`Sm & `Dm) | (~`Rm & `Dm) | (`Sm & ~`Rm);
|
sr[0] <= (`Sm & `Dm) | (~`Rm & `Dm) | (`Sm & ~`Rm);
|
sr[4] <= (`Sm & `Dm) | (~`Rm & `Dm) | (`Sm & ~`Rm); //=ccr[0];
|
sr[4] <= (`Sm & `Dm) | (~`Rm & `Dm) | (`Sm & ~`Rm); //=ccr[0];
|
sr[1] <= (`Sm & `Dm & ~`Rm) | (~`Sm & ~`Dm & `Rm);
|
sr[1] <= (`Sm & `Dm & ~`Rm) | (~`Sm & ~`Dm & `Rm);
|
end
|
end
|
// SUBI,SUB to mem,SUB to Dn,SUBQ
|
// SUBI,SUB to mem,SUB to Dn,SUBQ
|
else if( (ir[15:12] == 4'b0000 && ir[11:9] == 3'b010) ||
|
else if(decoder_alu_reg[4]) begin
|
(ir[15:12] == 4'b1001) ||
|
|
(ir[15:12] == 4'b0101 && ir[8] == 1'b1)
|
|
) begin
|
|
// C,X,V
|
// C,X,V
|
sr[0] <= (`Sm & ~`Dm) | (`Rm & ~`Dm) | (`Sm & `Rm);
|
sr[0] <= (`Sm & ~`Dm) | (`Rm & ~`Dm) | (`Sm & `Rm);
|
sr[4] <= (`Sm & ~`Dm) | (`Rm & ~`Dm) | (`Sm & `Rm); //=ccr[0];
|
sr[4] <= (`Sm & ~`Dm) | (`Rm & ~`Dm) | (`Sm & `Rm); //=ccr[0];
|
sr[1] <= (~`Sm & `Dm & ~`Rm) | (`Sm & ~`Dm & `Rm);
|
sr[1] <= (~`Sm & `Dm & ~`Rm) | (`Sm & ~`Dm & `Rm);
|
end
|
end
|
| Line 2871... |
Line 2918... |
// V
|
// V
|
sr[1] <= (result[30] == 1'b0 && result[7] == 1'b1) ? 1'b1 : 1'b0;
|
sr[1] <= (result[30] == 1'b0 && result[7] == 1'b1) ? 1'b1 : 1'b0;
|
end
|
end
|
// SBCD
|
// SBCD
|
else if( ir[14:12] == 3'b000 ) begin
|
else if( ir[14:12] == 3'b000 ) begin
|
|
|
result[13:8] = 6'd32 + {2'b0, operand1[3:0]} - {2'b0, operand2[3:0]} - {5'b0, sr[4]};
|
result[13:8] = 6'd32 + {2'b0, operand1[3:0]} - {2'b0, operand2[3:0]} - {5'b0, sr[4]};
|
result[19:14] = 6'd32 + {2'b0, operand1[7:4]} - {2'b0, operand2[7:4]};
|
result[19:14] = 6'd32 + {2'b0, operand1[7:4]} - {2'b0, operand2[7:4]};
|
|
|
result[31:23] = operand1[7:0] - operand2[7:0] - {7'b0, sr[4]};
|
result[31:23] = operand1[7:0] - operand2[7:0] - {7'b0, sr[4]};
|
|
|
| Line 2921... |
Line 2967... |
sr[1] <= (~`Sm & `Dm & ~`Rm) | (`Sm & ~`Dm & `Rm);
|
sr[1] <= (~`Sm & `Dm & ~`Rm) | (`Sm & ~`Dm & `Rm);
|
end
|
end
|
end
|
end
|
|
|
`ALU_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR_prepare: begin
|
`ALU_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR_prepare: begin
|
|
// 32-bit load even for 8-bit and 16-bit operations
|
if(size[0] == 1'b1) result[7:0] = operand1[7:0];
|
// The extra bits will be anyway discarded during register / memory write
|
else if(size[1] == 1'b1) result[15:0] = operand1[15:0];
|
result[31:0] = operand1[31:0];
|
else if(size[2] == 1'b1) result[31:0] = operand1[31:0];
|
|
|
|
// X for ASL
|
|
//if(operand2[5:0] > 6'b0 && ir[8] == 1'b1 && ((ir[7:6] == 2'b11 && ir[10:9] == 2'b00) || (ir[7:6] != 2'b11 && ir[4:3] == 2'b00)) ) begin
|
|
// X set to Dm
|
|
// sr[4] <= `Dm;
|
|
//end
|
|
// else X not affected
|
|
|
|
// V cleared
|
// V cleared
|
sr[1] <= 1'b0;
|
sr[1] <= 1'b0;
|
// C for ROXL,ROXR: set to X
|
// C for ROXL,ROXR: set to X
|
if( (ir[7:6] == 2'b11 && ir[10:9] == 2'b10) || (ir[7:6] != 2'b11 && ir[4:3] == 2'b10) ) begin
|
if(decoder_alu_reg[11] | decoder_alu_reg[15]) begin
|
sr[0] <= sr[4];
|
sr[0] <= sr[4];
|
end
|
end
|
else begin
|
else begin
|
// C cleared
|
// C cleared
|
sr[0] <= 1'b0;
|
sr[0] <= 1'b0;
|
| Line 2951... |
Line 2989... |
// Z set
|
// Z set
|
sr[2] <= `Z;
|
sr[2] <= `Z;
|
end
|
end
|
|
|
`ALU_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR: begin
|
`ALU_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR: begin
|
|
// ASL / LSL / ROL / ROXL
|
// ASL
|
if (decoder_alu_reg[8] | decoder_alu_reg[9] | decoder_alu_reg[10] | decoder_alu_reg[11]) begin
|
if( ((ir[7:6] == 2'b11 && ir[10:9] == 2'b00) || (ir[7:6] != 2'b11 && ir[4:3] == 2'b00)) && ir[8] == 1'b1) begin
|
result[31:0] = {operand1[30:0], lbit};
|
result[31:0] = {operand1[30:0], 1'b0};
|
|
|
sr[0] <= `Dm; // C for ASL / LSL / ROL / ROXL
|
sr[1] <= (sr[1] == 1'b0)? (`Rm != `Dm) : 1'b1; // V
|
if (decoder_alu_reg[8])
|
sr[0] <= `Dm; // C
|
sr[1] <= (sr[1] == 1'b0)? (`Rm != `Dm) : 1'b1; // V for ASL
|
sr[4] <= `Dm; // X
|
else
|
end
|
sr[1] <= 1'b0; // V for LSL / ROL / ROXL
|
// LSL
|
|
else if( ((ir[7:6] == 2'b11 && ir[10:9] == 2'b01) || (ir[7:6] != 2'b11 && ir[4:3] == 2'b01)) && ir[8] == 1'b1) begin
|
if (!decoder_alu_reg[10]) sr[4] <= `Dm; // X for ASL / LSL / ROXL
|
result[31:0] = {operand1[30:0], 1'b0};
|
end
|
|
// ASR / LSR / ROR / ROXR
|
sr[1] <= 1'b0; // V
|
else begin
|
sr[0] <= `Dm; // C
|
result[6:0] = operand1[7:1];
|
sr[4] <= `Dm; // X
|
result[7] = (size[0]) ? rbit : operand1[8];
|
end
|
result[14:8] = operand1[15:9];
|
// ROL
|
result[15] = (size[1]) ? rbit : operand1[16];
|
else if( ((ir[7:6] == 2'b11 && ir[10:9] == 2'b11) || (ir[7:6] != 2'b11 && ir[4:3] == 2'b11)) && ir[8] == 1'b1) begin
|
result[30:16] = operand1[31:17];
|
result[31:0] = {operand1[30:0], `Dm};
|
result[31] = rbit;
|
|
sr[0] <= operand1[0]; // C for ASR / LSR / ROR / ROXR
|
sr[1] <= 1'b0; // V
|
sr[1] <= 1'b0; // V for ASR / LSR / ROR / ROXR
|
sr[0] <= `Dm; // C
|
if (!decoder_alu_reg[14]) sr[4] <= operand1[0]; // X for ASR / LSR / ROXR
|
// X not affected
|
|
end
|
|
// ROXL
|
|
else if( ((ir[7:6] == 2'b11 && ir[10:9] == 2'b10) || (ir[7:6] != 2'b11 && ir[4:3] == 2'b10)) && ir[8] == 1'b1) begin
|
|
result[31:0] = {operand1[30:0], sr[4]};
|
|
|
|
sr[1] <= 1'b0; // V
|
|
sr[0] <= `Dm; // C
|
|
sr[4] <= `Dm; // X
|
|
end
|
|
// ASR
|
|
else if( ((ir[7:6] == 2'b11 && ir[10:9] == 2'b00) || (ir[7:6] != 2'b11 && ir[4:3] == 2'b00)) && ir[8] == 1'b0) begin
|
|
if(size[0] == 1'b1) result[7:0] = { operand1[7], operand1[7:1] };
|
|
else if(size[1] == 1'b1) result[15:0] = { operand1[15], operand1[15:1] };
|
|
else if(size[2] == 1'b1) result[31:0] = { operand1[31], operand1[31:1] };
|
|
|
|
sr[1] <= 1'b0; // V
|
|
sr[0] <= operand1[0]; // C
|
|
sr[4] <= operand1[0]; // X
|
|
end
|
|
// LSR
|
|
else if( ((ir[7:6] == 2'b11 && ir[10:9] == 2'b01) || (ir[7:6] != 2'b11 && ir[4:3] == 2'b01)) && ir[8] == 1'b0) begin
|
|
if(size[0] == 1'b1) result[7:0] = { 1'b0, operand1[7:1] };
|
|
else if(size[1] == 1'b1) result[15:0] = { 1'b0, operand1[15:1] };
|
|
else if(size[2] == 1'b1) result[31:0] = { 1'b0, operand1[31:1] };
|
|
|
|
sr[1] <= 1'b0; // V
|
|
sr[0] <= operand1[0]; // C
|
|
sr[4] <= operand1[0]; // X
|
|
end
|
|
// ROR
|
|
else if( ((ir[7:6] == 2'b11 && ir[10:9] == 2'b11) || (ir[7:6] != 2'b11 && ir[4:3] == 2'b11)) && ir[8] == 1'b0) begin
|
|
if(size[0] == 1'b1) result[7:0] = { operand1[0], operand1[7:1] };
|
|
else if(size[1] == 1'b1) result[15:0] = { operand1[0], operand1[15:1] };
|
|
else if(size[2] == 1'b1) result[31:0] = { operand1[0], operand1[31:1] };
|
|
|
|
sr[1] <= 1'b0; // V
|
|
sr[0] <= operand1[0]; // C
|
|
// X not affected
|
|
end
|
|
// ROXR
|
|
else if( ((ir[7:6] == 2'b11 && ir[10:9] == 2'b10) || (ir[7:6] != 2'b11 && ir[4:3] == 2'b10)) && ir[8] == 1'b0) begin
|
|
if(size[0] == 1'b1) result[7:0] = {sr[4], operand1[7:1]};
|
|
else if(size[1] == 1'b1) result[15:0] = {sr[4], operand1[15:1]};
|
|
else if(size[2] == 1'b1) result[31:0] = {sr[4], operand1[31:1]};
|
|
|
|
sr[1] <= 1'b0; // V
|
|
sr[0] <= operand1[0]; // C
|
|
sr[4] <= operand1[0]; // X
|
|
end
|
end
|
|
|
// N set
|
// N set
|
sr[3] <= `Rm;
|
sr[3] <= `Rm;
|
// Z set
|
// Z set
|
| Line 3054... |
Line 3043... |
// SUBA: 1001
|
// SUBA: 1001
|
// ADDQ,SUBQ: 0101 xxx0,1
|
// ADDQ,SUBQ: 0101 xxx0,1
|
// operation requires that operand2 was sign extended
|
// operation requires that operand2 was sign extended
|
|
|
// ADDA,ADDQ
|
// ADDA,ADDQ
|
if( ir[15:12] == 4'b1101 || (ir[15:12] == 4'b0101 && ir[8] == 1'b0) )
|
if(decoder_alu_reg[6]) result[31:0] = operand1[31:0] + operand2[31:0];
|
result[31:0] = operand1[31:0] + operand2[31:0];
|
|
// SUBA,CMPA,SUBQ
|
// SUBA,CMPA,SUBQ
|
else if( ir[15:12] == 4'b1001 || ir[15:12] == 4'b1011 || (ir[15:12] == 4'b0101 && ir[8] == 1'b1) )
|
else result[31:0] = operand1[31:0] - operand2[31:0];
|
result[31:0] = operand1[31:0] - operand2[31:0];
|
|
|
|
// for CMPA
|
// for CMPA
|
if( ir[15:12] == 4'b1011 ) begin
|
if( ir[15:12] == 4'b1011 ) begin
|
// Z
|
// Z
|
sr[2] <= `Z;
|
sr[2] <= `Z;
|
| Line 3216... |
Line 3203... |
end
|
end
|
|
|
|
|
`ALU_NEGX_CLR_NEG_NOT_NBCD_SWAP_EXT: begin
|
`ALU_NEGX_CLR_NEG_NOT_NBCD_SWAP_EXT: begin
|
// NEGX / CLR / NEG / NOT
|
// NEGX / CLR / NEG / NOT
|
|
// Optimization thanks to Frederic Requin
|
if ((ir[11:8] == 4'b0000) || (ir[11:8] == 4'b0010) || (ir[11:8] == 4'b0100) || (ir[11:8] == 4'b0110))
|
if ((ir[11:8] == 4'b0000) || (ir[11:8] == 4'b0010) || (ir[11:8] == 4'b0100) || (ir[11:8] == 4'b0110))
|
result = 32'b0 - (operand1[31:0] & {32{ir[10] | ~ir[9]}}) - ((sr[4] & ~ir[10] & ~ir[9]) | (ir[10] & ir[9]));
|
result = 32'b0 - (operand1[31:0] & {32{ir[10] | ~ir[9]}}) - ((sr[4] & ~ir[10] & ~ir[9]) | (ir[10] & ir[9]));
|
// NBCD
|
// NBCD
|
else if( ir[11:6] == 6'b1000_00 ) begin
|
else if( ir[11:6] == 6'b1000_00 ) begin
|
|
|
result[3:0] = 5'd25 - operand1[3:0];
|
result[3:0] = 5'd25 - operand1[3:0];
|
result[7:4] = (operand1[3:0] > 4'd9) ? (5'd24 - operand1[7:4]) : (5'd25 - operand1[7:4]);
|
result[7:4] = (operand1[3:0] > 4'd9) ? (5'd24 - operand1[7:4]) : (5'd25 - operand1[7:4]);
|
|
|
if(sr[4] == 1'b0 && result[3:0] == 4'd9 && result[7:4] == 4'd9) begin
|
if(sr[4] == 1'b0 && result[3:0] == 4'd9 && result[7:4] == 4'd9) begin
|
result[3:0] = 4'd0;
|
result[3:0] = 4'd0;
|
| Line 3302... |
Line 3289... |
end
|
end
|
|
|
`ALU_MOVE_TO_CCR_SR_RTE_RTR_STOP_LOGIC_TO_CCR_SR: begin
|
`ALU_MOVE_TO_CCR_SR_RTE_RTR_STOP_LOGIC_TO_CCR_SR: begin
|
|
|
// MOVE TO SR,RTE,STOP,ORI to SR,ANDI to SR,EORI to SR
|
// MOVE TO SR,RTE,STOP,ORI to SR,ANDI to SR,EORI to SR
|
if( ir[15:8] == 8'b0100_0110 || ir[15:0] == 16'b0100_1110_0111_0011 || ir[15:0] == 16'b0100_1110_0111_0010 ||
|
if(decoder_alu_reg[16]) sr <= { operand1[15], 1'b0, operand1[13], 2'b0, operand1[10:8], 3'b0, operand1[4:0] };
|
ir[15:0] == 16'b0000_000_0_01_111100 || ir[15:0] == 16'b0000_001_0_01_111100 || ir[15:0] == 16'b0000_101_0_01_111100
|
|
) sr <= { operand1[15], 1'b0, operand1[13], 2'b0, operand1[10:8], 3'b0, operand1[4:0] };
|
|
// MOVE TO CCR,RTR,ORI to CCR,ANDI to CCR,EORI to CCR
|
// MOVE TO CCR,RTR,ORI to CCR,ANDI to CCR,EORI to CCR
|
else if( ir[15:8] == 8'b0100_0100 || ir[15:0] == 16'b0100_1110_0111_0111 ||
|
else sr <= { sr[15:8], 3'b0, operand1[4:0] };
|
ir[15:0] == 16'b0000_000_0_00_111100 || ir[15:0] == 16'b0000_001_0_00_111100 || ir[15:0] == 16'b0000_101_0_00_111100
|
|
) sr <= { sr[15:8], 3'b0, operand1[4:0] };
|
|
end
|
end
|
|
|
`ALU_SIMPLE_MOVE: begin
|
`ALU_SIMPLE_MOVE: begin
|
result <= operand1;
|
result <= operand1;
|
|
|
