| Line 63... |
Line 63... |
//
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//
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//
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//
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//////////////////////////////////////
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//////////////////////////////////////
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OUTFILE apb_master.v
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OUTFILE PREFIX.v
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INCLUDE def_apb_master.txt
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INCLUDE def_apb_master.txt
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VERIFY (DATA_BITS==32) else only 32 bit data supported
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VERIFY (DATA_BITS==32) else only 32 bit data supported
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module apb_master(PORTS);
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module PREFIX(PORTS);
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input clk;
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input clk;
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input reset;
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input reset;
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| Line 97... |
Line 97... |
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//set random tasks to be only 32 bit singles
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//set random tasks to be only 32 bit singles
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initial
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initial
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begin
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begin
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#1;
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#1;
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apb_master_axi_master.enable_all;
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PREFIX_axi_master.enable_all;
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apb_master_axi_master.use_addr_base=1;
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PREFIX_axi_master.use_addr_base=1;
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apb_master_axi_master.len_min=0;
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PREFIX_axi_master.len_min=0;
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apb_master_axi_master.len_max=0;
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PREFIX_axi_master.len_max=0;
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apb_master_axi_master.size_min=2;
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PREFIX_axi_master.size_min=2;
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apb_master_axi_master.size_max=2;
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PREFIX_axi_master.size_max=2;
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end
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end
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CREATE axi_master.v DEFCMD(SWAP.GLOBAL CONST(PREFIX) apb_master_axi_master)
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CREATE axi_master.v DEFCMD(SWAP.GLOBAL CONST(PREFIX) PREFIX_axi_master)
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apb_master_axi_master apb_master_axi_master(
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PREFIX_axi_master PREFIX_axi_master(
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.GROUP_STUB_AXI(GROUP_STUB_AXI),
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.GROUP_STUB_AXI(GROUP_STUB_AXI),
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.idle()
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.idle()
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);
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);
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CREATE axi2apb.v DEFCMD(SWAP CONST(SLAVE_NUM) 1) DEFCMD(SWAP.GLOBAL CONST(PREFIX) apb_master)
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CREATE axi2apb.v DEFCMD(SWAP CONST(SLAVE_NUM) 1) DEFCMD(SWAP.GLOBAL CONST(PREFIX) PREFIX_axi2apb)
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apb_master_axi2apb apb_master_axi2apb(
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PREFIX_axi2apb PREFIX_axi2apb(
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.GROUP_STUB_AXI(GROUP_STUB_AXI),
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.GROUP_STUB_AXI(GROUP_STUB_AXI),
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.penable(penable),
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.penable(penable),
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| Line 138... |
Line 138... |
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task write_single;
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task write_single;
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input [ADDR_BITS-1:0] addr;
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input [ADDR_BITS-1:0] addr;
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input [DATA_BITS-1:0] wdata;
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input [DATA_BITS-1:0] wdata;
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begin
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begin
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apb_master_axi_master.write_single(0, addr, wdata);
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PREFIX_axi_master.write_single(0, addr, wdata);
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end
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end
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endtask
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endtask
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task read_single;
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task read_single;
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input [ADDR_BITS-1:0] addr;
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input [ADDR_BITS-1:0] addr;
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output [DATA_BITS-1:0] rdata;
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output [DATA_BITS-1:0] rdata;
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begin
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begin
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apb_master_axi_master.read_single(0, addr, rdata);
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PREFIX_axi_master.read_single(0, addr, rdata);
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end
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end
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endtask
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endtask
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task check_single;
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task check_single;
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input [ADDR_BITS-1:0] addr;
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input [ADDR_BITS-1:0] addr;
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input [DATA_BITS-1:0] expected;
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input [DATA_BITS-1:0] expected;
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begin
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begin
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apb_master_axi_master.check_single(0, addr, expected);
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PREFIX_axi_master.check_single(0, addr, expected);
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end
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end
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endtask
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endtask
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task write_and_check_single;
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task write_and_check_single;
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input [ADDR_BITS-1:0] addr;
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input [ADDR_BITS-1:0] addr;
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input [DATA_BITS-1:0] data;
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input [DATA_BITS-1:0] data;
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begin
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begin
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apb_master_axi_master.write_and_check_single(0, addr, data);
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PREFIX_axi_master.write_and_check_single(0, addr, data);
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end
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end
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endtask
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endtask
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endmodule
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endmodule
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