| Line 101... |
Line 101... |
// insert_rand_chk(input master_num, input burst_num)
|
// insert_rand_chk(input master_num, input burst_num)
|
// Description: add multiple commands to command FIFO. Each command writes incremental data to a random address, reads the data back and checks the data. Useful for random testing.
|
// Description: add multiple commands to command FIFO. Each command writes incremental data to a random address, reads the data back and checks the data. Useful for random testing.
|
// Parameters: master_num - number of internal master
|
// Parameters: master_num - number of internal master
|
// burst_num - total number of bursts to check
|
// burst_num - total number of bursts to check
|
//
|
//
|
|
// insert_rand(input burst_num)
|
|
// Description: disperces burst_num between internal masters and calls insert_rand_chk for each master
|
|
// Parameters: burst_num - total number of bursts to check (combined)
|
|
//
|
//
|
//
|
// Parameters:
|
// Parameters:
|
//
|
//
|
// For random testing: (changing these values automatically update interanl masters)
|
// For random testing: (changing these values automatically update interanl masters)
|
|
// ahb_bursts - if set, bursts will only be of length 1, 4, 8 or 16.
|
// len_min - minimum burst AXI LEN (length)
|
// len_min - minimum burst AXI LEN (length)
|
// len_max - maximum burst AXI LEN (length)
|
// len_max - maximum burst AXI LEN (length)
|
// size_min - minimum burst AXI SIZE (width)
|
// size_min - minimum burst AXI SIZE (width)
|
// size_max - maximum burst AXI SIZE (width)
|
// size_max - maximum burst AXI SIZE (width)
|
// addr_min - minimum address (in bytes)
|
// addr_min - minimum address (in bytes)
|
| Line 119... |
Line 123... |
|
|
OUTFILE PREFIX.v
|
OUTFILE PREFIX.v
|
|
|
INCLUDE def_axi_master.txt
|
INCLUDE def_axi_master.txt
|
|
|
|
ITER IDX ID_NUM
|
ITER IX ID_NUM
|
|
module PREFIX(PORTS);
|
module PREFIX(PORTS);
|
|
|
|
`include "prgen_rand.v"
|
|
|
input clk;
|
input clk;
|
input reset;
|
input reset;
|
|
|
port GROUP_STUB_AXI;
|
port GROUP_STUB_AXI;
|
|
|
| Line 135... |
Line 140... |
|
|
|
|
//random parameters
|
//random parameters
|
integer GROUP_AXI_MASTER_RAND = GROUP_AXI_MASTER_RAND.DEFAULT;
|
integer GROUP_AXI_MASTER_RAND = GROUP_AXI_MASTER_RAND.DEFAULT;
|
|
|
wire GROUP_STUB_AXI_IX;
|
wire GROUP_STUB_AXI_IDX;
|
wire idle_IX;
|
wire idle_IDX;
|
wire scrbrd_empty_IX;
|
wire scrbrd_empty_IDX;
|
|
|
|
|
always @(*)
|
always @(*)
|
begin
|
begin
|
#FFD;
|
#FFD;
|
PREFIX_singleIX.GROUP_AXI_MASTER_RAND = GROUP_AXI_MASTER_RAND;
|
PREFIX_singleIDX.GROUP_AXI_MASTER_RAND = GROUP_AXI_MASTER_RAND;
|
end
|
end
|
|
|
assign idle = CONCAT(idle_IX &);
|
assign idle = CONCAT(idle_IDX &);
|
assign scrbrd_empty = CONCAT(scrbrd_empty_IX &);
|
assign scrbrd_empty = CONCAT(scrbrd_empty_IDX &);
|
|
|
|
|
CREATE axi_master_single.v
|
CREATE axi_master_single.v
|
|
|
LOOP IX ID_NUM
|
LOOP IDX ID_NUM
|
PREFIX_single #(IX, IDIX_VAL, CMD_DEPTH)
|
PREFIX_single #(IDX, ID_BITS'GROUP_AXI_ID[IDX], CMD_DEPTH)
|
PREFIX_singleIX(
|
PREFIX_singleIDX(
|
.clk(clk),
|
.clk(clk),
|
.reset(reset),
|
.reset(reset),
|
.GROUP_STUB_AXI(GROUP_STUB_AXI_IX),
|
.GROUP_STUB_AXI(GROUP_STUB_AXI_IDX),
|
.idle(idle_IX),
|
.idle(idle_IDX),
|
.scrbrd_empty(scrbrd_empty_IX)
|
.scrbrd_empty(scrbrd_empty_IDX)
|
);
|
);
|
ENDLOOP IX
|
|
|
ENDLOOP IDX
|
|
|
IFDEF TRUE(ID_NUM==1)
|
IFDEF TRUE(ID_NUM==1)
|
|
|
assign GROUP_STUB_AXI.OUT = GROUP_STUB_AXI_0.OUT;
|
assign GROUP_STUB_AXI.OUT = GROUP_STUB_AXI_0.OUT;
|
assign GROUP_STUB_AXI_0.IN = GROUP_STUB_AXI.IN;
|
assign GROUP_STUB_AXI_0.IN = GROUP_STUB_AXI.IN;
|
|
|
ELSE TRUE(ID_NUM==1)
|
ELSE TRUE(ID_NUM==1)
|
|
|
CREATE ic.v DEFCMD(SWAP.GLOBAL PARENT PREFIX) DEFCMD(SWAP.GLOBAL MASTER_NUM ID_NUM) DEFCMD(SWAP.GLOBAL CONST(ID_BITS) ID_BITS) DEFCMD(SWAP.GLOBAL CONST(CMD_DEPTH) CMD_DEPTH) DEFCMD(SWAP.GLOBAL CONST(DATA_BITS) DATA_BITS) DEFCMD(SWAP.GLOBAL CONST(ADDR_BITS) ADDR_BITS)
|
CREATE ic.v \\
|
LOOP IX ID_NUM
|
DEFCMD(SWAP.GLOBAL CONST(PREFIX) PREFIX) \\
|
STOMP NEWLINE
|
DEFCMD(SWAP.GLOBAL MASTER_NUM ID_NUM) \\
|
DEFCMD(LOOP.GLOBAL MIX_IDX 1)
|
DEFCMD(SWAP.GLOBAL SLAVE_NUM 1) \\
|
|
DEFCMD(SWAP.GLOBAL CONST(ID_BITS) ID_BITS) \\
|
|
DEFCMD(SWAP.GLOBAL CONST(CMD_DEPTH) CMD_DEPTH) \\
|
|
DEFCMD(SWAP.GLOBAL CONST(DATA_BITS) DATA_BITS) \\
|
|
DEFCMD(SWAP.GLOBAL CONST(ADDR_BITS) ADDR_BITS) \\
|
|
DEFCMD(SWAP.GLOBAL CONST(USER_BITS) 0)
|
|
LOOP IDX ID_NUM
|
STOMP NEWLINE
|
STOMP NEWLINE
|
DEFCMD(SWAP.GLOBAL ID_MIX_ID0 IDIX_VAL)
|
DEFCMD(GROUP.GLOBAL MIDX_ID overrides { ) \\
|
ENDLOOP IX
|
DEFCMD(GROUP_AXI_ID[IDX]) \\
|
|
DEFCMD(})
|
|
ENDLOOP IDX
|
|
|
|
|
PREFIX_ic PREFIX_ic(
|
PREFIX_ic PREFIX_ic(
|
.clk(clk),
|
.clk(clk),
|
.reset(reset),
|
.reset(reset),
|
.MIX_GROUP_STUB_AXI(GROUP_STUB_AXI_IX),
|
.MIDX_GROUP_STUB_AXI(GROUP_STUB_AXI_IDX),
|
.S0_GROUP_STUB_AXI(GROUP_STUB_AXI),
|
.S0_GROUP_STUB_AXI(GROUP_STUB_AXI),
|
STOMP ,
|
STOMP ,
|
|
|
);
|
);
|
|
|
| Line 207... |
Line 222... |
task enable;
|
task enable;
|
input [31:0] master_num;
|
input [31:0] master_num;
|
begin
|
begin
|
check_master_num("enable", master_num);
|
check_master_num("enable", master_num);
|
case (master_num)
|
case (master_num)
|
IX : PREFIX_singleIX.enable = 1;
|
IDX : PREFIX_singleIDX.enable = 1;
|
endcase
|
endcase
|
end
|
end
|
endtask
|
endtask
|
|
|
task enable_all;
|
task enable_all;
|
begin
|
begin
|
PREFIX_singleIX.enable = 1;
|
PREFIX_singleIDX.enable = 1;
|
end
|
end
|
endtask
|
endtask
|
|
|
task write_single;
|
task write_single;
|
input [31:0] master_num;
|
input [31:0] master_num;
|
input [ADDR_BITS-1:0] addr;
|
input [ADDR_BITS-1:0] addr;
|
input [DATA_BITS-1:0] wdata;
|
input [DATA_BITS-1:0] wdata;
|
begin
|
begin
|
check_master_num("write_single", master_num);
|
check_master_num("write_single", master_num);
|
case (master_num)
|
case (master_num)
|
IX : PREFIX_singleIX.write_single(addr, wdata);
|
IDX : PREFIX_singleIDX.write_single(addr, wdata);
|
endcase
|
endcase
|
end
|
end
|
endtask
|
endtask
|
|
|
task read_single;
|
task read_single;
|
| Line 237... |
Line 252... |
input [ADDR_BITS-1:0] addr;
|
input [ADDR_BITS-1:0] addr;
|
output [DATA_BITS-1:0] rdata;
|
output [DATA_BITS-1:0] rdata;
|
begin
|
begin
|
check_master_num("read_single", master_num);
|
check_master_num("read_single", master_num);
|
case (master_num)
|
case (master_num)
|
IX : PREFIX_singleIX.read_single(addr, rdata);
|
IDX : PREFIX_singleIDX.read_single(addr, rdata);
|
endcase
|
endcase
|
end
|
end
|
endtask
|
endtask
|
|
|
task check_single;
|
task check_single;
|
| Line 249... |
Line 264... |
input [ADDR_BITS-1:0] addr;
|
input [ADDR_BITS-1:0] addr;
|
input [DATA_BITS-1:0] expected;
|
input [DATA_BITS-1:0] expected;
|
begin
|
begin
|
check_master_num("check_single", master_num);
|
check_master_num("check_single", master_num);
|
case (master_num)
|
case (master_num)
|
IX : PREFIX_singleIX.check_single(addr, expected);
|
IDX : PREFIX_singleIDX.check_single(addr, expected);
|
endcase
|
endcase
|
end
|
end
|
endtask
|
endtask
|
|
|
task write_and_check_single;
|
task write_and_check_single;
|
| Line 261... |
Line 276... |
input [ADDR_BITS-1:0] addr;
|
input [ADDR_BITS-1:0] addr;
|
input [DATA_BITS-1:0] data;
|
input [DATA_BITS-1:0] data;
|
begin
|
begin
|
check_master_num("write_and_check_single", master_num);
|
check_master_num("write_and_check_single", master_num);
|
case (master_num)
|
case (master_num)
|
IX : PREFIX_singleIX.write_and_check_single(addr, data);
|
IDX : PREFIX_singleIDX.write_and_check_single(addr, data);
|
endcase
|
endcase
|
end
|
end
|
endtask
|
endtask
|
|
|
task insert_wr_cmd;
|
task insert_wr_cmd;
|
| Line 274... |
Line 289... |
input [LEN_BITS-1:0] len;
|
input [LEN_BITS-1:0] len;
|
input [SIZE_BITS-1:0] size;
|
input [SIZE_BITS-1:0] size;
|
begin
|
begin
|
check_master_num("insert_wr_cmd", master_num);
|
check_master_num("insert_wr_cmd", master_num);
|
case (master_num)
|
case (master_num)
|
IX : PREFIX_singleIX.insert_wr_cmd(addr, len, size);
|
IDX : PREFIX_singleIDX.insert_wr_cmd(addr, len, size);
|
endcase
|
endcase
|
end
|
end
|
endtask
|
endtask
|
|
|
task insert_rd_cmd;
|
task insert_rd_cmd;
|
| Line 287... |
Line 302... |
input [LEN_BITS-1:0] len;
|
input [LEN_BITS-1:0] len;
|
input [SIZE_BITS-1:0] size;
|
input [SIZE_BITS-1:0] size;
|
begin
|
begin
|
check_master_num("insert_rd_cmd", master_num);
|
check_master_num("insert_rd_cmd", master_num);
|
case (master_num)
|
case (master_num)
|
IX : PREFIX_singleIX.insert_rd_cmd(addr, len, size);
|
IDX : PREFIX_singleIDX.insert_rd_cmd(addr, len, size);
|
endcase
|
endcase
|
end
|
end
|
endtask
|
endtask
|
|
|
task insert_wr_data;
|
task insert_wr_data;
|
input [31:0] master_num;
|
input [31:0] master_num;
|
input [DATA_BITS-1:0] wdata;
|
input [DATA_BITS-1:0] wdata;
|
begin
|
begin
|
check_master_num("insert_wr_data", master_num);
|
check_master_num("insert_wr_data", master_num);
|
case (master_num)
|
case (master_num)
|
IX : PREFIX_singleIX.insert_wr_data(wdata);
|
IDX : PREFIX_singleIDX.insert_wr_data(wdata);
|
endcase
|
endcase
|
end
|
end
|
endtask
|
endtask
|
|
|
task insert_wr_incr_data;
|
task insert_wr_incr_data;
|
| Line 311... |
Line 326... |
input [LEN_BITS-1:0] len;
|
input [LEN_BITS-1:0] len;
|
input [SIZE_BITS-1:0] size;
|
input [SIZE_BITS-1:0] size;
|
begin
|
begin
|
check_master_num("insert_wr_incr_data", master_num);
|
check_master_num("insert_wr_incr_data", master_num);
|
case (master_num)
|
case (master_num)
|
IX : PREFIX_singleIX.insert_wr_incr_data(addr, len, size);
|
IDX : PREFIX_singleIDX.insert_wr_incr_data(addr, len, size);
|
endcase
|
endcase
|
end
|
end
|
endtask
|
endtask
|
|
|
task insert_rand_chk;
|
task insert_rand_chk;
|
input [31:0] master_num;
|
input [31:0] master_num;
|
input [31:0] burst_num;
|
input [31:0] burst_num;
|
begin
|
begin
|
check_master_num("insert_rand_chk", master_num);
|
check_master_num("insert_rand_chk", master_num);
|
case (master_num)
|
case (master_num)
|
IX : PREFIX_singleIX.insert_rand_chk(burst_num);
|
IDX : PREFIX_singleIDX.insert_rand_chk(burst_num);
|
endcase
|
endcase
|
end
|
end
|
endtask
|
endtask
|
|
|
|
task insert_rand;
|
|
input [31:0] burst_num;
|
|
|
|
reg [31:0] burst_numIDX;
|
|
integer remain;
|
|
begin
|
|
remain = burst_num;
|
|
LOOP IDX ID_NUM
|
|
if (remain > 0)
|
|
begin
|
|
burst_numIDX = rand(1, remain);
|
|
remain = remain - burst_numIDX;
|
|
insert_rand_chk(IDX, burst_numIDX);
|
|
end
|
|
ENDLOOP IDX
|
|
end
|
|
endtask
|
|
|
|
|
endmodule
|
endmodule
|
|
|
|
|
