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Subversion Repositories apb_mstr

[/] [apb_mstr/] [trunk/] [src/] [base/] [axi_master_single.v] - Diff between revs 4 and 8

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Rev 4 Rev 8
Line 49... Line 49... 
                                       (MAX_CMDS <= 128) ? 7 :
 
                                       (MAX_CMDS <= 128) ? 7 :
 
                                       (MAX_CMDS <= 256) ? 8 :
 
                                       (MAX_CMDS <= 256) ? 8 :
 
                                       (MAX_CMDS <= 512) ? 9 : 0; //0 is ilegal
 
                                       (MAX_CMDS <= 512) ? 9 : 0; //0 is ilegal
 
 
 
 
 
 
 
 
 
 
 
 
 
   input                               clk;
 
   input                               clk;
 
   input                               reset;
 
   input                               reset;
 
 
 
 
 
   port                                GROUP_STUB_AXI;
 
   port                                GROUP_STUB_AXI;
 
 
 
 
Line 73... Line 72... 
 
 
 
 
   reg                                 enable = 0;
 
   reg                                 enable = 0;
 
   reg                                 rd_enable = 0;
 
   reg                                 rd_enable = 0;
 
   reg                                 wr_enable = 0;
 
   reg                                 wr_enable = 0;
 
   reg                                 wait_for_write = 0;
 
   reg                                 wait_for_write = 0;
 
 
 
   reg                                 err_on_wr_resp = 1;
 
 
 
   reg                                 err_on_rd_resp = 1;
 
 
 
 
 
   reg                                 scrbrd_enable = 0;
 
   reg                                 scrbrd_enable = 0;
 
   reg [LEN_BITS-1:0]                   wvalid_cnt;
 
   reg [LEN_BITS-1:0]                   wvalid_cnt;
 
 
 
 
 
   reg                                 rd_cmd_push = 0;
 
   reg                                 rd_cmd_push = 0;
Line 247... Line 248... 
   assign         ARCACHE = 4'd0; //not supported
 
   assign         ARCACHE = 4'd0; //not supported
 
   assign         ARPROT  = 4'd0; //not supported
 
   assign         ARPROT  = 4'd0; //not supported
 
   assign         ARLOCK  = 2'd0; //not supported
 
   assign         ARLOCK  = 2'd0; //not supported
 
 
 
 
 
   assign         rd_fifo_data_in = RDATA;
 
   assign         rd_fifo_data_in = RDATA;
 
   assign         rd_fifo_resp_in = BRESP;
 
   assign         rd_fifo_resp_in = RRESP;
 
 
 
 
 
   assign         wr_data_bytes = 1'b1 << wr_data_size;
 
   assign         wr_data_bytes = 1'b1 << wr_data_size;
 
 
 
 
 
   assign         wr_data_strb =
 
   assign         wr_data_strb =
 
                  wr_data_size == 'd0 ? 1'b1       :
 
                  wr_data_size == 'd0 ? 1'b1       :
Line 323... Line 324... 
         rd_resp_addr_in = addr;
 
         rd_resp_addr_in = addr;
 
         rd_resp_size_in = size;
 
         rd_resp_size_in = size;
 
 
 
 
 
         if (rd_cmd_full) enable = 1; //start stub not started yet
 
         if (rd_cmd_full) enable = 1; //start stub not started yet
 
 
 
 
 
         wait ((!rd_cmd_full) & (!rd_resp_full));
 
         #FFD; wait ((!rd_cmd_full) & (!rd_resp_full));
 
         @(negedge clk); #FFD;
 
         @(negedge clk); #FFD;
 
         rd_cmd_push  = 1;
 
         rd_cmd_push  = 1;
 
         rd_resp_push = 1;
 
         rd_resp_push = 1;
 
         @(posedge clk); #FFD;
 
         @(posedge clk); #FFD;
 
         rd_cmd_push  = 0;
 
         rd_cmd_push  = 0;
Line 348... Line 349... 
         wr_data_len_in  = len;
 
         wr_data_len_in  = len;
 
         wr_data_size_in = size;
 
         wr_data_size_in = size;
 
 
 
 
 
         if (wr_cmd_full) enable = 1; //start stub not started yet
 
         if (wr_cmd_full) enable = 1; //start stub not started yet
 
 
 
 
 
         wait ((!wr_cmd_full) & (!wr_data_full));
 
         #FFD; wait ((!wr_cmd_full) & (!wr_data_full));
 
         @(negedge clk); #FFD;
 
         @(negedge clk); #FFD;
 
         wr_cmd_push  = 1;
 
         wr_cmd_push  = 1;
 
         wr_data_push = 1;
 
         wr_data_push = 1;
 
         @(posedge clk); #FFD;
 
         @(posedge clk); #FFD;
 
         wr_cmd_push  = 0;
 
         wr_cmd_push  = 0;
Line 364... Line 365... 
      input [DATA_BITS-1:0]  wdata;
 
      input [DATA_BITS-1:0]  wdata;
 
 
 
 
 
      begin
 
      begin
 
         wr_fifo_data_in  = wdata;
 
         wr_fifo_data_in  = wdata;
 
 
 
 
 
         wait (!wr_fifo_full);
 
         #FFD; wait (!wr_fifo_full);
 
         @(negedge clk); #FFD;
 
         @(negedge clk); #FFD;
 
         wr_fifo_push = 1;
 
         wr_fifo_push = 1;
 
         @(posedge clk); #FFD;
 
         @(posedge clk); #FFD;
 
         wr_fifo_push = 0;
 
         wr_fifo_push = 0;
 
      end
 
      end
Line 411... Line 412... 
         scrbrd_enable = 1;
 
         scrbrd_enable = 1;
 
         scrbrd_addr_in  = addr;
 
         scrbrd_addr_in  = addr;
 
         scrbrd_data_in  = data;
 
         scrbrd_data_in  = data;
 
         scrbrd_mask_in  = mask;
 
         scrbrd_mask_in  = mask;
 
 
 
 
 
         wait (!scrbrd_full);
 
         #FFD; wait (!scrbrd_full);
 
         @(negedge clk); #FFD;
 
         @(negedge clk); #FFD;
 
         scrbrd_push = 1;
 
         scrbrd_push = 1;
 
         @(posedge clk); #FFD;
 
         @(posedge clk); #FFD;
 
         scrbrd_push = 0;
 
         scrbrd_push = 0;
 
      end
 
      end
Line 480... Line 481... 
      reg [ADDR_BITS-1:0]  addr;
 
      reg [ADDR_BITS-1:0]  addr;
 
      reg [LEN_BITS-1:0]   len;
 
      reg [LEN_BITS-1:0]   len;
 
      reg [SIZE_BITS-1:0]  size;
 
      reg [SIZE_BITS-1:0]  size;
 
 
 
 
 
      begin
 
      begin
 
 
 
         if (DATA_BITS==32) size_max = 2'b10;
 
         len   = rand(len_min, len_max);
 
         len   = rand(len_min, len_max);
 
         size  = rand(size_min, size_max);
 
         size  = rand(size_min, size_max);
 
         addr  = rand_align(addr_min, addr_max, 1 << size);
 
         addr  = rand_align(addr_min, addr_max, 1 << size);
 
 
 
 
 
 
 
         if (ahb_bursts)
 
 
 
           begin
 
 
 
              len   =
 
 
 
                      len[3] ? 15 :
 
 
 
                      len[2] ? 7 :
 
 
 
                      len[1] ? 3 : 0;
 
 
 
              if (len > 0)
 
 
 
                size = (DATA_BITS == 64) ? 2'b11 : 2'b10; //AHB bursts always full data
 
 
 
 
 
 
 
              addr = align(addr, EXPR(DATA_BITS/8)*(len+1)); //address aligned to burst size
 
 
 
           end
 
         insert_wr_rd_scrbrd(addr, len, size);
 
         insert_wr_rd_scrbrd(addr, len, size);
 
      end
 
      end
 
   endtask
 
   endtask
 
 
 
 
 
   task insert_rand_chk;
 
   task insert_rand_chk;
Line 526... Line 540... 
      output [1:0] resp;
 
      output [1:0] resp;
 
 
 
 
 
      reg [DATA_BITS-1:0] rdata;
 
      reg [DATA_BITS-1:0] rdata;
 
      reg [1:0] resp;
 
      reg [1:0] resp;
 
      begin
 
      begin
 
         wait (!rd_fifo_empty);
 
         #FFD; wait (!rd_fifo_empty);
 
         rdata = rd_fifo_data;
 
         rdata = rd_fifo_data;
 
         resp = rd_fifo_resp;
 
         resp = rd_fifo_resp;
 
         @(negedge clk); #FFD;
 
         @(negedge clk); #FFD;
 
         rd_fifo_pop = 1;
 
         rd_fifo_pop = 1;
 
         @(posedge clk); #FFD;
 
         @(posedge clk); #FFD;
 
         rd_fifo_pop = 0;
 
         rd_fifo_pop = 0;
 
 
 
         if ((resp != 2'b00) && (err_on_rd_resp))
 
 
 
           $display("PREFIX_MASTER%0d: RRESP_ERROR: Received RRESP 2'b%0b.\tTime: %0d ns.", MASTER_NUM, resp, $time);
 
      end
 
      end
 
   endtask
 
   endtask
 
 
 
 
 
   task get_scrbrd;
 
   task get_scrbrd;
 
      output [ADDR_BITS-1:0] addr;
 
      output [ADDR_BITS-1:0] addr;
Line 545... Line 561... 
 
 
 
 
      reg [ADDR_BITS-1:0] addr;
 
      reg [ADDR_BITS-1:0] addr;
 
      reg [DATA_BITS-1:0] rdata;
 
      reg [DATA_BITS-1:0] rdata;
 
      reg [DATA_BITS-1:0] mask;
 
      reg [DATA_BITS-1:0] mask;
 
      begin
 
      begin
 
         wait (!scrbrd_empty);
 
         #FFD; wait (!scrbrd_empty);
 
         addr = scrbrd_addr;
 
         addr = scrbrd_addr;
 
         rdata = scrbrd_data;
 
         rdata = scrbrd_data;
 
         mask = scrbrd_mask;
 
         mask = scrbrd_mask;
 
         @(negedge clk); #FFD;
 
         @(negedge clk); #FFD;
 
         scrbrd_pop = 1;
 
         scrbrd_pop = 1;
Line 561... Line 577... 
   task get_wr_resp;
 
   task get_wr_resp;
 
      output [1:0] resp;
 
      output [1:0] resp;
 
 
 
 
 
      reg [1:0] resp;
 
      reg [1:0] resp;
 
      begin
 
      begin
 
         wait (!wr_resp_empty);
 
         #FFD; wait (!wr_resp_empty);
 
         resp = wr_resp_resp;
 
         resp = wr_resp_resp;
 
         @(negedge clk); #FFD;
 
         @(negedge clk); #FFD;
 
         wr_resp_pop = 1;
 
         wr_resp_pop = 1;
 
         @(posedge clk); #FFD;
 
         @(posedge clk); #FFD;
 
         wr_resp_pop = 0;
 
         wr_resp_pop = 0;
 
 
 
         if ((resp != 2'b00) && (err_on_wr_resp))
 
 
 
           $display("PREFIX_MASTER%0d: BRESP_ERROR: Received BRESP 2'b%0b.\tTime: %0d ns.", MASTER_NUM, resp, $time);
 
      end
 
      end
 
   endtask
 
   endtask
 
 
 
 
 
   task insert_rd_single;
 
   task insert_rd_single;
 
      input [ADDR_BITS-1:0]  addr;
 
      input [ADDR_BITS-1:0]  addr;
Line 623... Line 641... 
      reg [1:0] resp;
 
      reg [1:0] resp;
 
      reg [DATA_BITS-1:0] rdata;
 
      reg [DATA_BITS-1:0] rdata;
 
      begin
 
      begin
 
         read_single_ack(addr, rdata, resp);
 
         read_single_ack(addr, rdata, resp);
 
         if (rdata !== expected)
 
         if (rdata !== expected)
 
           $display("MASTER%0d: CHK_SINGLE_ERROR: Address: 0x%0h, Expected: 0x%0h, Received: 0x%0h.\tTime: %0d ns.", MASTER_NUM, addr, expected, rdata, $time);
 
           $display("PREFIX_MASTER%0d: CHK_SINGLE_ERROR: Address: 0x%0h, Expected: 0x%0h, Received: 0x%0h.\tTime: %0d ns.", MASTER_NUM, addr, expected, rdata, $time);
 
      end
 
      end
 
   endtask
 
   endtask
 
 
 
 
 
   task write_and_check_single;
 
   task write_and_check_single;
 
      input [ADDR_BITS-1:0]  addr;
 
      input [ADDR_BITS-1:0]  addr;
Line 663... Line 681... 
         get_rd_resp(rdata, resp);
 
         get_rd_resp(rdata, resp);
 
         expected_data = expected_data & mask; //TBD insert z as dontcare (for print)
 
         expected_data = expected_data & mask; //TBD insert z as dontcare (for print)
 
         rdata_masked = rdata & mask;
 
         rdata_masked = rdata & mask;
 
 
 
 
 
         if (expected_data !== rdata_masked)
 
         if (expected_data !== rdata_masked)
 
           $display("MASTER%0d: SCRBRD_ERROR: Address: 0x%0h, Expected: 0x%0h, Received: 0x%0h.\tTime: %0d ns.", MASTER_NUM, addr, expected_data, rdata, $time);
 
           $display("PREFIX_MASTER%0d: SCRBRD_ERROR: Address: 0x%0h, Expected: 0x%0h, Received: 0x%0h.\tTime: %0d ns.", MASTER_NUM, addr, expected_data, rdata, $time);
 
      end
 
      end
 
   endtask
 
   endtask
 
 
 
 
 
   always @(posedge scrbrd_enable)
 
   always @(posedge scrbrd_enable)
 
     begin
 
     begin

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