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[/] [apbi2c/] [trunk/] [rtl/] [module_i2c.v] - Diff between revs 11 and 18

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Rev 11	Rev 18
Line 203...	Line 203...

`case(state_tx)//STATE_TX IS MORE SECURE CHANGE ONLY IF YOU KNOW WHAT ARE YOU DOING`	`case(state_tx)//STATE_TX IS MORE SECURE CHANGE ONLY IF YOU KNOW WHAT ARE YOU DOING`
`TX_IDLE:`	`TX_IDLE:`
`begin`	`begin`
`//OBEYING SPEC`	`//OBEYING SPEC`
`if(DATA_CONFIG_REG[0] == 1'b0 && fifo_tx_f_full == 1'b0 && DATA_CONFIG_REG[1] == 1'b0)`	`if(DATA_CONFIG_REG[0] == 1'b0 && (fifo_tx_f_full == 1'b1 \|\| fifo_tx_f_empty == 1'b0) && DATA_CONFIG_REG[1] == 1'b0)`
`begin`	`begin`
`next_state_tx = TX_IDLE;`	`next_state_tx = TX_IDLE;`
`end`	`end`
`else if(DATA_CONFIG_REG[0] == 1'b1 && fifo_tx_f_full == 1'b1 && DATA_CONFIG_REG[1] == 1'b1)`	`else if(DATA_CONFIG_REG[0] == 1'b1 && (fifo_tx_f_full == 1'b1 \|\| fifo_tx_f_empty == 1'b0) && DATA_CONFIG_REG[1] == 1'b1)`
`begin`	`begin`
`next_state_tx = TX_IDLE;`	`next_state_tx = TX_IDLE;`
`end`	`end`
`else if(DATA_CONFIG_REG[0] == 1'b1 && fifo_tx_f_full == 1'b1 && DATA_CONFIG_REG[1] == 1'b0)`	`else if(DATA_CONFIG_REG[0] == 1'b1 && (fifo_tx_f_full == 1'b1 \|\| fifo_tx_f_empty == 1'b0) && DATA_CONFIG_REG[1] == 1'b0)`
`begin`	`begin`
`next_state_tx = TX_START;`	`next_state_tx = TX_START;`
`end`	`end`


Line 764...	Line 764...
`begin`	`begin`

`fifo_tx_rd_en <= 1'b0;`	`fifo_tx_rd_en <= 1'b0;`


`if(DATA_CONFIG_REG[0] == 1'b0 && fifo_tx_f_full == 1'b0 && DATA_CONFIG_REG[1] == 1'b0)`	`if(DATA_CONFIG_REG[0] == 1'b0 && (fifo_tx_f_full == 1'b1 \|\|fifo_tx_f_empty == 1'b0) && DATA_CONFIG_REG[1] == 1'b0)`
`begin`	`begin`
`count_send_data <= 12'd0;`	`count_send_data <= 12'd0;`
`SDA_OUT<= 1'b1;`	`SDA_OUT<= 1'b1;`
`BR_CLK_O <= 1'b1;`	`BR_CLK_O <= 1'b1;`
`end`	`end`
`else if(DATA_CONFIG_REG[0] == 1'b1 && fifo_tx_f_full == 1'b1 && DATA_CONFIG_REG[1] == 1'b0)`	`else if(DATA_CONFIG_REG[0] == 1'b1 && (fifo_tx_f_full == 1'b1 \|\|fifo_tx_f_empty == 1'b0) && DATA_CONFIG_REG[1] == 1'b0)`
`begin`	`begin`
`count_send_data <= count_send_data + 12'd1;`	`count_send_data <= count_send_data + 12'd1;`
`SDA_OUT<=1'b0;`	`SDA_OUT<=1'b0;`
`end`	`end`
`else if(DATA_CONFIG_REG[0] == 1'b1 && fifo_tx_f_full == 1'b1 && DATA_CONFIG_REG[1] == 1'b1)`	`else if(DATA_CONFIG_REG[0] == 1'b1 && (fifo_tx_f_full == 1'b1 \|\|fifo_tx_f_empty == 1'b0) && DATA_CONFIG_REG[1] == 1'b1)`
`begin`	`begin`
`count_send_data <= 12'd0;`	`count_send_data <= 12'd0;`
`SDA_OUT<= 1'b1;`	`SDA_OUT<= 1'b1;`
`BR_CLK_O <= 1'b1;`	`BR_CLK_O <= 1'b1;`
`end`	`end`
Line 1302...	Line 1302...
`end`	`end`
`end`	`end`
`else`	`else`
`begin`	`begin`
`count_send_data <= 12'd0;`	`count_send_data <= 12'd0;`
	`SDA_OUT<=1'b0;`
`end`	`end`

`end`	`end`
`TX_RESPONSE_ADRESS:`	`TX_RESPONSE_ADRESS:`
`begin`	`begin`
Line 1556...	Line 1557...

`end`	`end`
`else`	`else`
`begin`	`begin`
`count_send_data <= 12'd0;`	`count_send_data <= 12'd0;`
	`SDA_OUT<=1'b0;`
`end`	`end`

`end`	`end`
`TX_RESPONSE_DATA0_1:`	`TX_RESPONSE_DATA0_1:`
`begin`	`begin`
Line 1817...	Line 1819...

`end`	`end`
`else`	`else`
`begin`	`begin`
`count_send_data <= 12'd0;`	`count_send_data <= 12'd0;`
	`SDA_OUT<=1'b0;`
`end`	`end`

`end`	`end`
`TX_RESPONSE_DATA1_1:`	`TX_RESPONSE_DATA1_1:`
`begin`	`begin`
Line 2608...	Line 2611...
`count_receive_data <= 12'd0;`	`count_receive_data <= 12'd0;`
`end`	`end`
`end`	`end`
`RX_START:`	`RX_START:`
`begin`	`begin`
`if(SDA == 1'b0 && SCL == 1'b0)`	`if(SDA == 1'b0 && SCL == 1'b0 && count_receive_data < DATA_CONFIG_REG[13:2] )`
`begin`	`begin`
`count_receive_data <= count_receive_data +12'd1;`	`count_receive_data <= count_receive_data +12'd1;`
`end`	`end`
`else`	`else`
`begin`	`begin`

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[/] [apbi2c/] [trunk/] [rtl/] [module_i2c.v] - Diff between revs 11 and 18