| Line 128... |
Line 128... |
//RESPONSE USED TO HOLD SIGNAL TO ACK OR NACK
|
//RESPONSE USED TO HOLD SIGNAL TO ACK OR NACK
|
reg RESPONSE;
|
reg RESPONSE;
|
|
|
// TX PARAMETERS USED TO STATE MACHINE
|
// TX PARAMETERS USED TO STATE MACHINE
|
|
|
localparam [5:0] TX_IDLE = 6'd0, //IDLE
|
localparam [5:0] RX_TX_IDLE = 6'd0, //IDLE
|
|
|
TX_START = 6'd1,//START BIT
|
RX_TX_START = 6'd1,//START BIT
|
|
|
TX_CONTROLIN_1 = 6'd2, //START BYTE
|
RX_TX_CONTROLIN_1 = 6'd2, //START BYTE
|
TX_CONTROLIN_2 = 6'd3,
|
RX_TX_CONTROLIN_2 = 6'd3,
|
TX_CONTROLIN_3 = 6'd4,
|
RX_TX_CONTROLIN_3 = 6'd4,
|
TX_CONTROLIN_4 = 6'd5,
|
RX_TX_CONTROLIN_4 = 6'd5,
|
TX_CONTROLIN_5 = 6'd6,
|
RX_TX_CONTROLIN_5 = 6'd6,
|
TX_CONTROLIN_6 = 6'd7,
|
RX_TX_CONTROLIN_6 = 6'd7,
|
TX_CONTROLIN_7 = 6'd8,
|
RX_TX_CONTROLIN_7 = 6'd8,
|
TX_CONTROLIN_8 = 6'd9, //END FIRST BYTE
|
RX_TX_CONTROLIN_8 = 6'd9, //END FIRST BYTE
|
|
|
TX_RESPONSE_CIN =6'd10, //RESPONSE
|
RX_TX_RESPONSE_CIN =6'd10, //RESPONSE
|
|
|
TX_ADRESS_1 = 6'd11,//START BYTE
|
RX_TX_ADRESS_1 = 6'd11,//START BYTE
|
TX_ADRESS_2 = 6'd12,
|
RX_TX_ADRESS_2 = 6'd12,
|
TX_ADRESS_3 = 6'd13,
|
RX_TX_ADRESS_3 = 6'd13,
|
TX_ADRESS_4 = 6'd14,
|
RX_TX_ADRESS_4 = 6'd14,
|
TX_ADRESS_5 = 6'd15,
|
RX_TX_ADRESS_5 = 6'd15,
|
TX_ADRESS_6 = 6'd16,
|
RX_TX_ADRESS_6 = 6'd16,
|
TX_ADRESS_7 = 6'd17,
|
RX_TX_ADRESS_7 = 6'd17,
|
TX_ADRESS_8 = 6'd18,//END FIRST BYTE
|
RX_TX_ADRESS_8 = 6'd18,//END FIRST BYTE
|
|
|
TX_RESPONSE_ADRESS =6'd19, //RESPONSE
|
RX_TX_RESPONSE_ADRESS =6'd19, //RESPONSE
|
|
|
TX_DATA0_1 = 6'd20,//START BYTE
|
RX_TX_DATA0_1 = 6'd20,//START BYTE
|
TX_DATA0_2 = 6'd21,
|
RX_TX_DATA0_2 = 6'd21,
|
TX_DATA0_3 = 6'd22,
|
RX_TX_DATA0_3 = 6'd22,
|
TX_DATA0_4 = 6'd23,
|
RX_TX_DATA0_4 = 6'd23,
|
TX_DATA0_5 = 6'd24,
|
RX_TX_DATA0_5 = 6'd24,
|
TX_DATA0_6 = 6'd25,
|
RX_TX_DATA0_6 = 6'd25,
|
TX_DATA0_7 = 6'd26,
|
RX_TX_DATA0_7 = 6'd26,
|
TX_DATA0_8 = 6'd27,//END FIRST BYTE
|
RX_TX_DATA0_8 = 6'd27,//END FIRST BYTE
|
|
|
TX_RESPONSE_DATA0_1 = 6'd28, //RESPONSE
|
RX_TX_RESPONSE_DATA0_1 = 6'd28, //RESPONSE
|
|
|
TX_DATA1_1 = 6'd29,//START BYTE
|
RX_TX_DATA1_1 = 6'd29,//START BYTE
|
TX_DATA1_2 = 6'd30,
|
RX_TX_DATA1_2 = 6'd30,
|
TX_DATA1_3 = 6'd31,
|
RX_TX_DATA1_3 = 6'd31,
|
TX_DATA1_4 = 6'd32,
|
RX_TX_DATA1_4 = 6'd32,
|
TX_DATA1_5 = 6'd33,
|
RX_TX_DATA1_5 = 6'd33,
|
TX_DATA1_6 = 6'd34,
|
RX_TX_DATA1_6 = 6'd34,
|
TX_DATA1_7 = 6'd35,
|
RX_TX_DATA1_7 = 6'd35,
|
TX_DATA1_8 = 6'd36,//END FIRST BYTE
|
RX_TX_DATA1_8 = 6'd36,//END FIRST BYTE
|
|
|
TX_RESPONSE_DATA1_1 = 6'd37,//RESPONSE
|
RX_TX_RESPONSE_DATA1_1 = 6'd37,//RESPONSE
|
|
|
TX_DELAY_BYTES = 6'd38,//USED ONLY IN ACK TO DELAY BETWEEN
|
RX_TX_DELAY_BYTES = 6'd38,//USED ONLY IN ACK TO DELAY BETWEEN
|
TX_NACK = 6'd39,//USED ONLY IN ACK TO DELAY BETWEEN BYTES
|
RX_TX_NACK = 6'd39,//USED ONLY IN ACK TO DELAY BETWEEN BYTES
|
TX_STOP = 6'd40;//USED TO SEND STOP BIT
|
RX_TX_STOP = 6'd40;//USED TO SEND STOP BIT
|
|
|
//STATE CONTROL
|
//STATE CONTROL
|
reg [5:0] state_tx;
|
reg [5:0] state_tx_rx;
|
reg [5:0] next_state_tx;
|
reg [5:0] next_state_tx_rx;
|
|
|
//ASSIGN REGISTERS TO BIDIRETIONAL PORTS
|
//ASSIGN REGISTERS TO BIDIRETIONAL PORTS
|
assign SDA = (DATA_CONFIG_REG[0] == 1'b1 & DATA_CONFIG_REG[1] == 1'b0)?SDA_OUT:1'b0;
|
assign SDA = (DATA_CONFIG_REG[0] == 1'b1 & DATA_CONFIG_REG[1] == 1'b0)?SDA_OUT:1'b0;
|
assign SCL = (DATA_CONFIG_REG[0] == 1'b1 & DATA_CONFIG_REG[1] == 1'b0)?BR_CLK_O:1'b0;
|
assign SCL = (DATA_CONFIG_REG[0] == 1'b1 & DATA_CONFIG_REG[1] == 1'b0)?BR_CLK_O:1'b0;
|
|
|
| Line 197... |
Line 197... |
always@(*)
|
always@(*)
|
begin
|
begin
|
|
|
//THE FUN START HERE :-)
|
//THE FUN START HERE :-)
|
//COMBINATIONAL UPDATE STATE BE CAREFUL WITH WHAT YOU MAKE HERE
|
//COMBINATIONAL UPDATE STATE BE CAREFUL WITH WHAT YOU MAKE HERE
|
next_state_tx = state_tx;
|
next_state_tx_rx = state_tx_rx;
|
|
|
case(state_tx)//STATE_TX IS MORE SECURE CHANGE ONLY IF YOU KNOW WHAT ARE YOU DOING
|
case(state_tx_rx)//state_tx_rx IS MORE SECURE CHANGE ONLY IF YOU KNOW WHAT ARE YOU DOING
|
TX_IDLE:
|
RX_TX_IDLE:
|
begin
|
begin
|
//OBEYING SPEC
|
//OBEYING SPEC
|
if(DATA_CONFIG_REG[0] == 1'b0 && (fifo_tx_f_full == 1'b1 || fifo_tx_f_empty == 1'b0) && DATA_CONFIG_REG[1] == 1'b0)
|
if(DATA_CONFIG_REG[0] == 1'b0 && (fifo_tx_f_full == 1'b1 || fifo_tx_f_empty == 1'b0) && DATA_CONFIG_REG[1] == 1'b0)
|
begin
|
begin
|
next_state_tx = TX_IDLE;
|
next_state_tx_rx = RX_TX_IDLE;
|
end
|
end
|
else if(DATA_CONFIG_REG[0] == 1'b1 && (fifo_tx_f_full == 1'b1 || fifo_tx_f_empty == 1'b0) && DATA_CONFIG_REG[1] == 1'b1)
|
else if(DATA_CONFIG_REG[0] == 1'b1 && (fifo_tx_f_full == 1'b1 || fifo_tx_f_empty == 1'b0) && DATA_CONFIG_REG[1] == 1'b1)
|
begin
|
begin
|
next_state_tx = TX_IDLE;
|
next_state_tx_rx = RX_TX_IDLE;
|
end
|
end
|
else if(DATA_CONFIG_REG[0] == 1'b1 && (fifo_tx_f_full == 1'b1 || fifo_tx_f_empty == 1'b0) && DATA_CONFIG_REG[1] == 1'b0)
|
else if(DATA_CONFIG_REG[0] == 1'b1 && (fifo_tx_f_full == 1'b1 || fifo_tx_f_empty == 1'b0) && DATA_CONFIG_REG[1] == 1'b0)
|
begin
|
begin
|
next_state_tx = TX_START;
|
next_state_tx_rx = RX_TX_START;
|
end
|
end
|
|
|
|
|
end
|
end
|
TX_START://THIS IS USED TOO ALL STATE MACHINES THE COUNTER_SEND_DATA
|
RX_TX_START://THIS IS USED TOO ALL STATE MACHINES THE COUNTER_SEND_DATA
|
begin
|
begin
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
next_state_tx = TX_START;
|
next_state_tx_rx = RX_TX_START;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
next_state_tx = TX_CONTROLIN_1;
|
next_state_tx_rx = RX_TX_CONTROLIN_1;
|
end
|
end
|
|
|
end
|
end
|
TX_CONTROLIN_1:
|
RX_TX_CONTROLIN_1:
|
begin
|
begin
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
next_state_tx = TX_CONTROLIN_1;
|
next_state_tx_rx = RX_TX_CONTROLIN_1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
next_state_tx = TX_CONTROLIN_2;
|
next_state_tx_rx = RX_TX_CONTROLIN_2;
|
end
|
end
|
|
|
end
|
end
|
TX_CONTROLIN_2:
|
RX_TX_CONTROLIN_2:
|
begin
|
begin
|
|
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
next_state_tx =TX_CONTROLIN_2;
|
next_state_tx_rx = RX_TX_CONTROLIN_2;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
next_state_tx = TX_CONTROLIN_3;
|
next_state_tx_rx = RX_TX_CONTROLIN_3;
|
end
|
end
|
|
|
end
|
end
|
TX_CONTROLIN_3:
|
RX_TX_CONTROLIN_3:
|
begin
|
begin
|
|
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
next_state_tx = TX_CONTROLIN_3;
|
next_state_tx_rx = RX_TX_CONTROLIN_3;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
next_state_tx = TX_CONTROLIN_4;
|
next_state_tx_rx = RX_TX_CONTROLIN_4;
|
end
|
end
|
end
|
end
|
TX_CONTROLIN_4:
|
RX_TX_CONTROLIN_4:
|
begin
|
begin
|
|
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
next_state_tx = TX_CONTROLIN_4;
|
next_state_tx_rx = RX_TX_CONTROLIN_4;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
next_state_tx = TX_CONTROLIN_5;
|
next_state_tx_rx = RX_TX_CONTROLIN_5;
|
end
|
end
|
end
|
end
|
TX_CONTROLIN_5:
|
RX_TX_CONTROLIN_5:
|
begin
|
begin
|
|
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
next_state_tx = TX_CONTROLIN_5;
|
next_state_tx_rx = RX_TX_CONTROLIN_5;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
next_state_tx = TX_CONTROLIN_6;
|
next_state_tx_rx = RX_TX_CONTROLIN_6;
|
end
|
end
|
end
|
end
|
TX_CONTROLIN_6:
|
RX_TX_CONTROLIN_6:
|
begin
|
begin
|
|
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
next_state_tx = TX_CONTROLIN_6;
|
next_state_tx_rx = RX_TX_CONTROLIN_6;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
next_state_tx = TX_CONTROLIN_7;
|
next_state_tx_rx = RX_TX_CONTROLIN_7;
|
end
|
end
|
end
|
end
|
TX_CONTROLIN_7:
|
RX_TX_CONTROLIN_7:
|
begin
|
begin
|
|
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
next_state_tx = TX_CONTROLIN_7;
|
next_state_tx_rx = RX_TX_CONTROLIN_7;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
next_state_tx = TX_CONTROLIN_8;
|
next_state_tx_rx = RX_TX_CONTROLIN_8;
|
end
|
end
|
end
|
end
|
TX_CONTROLIN_8:
|
RX_TX_CONTROLIN_8:
|
begin
|
begin
|
|
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
next_state_tx = TX_CONTROLIN_8;
|
next_state_tx_rx = RX_TX_CONTROLIN_8;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
next_state_tx = TX_RESPONSE_CIN;
|
next_state_tx_rx = RX_TX_RESPONSE_CIN;
|
end
|
end
|
end
|
end
|
TX_RESPONSE_CIN:
|
RX_TX_RESPONSE_CIN:
|
begin
|
begin
|
|
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
next_state_tx = TX_RESPONSE_CIN;
|
next_state_tx_rx = RX_TX_RESPONSE_CIN;
|
end
|
end
|
else if(RESPONSE == 1'b0)//ACK
|
else if(RESPONSE == 1'b0)//ACK
|
begin
|
begin
|
next_state_tx = TX_DELAY_BYTES;
|
next_state_tx_rx = RX_TX_DELAY_BYTES;
|
end
|
end
|
else if(RESPONSE == 1'b1)//NACK
|
else if(RESPONSE == 1'b1)//NACK
|
begin
|
begin
|
next_state_tx = TX_NACK;
|
next_state_tx_rx = RX_TX_NACK;
|
end
|
end
|
|
|
end
|
end
|
|
|
//NOW SENDING ADDRESS
|
//NOW SENDING ADDRESS
|
TX_ADRESS_1:
|
RX_TX_ADRESS_1:
|
begin
|
begin
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
next_state_tx = TX_ADRESS_1;
|
next_state_tx_rx = RX_TX_ADRESS_1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
next_state_tx = TX_ADRESS_2;
|
next_state_tx_rx = RX_TX_ADRESS_2;
|
end
|
end
|
end
|
end
|
TX_ADRESS_2:
|
RX_TX_ADRESS_2:
|
begin
|
begin
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
next_state_tx = TX_ADRESS_2;
|
next_state_tx_rx = RX_TX_ADRESS_2;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
next_state_tx = TX_ADRESS_3;
|
next_state_tx_rx = RX_TX_ADRESS_3;
|
end
|
end
|
end
|
end
|
TX_ADRESS_3:
|
RX_TX_ADRESS_3:
|
begin
|
begin
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
next_state_tx = TX_ADRESS_3;
|
next_state_tx_rx = RX_TX_ADRESS_3;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
next_state_tx = TX_ADRESS_4;
|
next_state_tx_rx = RX_TX_ADRESS_4;
|
end
|
end
|
end
|
end
|
TX_ADRESS_4:
|
RX_TX_ADRESS_4:
|
begin
|
begin
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
next_state_tx = TX_ADRESS_4;
|
next_state_tx_rx = RX_TX_ADRESS_4;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
next_state_tx = TX_ADRESS_5;
|
next_state_tx_rx = RX_TX_ADRESS_5;
|
end
|
end
|
end
|
end
|
TX_ADRESS_5:
|
RX_TX_ADRESS_5:
|
begin
|
begin
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
next_state_tx = TX_ADRESS_5;
|
next_state_tx_rx = RX_TX_ADRESS_5;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
next_state_tx = TX_ADRESS_6;
|
next_state_tx_rx = RX_TX_ADRESS_6;
|
end
|
end
|
end
|
end
|
TX_ADRESS_6:
|
RX_TX_ADRESS_6:
|
begin
|
begin
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
next_state_tx = TX_ADRESS_6;
|
next_state_tx_rx = RX_TX_ADRESS_6;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
next_state_tx = TX_ADRESS_7;
|
next_state_tx_rx = RX_TX_ADRESS_7;
|
end
|
end
|
end
|
end
|
TX_ADRESS_7:
|
RX_TX_ADRESS_7:
|
begin
|
begin
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
next_state_tx = TX_ADRESS_7;
|
next_state_tx_rx = RX_TX_ADRESS_7;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
next_state_tx = TX_ADRESS_8;
|
next_state_tx_rx = RX_TX_ADRESS_8;
|
end
|
end
|
end
|
end
|
TX_ADRESS_8:
|
RX_TX_ADRESS_8:
|
begin
|
begin
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
next_state_tx = TX_ADRESS_8;
|
next_state_tx_rx = RX_TX_ADRESS_8;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
next_state_tx = TX_RESPONSE_ADRESS;
|
next_state_tx_rx = RX_TX_RESPONSE_ADRESS;
|
end
|
end
|
end
|
end
|
TX_RESPONSE_ADRESS:
|
RX_TX_RESPONSE_ADRESS:
|
begin
|
begin
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
next_state_tx = TX_RESPONSE_ADRESS;
|
next_state_tx_rx = RX_TX_RESPONSE_ADRESS;
|
end
|
end
|
else if(RESPONSE == 1'b0)//ACK
|
else if(RESPONSE == 1'b0)//ACK
|
begin
|
begin
|
next_state_tx = TX_DELAY_BYTES;
|
next_state_tx_rx = RX_TX_DELAY_BYTES;
|
end
|
end
|
else if(RESPONSE == 1'b1)//NACK --> RESTART CONDITION AND BACK TO START BYTE AGAIN
|
else if(RESPONSE == 1'b1)//NACK --> RESTART CONDITION AND BACK TO START BYTE AGAIN
|
begin
|
begin
|
next_state_tx = TX_NACK;
|
next_state_tx_rx = RX_TX_NACK;
|
end
|
end
|
end
|
end
|
|
|
//data in
|
//data in
|
TX_DATA0_1:
|
RX_TX_DATA0_1:
|
begin
|
begin
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
next_state_tx = TX_DATA0_1;
|
next_state_tx_rx = RX_TX_DATA0_1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
next_state_tx = TX_DATA0_2;
|
next_state_tx_rx = RX_TX_DATA0_2;
|
end
|
end
|
end
|
end
|
TX_DATA0_2:
|
RX_TX_DATA0_2:
|
begin
|
begin
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
next_state_tx = TX_DATA0_2;
|
next_state_tx_rx = RX_TX_DATA0_2;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
next_state_tx = TX_DATA0_3;
|
next_state_tx_rx = RX_TX_DATA0_3;
|
end
|
end
|
end
|
end
|
TX_DATA0_3:
|
RX_TX_DATA0_3:
|
begin
|
begin
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
next_state_tx = TX_DATA0_3;
|
next_state_tx_rx = RX_TX_DATA0_3;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
next_state_tx = TX_DATA0_4;
|
next_state_tx_rx = RX_TX_DATA0_4;
|
end
|
end
|
end
|
end
|
TX_DATA0_4:
|
RX_TX_DATA0_4:
|
begin
|
begin
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
next_state_tx = TX_DATA0_4;
|
next_state_tx_rx = RX_TX_DATA0_4;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
next_state_tx = TX_DATA0_5;
|
next_state_tx_rx = RX_TX_DATA0_5;
|
end
|
end
|
end
|
end
|
TX_DATA0_5:
|
RX_TX_DATA0_5:
|
begin
|
begin
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
next_state_tx = TX_DATA0_5;
|
next_state_tx_rx = RX_TX_DATA0_5;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
next_state_tx = TX_DATA0_6;
|
next_state_tx_rx = RX_TX_DATA0_6;
|
end
|
end
|
end
|
end
|
TX_DATA0_6:
|
RX_TX_DATA0_6:
|
begin
|
begin
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
next_state_tx = TX_DATA0_6;
|
next_state_tx_rx = RX_TX_DATA0_6;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
next_state_tx = TX_DATA0_7;
|
next_state_tx_rx = RX_TX_DATA0_7;
|
end
|
end
|
end
|
end
|
TX_DATA0_7:
|
RX_TX_DATA0_7:
|
begin
|
begin
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
next_state_tx = TX_DATA0_7;
|
next_state_tx_rx = RX_TX_DATA0_7;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
next_state_tx = TX_DATA0_8;
|
next_state_tx_rx = RX_TX_DATA0_8;
|
end
|
end
|
end
|
end
|
TX_DATA0_8:
|
RX_TX_DATA0_8:
|
begin
|
begin
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
next_state_tx = TX_DATA0_8;
|
next_state_tx_rx = RX_TX_DATA0_8;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
next_state_tx = TX_RESPONSE_DATA0_1;
|
next_state_tx_rx = RX_TX_RESPONSE_DATA0_1;
|
end
|
end
|
end
|
end
|
TX_RESPONSE_DATA0_1:
|
RX_TX_RESPONSE_DATA0_1:
|
begin
|
begin
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
next_state_tx = TX_RESPONSE_DATA0_1;
|
next_state_tx_rx = RX_TX_RESPONSE_DATA0_1;
|
end
|
end
|
else if(RESPONSE == 1'b0)//ACK
|
else if(RESPONSE == 1'b0)//ACK
|
begin
|
begin
|
next_state_tx = TX_DELAY_BYTES;
|
next_state_tx_rx = RX_TX_DELAY_BYTES;
|
end
|
end
|
else if(RESPONSE == 1'b1)//NACK
|
else if(RESPONSE == 1'b1)//NACK
|
begin
|
begin
|
next_state_tx = TX_NACK;
|
next_state_tx_rx = RX_TX_NACK;
|
end
|
end
|
end
|
end
|
|
|
//second byte
|
//second byte
|
TX_DATA1_1:
|
RX_TX_DATA1_1:
|
begin
|
begin
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
next_state_tx = TX_DATA1_1;
|
next_state_tx_rx = RX_TX_DATA1_1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
next_state_tx = TX_DATA1_2;
|
next_state_tx_rx = RX_TX_DATA1_2;
|
end
|
end
|
end
|
end
|
TX_DATA1_2:
|
RX_TX_DATA1_2:
|
begin
|
begin
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
next_state_tx = TX_DATA1_2;
|
next_state_tx_rx = RX_TX_DATA1_2;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
next_state_tx = TX_DATA1_3;
|
next_state_tx_rx = RX_TX_DATA1_3;
|
end
|
end
|
end
|
end
|
TX_DATA1_3:
|
RX_TX_DATA1_3:
|
begin
|
begin
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
next_state_tx = TX_DATA1_3;
|
next_state_tx_rx = RX_TX_DATA1_3;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
next_state_tx = TX_DATA1_4;
|
next_state_tx_rx = RX_TX_DATA1_4;
|
end
|
end
|
end
|
end
|
TX_DATA1_4:
|
RX_TX_DATA1_4:
|
begin
|
begin
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
next_state_tx = TX_DATA1_4;
|
next_state_tx_rx = RX_TX_DATA1_4;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
next_state_tx = TX_DATA1_5;
|
next_state_tx_rx = RX_TX_DATA1_5;
|
end
|
end
|
end
|
end
|
TX_DATA1_5:
|
RX_TX_DATA1_5:
|
begin
|
begin
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
next_state_tx = TX_DATA1_5;
|
next_state_tx_rx = RX_TX_DATA1_5;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
next_state_tx = TX_DATA1_6;
|
next_state_tx_rx = RX_TX_DATA1_6;
|
end
|
end
|
end
|
end
|
TX_DATA1_6:
|
RX_TX_DATA1_6:
|
begin
|
begin
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
next_state_tx = TX_DATA1_6;
|
next_state_tx_rx = RX_TX_DATA1_6;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
next_state_tx = TX_DATA1_7;
|
next_state_tx_rx = RX_TX_DATA1_7;
|
end
|
end
|
end
|
end
|
TX_DATA1_7:
|
RX_TX_DATA1_7:
|
begin
|
begin
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
next_state_tx = TX_DATA1_7;
|
next_state_tx_rx = RX_TX_DATA1_7;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
next_state_tx = TX_DATA1_8;
|
next_state_tx_rx = RX_TX_DATA1_8;
|
end
|
end
|
end
|
end
|
TX_DATA1_8:
|
RX_TX_DATA1_8:
|
begin
|
begin
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
next_state_tx = TX_DATA1_8;
|
next_state_tx_rx = RX_TX_DATA1_8;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
next_state_tx = TX_RESPONSE_DATA1_1;
|
next_state_tx_rx = RX_TX_RESPONSE_DATA1_1;
|
end
|
end
|
end
|
end
|
TX_RESPONSE_DATA1_1:
|
RX_TX_RESPONSE_DATA1_1:
|
begin
|
begin
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
next_state_tx = TX_RESPONSE_DATA1_1;
|
next_state_tx_rx = RX_TX_RESPONSE_DATA1_1;
|
end
|
end
|
else if(RESPONSE == 1'b0)//ACK
|
else if(RESPONSE == 1'b0)//ACK
|
begin
|
begin
|
next_state_tx = TX_DELAY_BYTES;
|
next_state_tx_rx = RX_TX_DELAY_BYTES;
|
end
|
end
|
else if(RESPONSE == 1'b1)//NACK
|
else if(RESPONSE == 1'b1)//NACK
|
begin
|
begin
|
next_state_tx = TX_NACK;
|
next_state_tx_rx = RX_TX_NACK;
|
end
|
end
|
end
|
end
|
TX_DELAY_BYTES://THIS FORM WORKS
|
RX_TX_DELAY_BYTES://THIS FORM WORKS
|
begin
|
begin
|
|
|
|
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
next_state_tx = TX_DELAY_BYTES;
|
next_state_tx_rx = RX_TX_DELAY_BYTES;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
|
|
if(count_tx == 2'd0)
|
if(count_tx == 2'd0)
|
begin
|
begin
|
next_state_tx = TX_ADRESS_1;
|
next_state_tx_rx = RX_TX_ADRESS_1;
|
end
|
end
|
else if(count_tx == 2'd1)
|
else if(count_tx == 2'd1)
|
begin
|
begin
|
next_state_tx = TX_DATA0_1;
|
next_state_tx_rx = RX_TX_DATA0_1;
|
end
|
end
|
else if(count_tx == 2'd2)
|
else if(count_tx == 2'd2)
|
begin
|
begin
|
next_state_tx = TX_DATA1_1;
|
next_state_tx_rx = RX_TX_DATA1_1;
|
end
|
end
|
else if(count_tx == 2'd3)
|
else if(count_tx == 2'd3)
|
begin
|
begin
|
next_state_tx = TX_STOP;
|
next_state_tx_rx = RX_TX_STOP;
|
end
|
end
|
|
|
end
|
end
|
|
|
end
|
end
|
TX_NACK://NOT TESTED YET !!!!
|
RX_TX_NACK://NOT TESTED YET !!!!
|
begin
|
begin
|
if(count_send_data != DATA_CONFIG_REG[13:2]*2'd2)
|
if(count_send_data != DATA_CONFIG_REG[13:2]*2'd2)
|
begin
|
begin
|
next_state_tx = TX_NACK;
|
next_state_tx_rx = RX_TX_NACK;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if(count_tx == 2'd0)
|
if(count_tx == 2'd0)
|
begin
|
begin
|
next_state_tx = TX_CONTROLIN_1;
|
next_state_tx_rx = RX_TX_CONTROLIN_1;
|
end
|
end
|
else if(count_tx == 2'd1)
|
else if(count_tx == 2'd1)
|
begin
|
begin
|
next_state_tx = TX_ADRESS_1;
|
next_state_tx_rx = RX_TX_ADRESS_1;
|
end
|
end
|
else if(count_tx == 2'd2)
|
else if(count_tx == 2'd2)
|
begin
|
begin
|
next_state_tx = TX_DATA0_1;
|
next_state_tx_rx = RX_TX_DATA0_1;
|
end
|
end
|
else if(count_tx == 2'd3)
|
else if(count_tx == 2'd3)
|
begin
|
begin
|
next_state_tx = TX_DATA1_1;
|
next_state_tx_rx = RX_TX_DATA1_1;
|
end
|
end
|
end
|
end
|
end
|
end
|
TX_STOP://THIS WORK
|
RX_TX_STOP://THIS WORK
|
begin
|
begin
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
if(count_send_data != DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
next_state_tx = TX_STOP;
|
next_state_tx_rx = RX_TX_STOP;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
next_state_tx = TX_IDLE;
|
next_state_tx_rx = RX_TX_IDLE;
|
end
|
end
|
end
|
end
|
default:
|
default:
|
begin
|
begin
|
next_state_tx = TX_IDLE;
|
next_state_tx_rx = RX_TX_IDLE;
|
end
|
end
|
endcase
|
endcase
|
|
|
|
|
end
|
end
|
|
|
|
|
|
|
//SEQUENTIAL TX
|
//SEQUENTIAL TX
|
always@(posedge PCLK)
|
always@(posedge PCLK)
|
begin
|
begin
|
|
|
//RESET SYNC
|
//RESET SYNC
|
if(!PRESETn)
|
if(!PRESETn)
|
begin
|
begin
|
//SIGNALS MUST BE RESETED
|
//SIGNALS MUST BE RESETED
|
count_send_data <= 12'd0;
|
count_send_data <= 12'd0;
|
state_tx <= TX_IDLE;
|
state_tx_rx <= RX_TX_IDLE;
|
SDA_OUT<= 1'b1;
|
SDA_OUT<= 1'b1;
|
fifo_tx_rd_en <= 1'b0;
|
fifo_tx_rd_en <= 1'b0;
|
count_tx <= 2'd0;
|
count_tx <= 2'd0;
|
BR_CLK_O <= 1'b1;
|
BR_CLK_O <= 1'b1;
|
RESPONSE<= 1'b0;
|
RESPONSE<= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
|
|
// SEQUENTIAL FUN START
|
// SEQUENTIAL FUN START
|
state_tx <= next_state_tx;
|
state_tx_rx <= next_state_tx_rx;
|
|
|
case(state_tx)
|
case(state_tx_rx)
|
TX_IDLE:
|
RX_TX_IDLE:
|
begin
|
begin
|
|
|
fifo_tx_rd_en <= 1'b0;
|
fifo_tx_rd_en <= 1'b0;
|
|
|
|
|
| Line 783... |
Line 786... |
SDA_OUT<= 1'b1;
|
SDA_OUT<= 1'b1;
|
BR_CLK_O <= 1'b1;
|
BR_CLK_O <= 1'b1;
|
end
|
end
|
|
|
end
|
end
|
TX_START:
|
RX_TX_START:
|
begin
|
begin
|
|
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
count_send_data <= count_send_data + 12'd1;
|
count_send_data <= count_send_data + 12'd1;
|
| Line 803... |
Line 806... |
SDA_OUT<=fifo_tx_data_out[0:0];
|
SDA_OUT<=fifo_tx_data_out[0:0];
|
count_tx <= 2'd0;
|
count_tx <= 2'd0;
|
end
|
end
|
|
|
end
|
end
|
TX_CONTROLIN_1:
|
RX_TX_CONTROLIN_1:
|
begin
|
begin
|
|
|
|
|
|
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
| Line 837... |
Line 840... |
end
|
end
|
|
|
|
|
end
|
end
|
|
|
TX_CONTROLIN_2:
|
RX_TX_CONTROLIN_2:
|
begin
|
begin
|
|
|
|
|
|
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
| Line 868... |
Line 871... |
SDA_OUT<=fifo_tx_data_out[2:2];
|
SDA_OUT<=fifo_tx_data_out[2:2];
|
end
|
end
|
|
|
end
|
end
|
|
|
TX_CONTROLIN_3:
|
RX_TX_CONTROLIN_3:
|
begin
|
begin
|
|
|
|
|
|
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
| Line 900... |
Line 903... |
end
|
end
|
|
|
|
|
|
|
end
|
end
|
TX_CONTROLIN_4:
|
RX_TX_CONTROLIN_4:
|
begin
|
begin
|
|
|
|
|
|
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
| Line 931... |
Line 934... |
SDA_OUT<=fifo_tx_data_out[4:4];
|
SDA_OUT<=fifo_tx_data_out[4:4];
|
end
|
end
|
|
|
end
|
end
|
|
|
TX_CONTROLIN_5:
|
RX_TX_CONTROLIN_5:
|
begin
|
begin
|
|
|
|
|
|
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
| Line 963... |
Line 966... |
end
|
end
|
|
|
end
|
end
|
|
|
|
|
TX_CONTROLIN_6:
|
RX_TX_CONTROLIN_6:
|
begin
|
begin
|
|
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
count_send_data <= count_send_data + 12'd1;
|
count_send_data <= count_send_data + 12'd1;
|
| Line 993... |
Line 996... |
end
|
end
|
|
|
|
|
end
|
end
|
|
|
TX_CONTROLIN_7:
|
RX_TX_CONTROLIN_7:
|
begin
|
begin
|
|
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
count_send_data <= count_send_data + 12'd1;
|
count_send_data <= count_send_data + 12'd1;
|
| Line 1022... |
Line 1025... |
SDA_OUT<=fifo_tx_data_out[7:7];
|
SDA_OUT<=fifo_tx_data_out[7:7];
|
end
|
end
|
|
|
|
|
end
|
end
|
TX_CONTROLIN_8:
|
RX_TX_CONTROLIN_8:
|
begin
|
begin
|
|
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
count_send_data <= count_send_data + 12'd1;
|
count_send_data <= count_send_data + 12'd1;
|
| Line 1051... |
Line 1054... |
SDA_OUT<= 1'b0;
|
SDA_OUT<= 1'b0;
|
end
|
end
|
|
|
|
|
end
|
end
|
TX_RESPONSE_CIN:
|
RX_TX_RESPONSE_CIN:
|
begin
|
begin
|
|
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
count_send_data <= count_send_data + 12'd1;
|
count_send_data <= count_send_data + 12'd1;
|
| Line 1081... |
Line 1084... |
count_send_data <= 12'd0;
|
count_send_data <= 12'd0;
|
end
|
end
|
|
|
|
|
end
|
end
|
TX_ADRESS_1:
|
RX_TX_ADRESS_1:
|
begin
|
begin
|
|
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
count_send_data <= count_send_data + 12'd1;
|
count_send_data <= count_send_data + 12'd1;
|
| Line 1109... |
Line 1112... |
count_send_data <= 12'd0;
|
count_send_data <= 12'd0;
|
SDA_OUT<=fifo_tx_data_out[9:9];
|
SDA_OUT<=fifo_tx_data_out[9:9];
|
end
|
end
|
|
|
end
|
end
|
TX_ADRESS_2:
|
RX_TX_ADRESS_2:
|
begin
|
begin
|
|
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
count_send_data <= count_send_data + 12'd1;
|
count_send_data <= count_send_data + 12'd1;
|
| Line 1137... |
Line 1140... |
count_send_data <= 12'd0;
|
count_send_data <= 12'd0;
|
SDA_OUT<=fifo_tx_data_out[10:10];
|
SDA_OUT<=fifo_tx_data_out[10:10];
|
end
|
end
|
|
|
end
|
end
|
TX_ADRESS_3:
|
RX_TX_ADRESS_3:
|
begin
|
begin
|
|
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
count_send_data <= count_send_data + 12'd1;
|
count_send_data <= count_send_data + 12'd1;
|
| Line 1165... |
Line 1168... |
count_send_data <= 12'd0;
|
count_send_data <= 12'd0;
|
SDA_OUT<=fifo_tx_data_out[11:11];
|
SDA_OUT<=fifo_tx_data_out[11:11];
|
end
|
end
|
|
|
end
|
end
|
TX_ADRESS_4:
|
RX_TX_ADRESS_4:
|
begin
|
begin
|
|
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
count_send_data <= count_send_data + 12'd1;
|
count_send_data <= count_send_data + 12'd1;
|
| Line 1192... |
Line 1195... |
begin
|
begin
|
count_send_data <= 12'd0;
|
count_send_data <= 12'd0;
|
SDA_OUT<=fifo_tx_data_out[12:12];
|
SDA_OUT<=fifo_tx_data_out[12:12];
|
end
|
end
|
end
|
end
|
TX_ADRESS_5:
|
RX_TX_ADRESS_5:
|
begin
|
begin
|
|
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
count_send_data <= count_send_data + 12'd1;
|
count_send_data <= count_send_data + 12'd1;
|
| Line 1221... |
Line 1224... |
SDA_OUT<=fifo_tx_data_out[13:13];
|
SDA_OUT<=fifo_tx_data_out[13:13];
|
end
|
end
|
|
|
|
|
end
|
end
|
TX_ADRESS_6:
|
RX_TX_ADRESS_6:
|
begin
|
begin
|
|
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
count_send_data <= count_send_data + 12'd1;
|
count_send_data <= count_send_data + 12'd1;
|
| Line 1249... |
Line 1252... |
count_send_data <= 12'd0;
|
count_send_data <= 12'd0;
|
SDA_OUT<=fifo_tx_data_out[14:14];
|
SDA_OUT<=fifo_tx_data_out[14:14];
|
end
|
end
|
|
|
end
|
end
|
TX_ADRESS_7:
|
RX_TX_ADRESS_7:
|
begin
|
begin
|
|
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
count_send_data <= count_send_data + 12'd1;
|
count_send_data <= count_send_data + 12'd1;
|
| Line 1278... |
Line 1281... |
SDA_OUT<=fifo_tx_data_out[15:15];
|
SDA_OUT<=fifo_tx_data_out[15:15];
|
end
|
end
|
|
|
|
|
end
|
end
|
TX_ADRESS_8:
|
RX_TX_ADRESS_8:
|
begin
|
begin
|
|
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
count_send_data <= count_send_data + 12'd1;
|
count_send_data <= count_send_data + 12'd1;
|
| Line 1306... |
Line 1309... |
count_send_data <= 12'd0;
|
count_send_data <= 12'd0;
|
SDA_OUT<=1'b0;
|
SDA_OUT<=1'b0;
|
end
|
end
|
|
|
end
|
end
|
TX_RESPONSE_ADRESS:
|
RX_TX_RESPONSE_ADRESS:
|
begin
|
begin
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
count_send_data <= count_send_data + 12'd1;
|
count_send_data <= count_send_data + 12'd1;
|
|
|
| Line 1334... |
Line 1337... |
begin
|
begin
|
count_send_data <= 12'd0;
|
count_send_data <= 12'd0;
|
end
|
end
|
|
|
end
|
end
|
TX_DATA0_1:
|
RX_TX_DATA0_1:
|
begin
|
begin
|
|
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
count_send_data <= count_send_data + 12'd1;
|
count_send_data <= count_send_data + 12'd1;
|
| Line 1363... |
Line 1366... |
SDA_OUT<=fifo_tx_data_out[17:17];
|
SDA_OUT<=fifo_tx_data_out[17:17];
|
end
|
end
|
|
|
|
|
end
|
end
|
TX_DATA0_2:
|
RX_TX_DATA0_2:
|
begin
|
begin
|
|
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
count_send_data <= count_send_data + 12'd1;
|
count_send_data <= count_send_data + 12'd1;
|
| Line 1392... |
Line 1395... |
SDA_OUT<=fifo_tx_data_out[18:18];
|
SDA_OUT<=fifo_tx_data_out[18:18];
|
end
|
end
|
|
|
|
|
end
|
end
|
TX_DATA0_3:
|
RX_TX_DATA0_3:
|
begin
|
begin
|
|
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
count_send_data <= count_send_data + 12'd1;
|
count_send_data <= count_send_data + 12'd1;
|
| Line 1420... |
Line 1423... |
count_send_data <= 12'd0;
|
count_send_data <= 12'd0;
|
SDA_OUT<=fifo_tx_data_out[19:19];
|
SDA_OUT<=fifo_tx_data_out[19:19];
|
end
|
end
|
|
|
end
|
end
|
TX_DATA0_4:
|
RX_TX_DATA0_4:
|
begin
|
begin
|
|
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
count_send_data <= count_send_data + 12'd1;
|
count_send_data <= count_send_data + 12'd1;
|
| Line 1448... |
Line 1451... |
count_send_data <= 12'd0;
|
count_send_data <= 12'd0;
|
SDA_OUT<=fifo_tx_data_out[20:20];
|
SDA_OUT<=fifo_tx_data_out[20:20];
|
end
|
end
|
|
|
end
|
end
|
TX_DATA0_5:
|
RX_TX_DATA0_5:
|
begin
|
begin
|
|
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
count_send_data <= count_send_data + 12'd1;
|
count_send_data <= count_send_data + 12'd1;
|
| Line 1476... |
Line 1479... |
count_send_data <= 12'd0;
|
count_send_data <= 12'd0;
|
SDA_OUT<=fifo_tx_data_out[21:21];
|
SDA_OUT<=fifo_tx_data_out[21:21];
|
end
|
end
|
|
|
end
|
end
|
TX_DATA0_6:
|
RX_TX_DATA0_6:
|
begin
|
begin
|
|
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
count_send_data <= count_send_data + 12'd1;
|
count_send_data <= count_send_data + 12'd1;
|
| Line 1504... |
Line 1507... |
count_send_data <= 12'd0;
|
count_send_data <= 12'd0;
|
SDA_OUT<=fifo_tx_data_out[22:22];
|
SDA_OUT<=fifo_tx_data_out[22:22];
|
end
|
end
|
|
|
end
|
end
|
TX_DATA0_7:
|
RX_TX_DATA0_7:
|
begin
|
begin
|
|
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
count_send_data <= count_send_data + 12'd1;
|
count_send_data <= count_send_data + 12'd1;
|
| Line 1532... |
Line 1535... |
count_send_data <= 12'd0;
|
count_send_data <= 12'd0;
|
SDA_OUT<=fifo_tx_data_out[23:23];
|
SDA_OUT<=fifo_tx_data_out[23:23];
|
end
|
end
|
|
|
end
|
end
|
TX_DATA0_8:
|
RX_TX_DATA0_8:
|
begin
|
begin
|
|
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
count_send_data <= count_send_data + 12'd1;
|
count_send_data <= count_send_data + 12'd1;
|
| Line 1561... |
Line 1564... |
count_send_data <= 12'd0;
|
count_send_data <= 12'd0;
|
SDA_OUT<=1'b0;
|
SDA_OUT<=1'b0;
|
end
|
end
|
|
|
end
|
end
|
TX_RESPONSE_DATA0_1:
|
RX_TX_RESPONSE_DATA0_1:
|
begin
|
begin
|
|
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
count_send_data <= count_send_data + 12'd1;
|
count_send_data <= count_send_data + 12'd1;
|
| Line 1590... |
Line 1593... |
begin
|
begin
|
count_send_data <= 12'd0;
|
count_send_data <= 12'd0;
|
end
|
end
|
|
|
end
|
end
|
TX_DATA1_1:
|
RX_TX_DATA1_1:
|
begin
|
begin
|
|
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
count_send_data <= count_send_data + 12'd1;
|
count_send_data <= count_send_data + 12'd1;
|
| Line 1620... |
Line 1623... |
|
|
end
|
end
|
|
|
|
|
end
|
end
|
TX_DATA1_2:
|
RX_TX_DATA1_2:
|
begin
|
begin
|
|
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
count_send_data <= count_send_data + 12'd1;
|
count_send_data <= count_send_data + 12'd1;
|
| Line 1648... |
Line 1651... |
count_send_data <= 12'd0;
|
count_send_data <= 12'd0;
|
SDA_OUT<=fifo_tx_data_out[26:26];
|
SDA_OUT<=fifo_tx_data_out[26:26];
|
end
|
end
|
|
|
end
|
end
|
TX_DATA1_3:
|
RX_TX_DATA1_3:
|
begin
|
begin
|
|
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
count_send_data <= count_send_data + 12'd1;
|
count_send_data <= count_send_data + 12'd1;
|
| Line 1677... |
Line 1680... |
count_send_data <= 12'd0;
|
count_send_data <= 12'd0;
|
SDA_OUT<=fifo_tx_data_out[27:27];
|
SDA_OUT<=fifo_tx_data_out[27:27];
|
end
|
end
|
|
|
end
|
end
|
TX_DATA1_4:
|
RX_TX_DATA1_4:
|
begin
|
begin
|
|
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
count_send_data <= count_send_data + 12'd1;
|
count_send_data <= count_send_data + 12'd1;
|
| Line 1706... |
Line 1709... |
count_send_data <= 12'd0;
|
count_send_data <= 12'd0;
|
SDA_OUT<=fifo_tx_data_out[28:28];
|
SDA_OUT<=fifo_tx_data_out[28:28];
|
end
|
end
|
|
|
end
|
end
|
TX_DATA1_5:
|
RX_TX_DATA1_5:
|
begin
|
begin
|
|
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
count_send_data <= count_send_data + 12'd1;
|
count_send_data <= count_send_data + 12'd1;
|
| Line 1735... |
Line 1738... |
count_send_data <= 12'd0;
|
count_send_data <= 12'd0;
|
SDA_OUT<=fifo_tx_data_out[29:29];
|
SDA_OUT<=fifo_tx_data_out[29:29];
|
end
|
end
|
|
|
end
|
end
|
TX_DATA1_6:
|
RX_TX_DATA1_6:
|
begin
|
begin
|
|
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
count_send_data <= count_send_data + 12'd1;
|
count_send_data <= count_send_data + 12'd1;
|
| Line 1764... |
Line 1767... |
count_send_data <= 12'd0;
|
count_send_data <= 12'd0;
|
SDA_OUT<=fifo_tx_data_out[30:30];
|
SDA_OUT<=fifo_tx_data_out[30:30];
|
end
|
end
|
|
|
end
|
end
|
TX_DATA1_7:
|
RX_TX_DATA1_7:
|
begin
|
begin
|
|
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
count_send_data <= count_send_data + 12'd1;
|
count_send_data <= count_send_data + 12'd1;
|
| Line 1794... |
Line 1797... |
SDA_OUT<=fifo_tx_data_out[31:31];
|
SDA_OUT<=fifo_tx_data_out[31:31];
|
end
|
end
|
|
|
|
|
end
|
end
|
TX_DATA1_8:
|
RX_TX_DATA1_8:
|
begin
|
begin
|
|
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
count_send_data <= count_send_data + 12'd1;
|
count_send_data <= count_send_data + 12'd1;
|
| Line 1823... |
Line 1826... |
count_send_data <= 12'd0;
|
count_send_data <= 12'd0;
|
SDA_OUT<=1'b0;
|
SDA_OUT<=1'b0;
|
end
|
end
|
|
|
end
|
end
|
TX_RESPONSE_DATA1_1:
|
RX_TX_RESPONSE_DATA1_1:
|
begin
|
begin
|
//fifo_tx_rd_en <= 1'b1;
|
//fifo_tx_rd_en <= 1'b1;
|
|
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
| Line 1854... |
Line 1857... |
count_send_data <= 12'd0;
|
count_send_data <= 12'd0;
|
fifo_tx_rd_en <= 1'b1;
|
fifo_tx_rd_en <= 1'b1;
|
end
|
end
|
|
|
end
|
end
|
TX_DELAY_BYTES:
|
RX_TX_DELAY_BYTES:
|
begin
|
begin
|
|
|
fifo_tx_rd_en <= 1'b0;
|
fifo_tx_rd_en <= 1'b0;
|
|
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
| Line 1896... |
Line 1899... |
|
|
end
|
end
|
|
|
end
|
end
|
//THIS BLOCK MUST BE CHECKED WITH CARE
|
//THIS BLOCK MUST BE CHECKED WITH CARE
|
TX_NACK:// MORE A RESTART
|
RX_TX_NACK:// MORE A RESTART
|
begin
|
begin
|
fifo_tx_rd_en <= 1'b0;
|
fifo_tx_rd_en <= 1'b0;
|
|
|
if(count_send_data < DATA_CONFIG_REG[13:2]*2'd2)
|
if(count_send_data < DATA_CONFIG_REG[13:2]*2'd2)
|
begin
|
begin
|
| Line 1959... |
Line 1962... |
end
|
end
|
|
|
|
|
end
|
end
|
end
|
end
|
TX_STOP:
|
RX_TX_STOP:
|
begin
|
begin
|
|
|
BR_CLK_O <= 1'b1;
|
BR_CLK_O <= 1'b1;
|
|
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
if(count_send_data < DATA_CONFIG_REG[13:2])
|
| Line 1994... |
Line 1997... |
end
|
end
|
|
|
|
|
end
|
end
|
|
|
|
|
// RX PARAMETERS USED TO STATE MACHINE
|
|
|
|
localparam [5:0] RX_IDLE = 6'd0, //IDLE
|
|
|
|
RX_START = 6'd1,//START BIT
|
|
|
|
RX_CONTROLIN_1 = 6'd2, //START BYTE
|
|
RX_CONTROLIN_2 = 6'd3,
|
|
RX_CONTROLIN_3 = 6'd4,
|
|
RX_CONTROLIN_4 = 6'd5,
|
|
RX_CONTROLIN_5 = 6'd6,
|
|
RX_CONTROLIN_6 = 6'd7,
|
|
RX_CONTROLIN_7 = 6'd8,
|
|
RX_CONTROLIN_8 = 6'd9, //END FIRST BYTE
|
|
|
|
RX_RESPONSE_CIN =6'd10, //RESPONSE
|
|
|
|
RX_ADRESS_1 = 6'd11,//START BYTE
|
|
RX_ADRESS_2 = 6'd12,
|
|
RX_ADRESS_3 = 6'd13,
|
|
RX_ADRESS_4 = 6'd14,
|
|
RX_ADRESS_5 = 6'd15,
|
|
RX_ADRESS_6 = 6'd16,
|
|
RX_ADRESS_7 = 6'd17,
|
|
RX_ADRESS_8 = 6'd18,//END FIRST BYTE
|
|
|
|
RX_RESPONSE_ADRESS =6'd19, //RESPONSE
|
|
|
|
RX_DATA0_1 = 6'd20,//START BYTE
|
|
RX_DATA0_2 = 6'd21,
|
|
RX_DATA0_3 = 6'd22,
|
|
RX_DATA0_4 = 6'd23,
|
|
RX_DATA0_5 = 6'd24,
|
|
RX_DATA0_6 = 6'd25,
|
|
RX_DATA0_7 = 6'd26,
|
|
RX_DATA0_8 = 6'd27,//END FIRST BYTE
|
|
|
|
RX_RESPONSE_DATA0_1 = 6'd28, //RESPONSE
|
|
|
|
RX_DATA1_1 = 6'd29,//START BYTE
|
|
RX_DATA1_2 = 6'd30,
|
|
RX_DATA1_3 = 6'd31,
|
|
RX_DATA1_4 = 6'd32,
|
|
RX_DATA1_5 = 6'd33,
|
|
RX_DATA1_6 = 6'd34,
|
|
RX_DATA1_7 = 6'd35,
|
|
RX_DATA1_8 = 6'd36,//END FIRST BYTE
|
|
|
|
RX_RESPONSE_DATA1_1 = 6'd37,//RESPONSE
|
|
|
|
RX_DELAY_BYTES = 6'd38,//USED ONLY IN ACK TO DELAY BETWEEN
|
|
RX_NACK = 6'd39,//USED ONLY IN ACK TO DELAY BETWEEN BYTES
|
|
RX_STOP = 6'd40;//USED TO SEND STOP BIT
|
|
|
|
//STATE CONTROL
|
|
reg [5:0] state_rx;
|
|
reg [5:0] next_state_rx;
|
|
|
|
reg [11:0] count_receive_data;
|
|
|
|
reg [1:0] count_rx;
|
|
|
|
//COMBINATIONAL BLOCK RX
|
|
|
|
always@(*)
|
|
begin
|
|
|
|
|
|
next_state_rx = state_rx;
|
|
|
|
case(state_rx)//STATE_RX IS MORE SECURE CHANGE ONLY IF YOU KNOW WHAT ARE YOU DOING
|
|
RX_IDLE:
|
|
begin
|
|
//OBEYING SPEC
|
|
if(DATA_CONFIG_REG[1] == 1'b0 && DATA_CONFIG_REG[0] == 1'b0)
|
|
begin
|
|
next_state_rx = RX_IDLE;
|
|
end
|
|
else if(DATA_CONFIG_REG[1] == 1'b1 && DATA_CONFIG_REG[0] == 1'b1)
|
|
begin
|
|
next_state_rx = RX_IDLE;
|
|
end
|
|
else if(DATA_CONFIG_REG[1] == 1'b1 && DATA_CONFIG_REG[0] == 1'b0 && SDA == 1'b0 && SCL == 1'b1)
|
|
begin
|
|
next_state_rx = RX_START;
|
|
end
|
|
end
|
|
RX_START:
|
|
begin
|
|
|
|
if(SDA == 1'b0 && SCL == 1'b1)
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_START;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_CONTROLIN_1;
|
|
end
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_IDLE;
|
|
end
|
|
end
|
|
RX_CONTROLIN_1:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_CONTROLIN_1;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_CONTROLIN_2;
|
|
end
|
|
end
|
|
RX_CONTROLIN_2:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_CONTROLIN_2;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_CONTROLIN_3;
|
|
end
|
|
end
|
|
RX_CONTROLIN_3:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_CONTROLIN_3;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_CONTROLIN_4;
|
|
end
|
|
end
|
|
RX_CONTROLIN_4:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_CONTROLIN_4;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_CONTROLIN_5;
|
|
end
|
|
end
|
|
RX_CONTROLIN_5:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_CONTROLIN_5;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_CONTROLIN_6;
|
|
end
|
|
end
|
|
RX_CONTROLIN_6:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_CONTROLIN_6;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_CONTROLIN_7;
|
|
end
|
|
end
|
|
RX_CONTROLIN_7:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_CONTROLIN_7;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_CONTROLIN_8;
|
|
end
|
|
end
|
|
RX_CONTROLIN_8:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_CONTROLIN_8;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_RESPONSE_CIN;
|
|
end
|
|
end
|
|
RX_RESPONSE_CIN:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_CONTROLIN_8;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_RESPONSE_CIN;
|
|
end
|
|
end
|
|
|
|
RX_ADRESS_1:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_ADRESS_1;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_ADRESS_2;
|
|
end
|
|
end
|
|
RX_ADRESS_2:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_ADRESS_2;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_ADRESS_3;
|
|
end
|
|
end
|
|
RX_ADRESS_3:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_ADRESS_3;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_ADRESS_4;
|
|
end
|
|
end
|
|
RX_ADRESS_4:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_ADRESS_4;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_ADRESS_5;
|
|
end
|
|
end
|
|
RX_ADRESS_5:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_ADRESS_5;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_ADRESS_6;
|
|
end
|
|
end
|
|
RX_ADRESS_6:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_ADRESS_6;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_ADRESS_7;
|
|
end
|
|
end
|
|
RX_ADRESS_7:
|
|
begin
|
|
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_ADRESS_7;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_ADRESS_8;
|
|
end
|
|
|
|
end
|
|
RX_ADRESS_8:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_ADRESS_8;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_RESPONSE_ADRESS;
|
|
end
|
|
end
|
|
RX_RESPONSE_ADRESS:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_RESPONSE_ADRESS;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_DATA0_1;
|
|
end
|
|
end
|
|
|
|
RX_DATA0_1:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_DATA0_1;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_DATA0_2;
|
|
end
|
|
end
|
|
RX_DATA0_2:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_DATA0_2;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_DATA0_3;
|
|
end
|
|
end
|
|
RX_DATA0_3:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_DATA0_3;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_DATA0_4;
|
|
end
|
|
end
|
|
RX_DATA0_4:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_DATA0_4;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_DATA0_5;
|
|
end
|
|
end
|
|
RX_DATA0_5:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_DATA0_5;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_DATA0_6;
|
|
end
|
|
end
|
|
RX_DATA0_6:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_DATA0_6;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_DATA0_7;
|
|
end
|
|
end
|
|
RX_DATA0_7:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_DATA0_7;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_DATA0_8;
|
|
end
|
|
end
|
|
RX_DATA0_8:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_DATA0_8;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_RESPONSE_DATA0_1;
|
|
end
|
|
end
|
|
RX_RESPONSE_DATA0_1:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_RESPONSE_DATA0_1;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_DATA1_1;
|
|
end
|
|
end
|
|
RX_DATA1_1:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_DATA1_1;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_DATA1_2;
|
|
end
|
|
end
|
|
RX_DATA1_2:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_DATA1_1;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_DATA1_3;
|
|
end
|
|
end
|
|
RX_DATA1_3:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_DATA1_3;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_DATA1_4;
|
|
end
|
|
end
|
|
RX_DATA1_4:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_DATA1_4;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_DATA1_5;
|
|
end
|
|
end
|
|
RX_DATA1_5:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_DATA1_5;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_DATA1_6;
|
|
end
|
|
end
|
|
RX_DATA1_6:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_DATA1_6;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_DATA1_7;
|
|
end
|
|
end
|
|
RX_DATA1_7:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_DATA1_7;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_DATA1_8;
|
|
end
|
|
end
|
|
RX_DATA1_8:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_DATA1_8;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_RESPONSE_DATA1_1;
|
|
end
|
|
end
|
|
RX_RESPONSE_DATA1_1:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_RESPONSE_DATA1_1;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_DELAY_BYTES;
|
|
end
|
|
end
|
|
RX_DELAY_BYTES:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_DELAY_BYTES;
|
|
end
|
|
else
|
|
begin
|
|
|
|
if(count_rx == 2'd0)
|
|
begin
|
|
next_state_rx = RX_ADRESS_1;
|
|
end
|
|
else if(count_rx == 2'd1)
|
|
begin
|
|
next_state_rx = RX_DATA0_1;
|
|
end
|
|
else if(count_rx == 2'd2)
|
|
begin
|
|
next_state_rx = RX_DATA1_1;
|
|
end
|
|
else if(count_rx == 2'd3)
|
|
begin
|
|
next_state_rx = RX_STOP;
|
|
end
|
|
|
|
end
|
|
end
|
|
RX_NACK:
|
|
begin
|
|
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2]*2'd2)
|
|
begin
|
|
next_state_rx = RX_NACK;
|
|
end
|
|
else
|
|
begin
|
|
if(count_rx == 2'd0)
|
|
begin
|
|
next_state_rx = RX_CONTROLIN_1;
|
|
end
|
|
else if(count_rx == 2'd1)
|
|
begin
|
|
next_state_rx = RX_ADRESS_1;
|
|
end
|
|
else if(count_rx == 2'd2)
|
|
begin
|
|
next_state_rx = RX_DATA0_1;
|
|
end
|
|
else if(count_rx == 2'd3)
|
|
begin
|
|
next_state_rx = RX_DATA1_1;
|
|
end
|
|
end
|
|
|
|
|
|
end
|
|
RX_STOP:
|
|
begin
|
|
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_STOP;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_IDLE;
|
|
end
|
|
|
|
end
|
|
default:
|
|
begin
|
|
next_state_rx = RX_IDLE;
|
|
end
|
|
endcase
|
|
end
|
|
|
|
|
|
//SEQUENTIAL BLOCK RX
|
|
|
|
always@(posedge PCLK)
|
|
begin
|
|
|
|
if(!PRESETn)
|
|
begin
|
|
//SIGNALS MUST BE RESETED
|
|
count_receive_data <= 12'd0;
|
|
state_rx <= RX_IDLE;
|
|
fifo_rx_wr_en <= 1'b0;
|
|
count_rx <= 2'd0;
|
|
end
|
|
else
|
|
begin
|
|
|
|
state_rx <= next_state_rx;
|
|
|
|
case(state_rx)//STATE_RX IS MORE SECURE CHANGE ONLY IF YOU KNOW WHAT ARE YOU DOING
|
|
RX_IDLE:
|
|
begin
|
|
if(SDA == 1'b0 && SCL == 1'b1)
|
|
begin
|
|
count_receive_data <= count_receive_data +12'd1;
|
|
end
|
|
else
|
|
begin
|
|
count_receive_data <= 12'd0;
|
|
end
|
|
end
|
|
RX_START:
|
|
begin
|
|
if(SDA == 1'b0 && SCL == 1'b0 && count_receive_data < DATA_CONFIG_REG[13:2] )
|
|
begin
|
|
count_receive_data <= count_receive_data +12'd1;
|
|
end
|
|
else
|
|
begin
|
|
count_receive_data <= 12'd0;
|
|
end
|
|
end
|
|
RX_CONTROLIN_1:
|
|
begin
|
|
|
|
end
|
|
RX_CONTROLIN_2:
|
|
begin
|
|
|
|
end
|
|
RX_CONTROLIN_3:
|
|
begin
|
|
|
|
end
|
|
RX_CONTROLIN_4:
|
|
begin
|
|
|
|
end
|
|
RX_CONTROLIN_5:
|
|
begin
|
|
|
|
end
|
|
RX_CONTROLIN_6:
|
|
begin
|
|
|
|
end
|
|
RX_CONTROLIN_7:
|
|
begin
|
|
|
|
end
|
|
RX_CONTROLIN_8:
|
|
begin
|
|
|
|
end
|
|
RX_RESPONSE_CIN:
|
|
begin
|
|
|
|
end
|
|
RX_ADRESS_1:
|
|
begin
|
|
end
|
|
RX_ADRESS_2:
|
|
begin
|
|
end
|
|
RX_ADRESS_3:
|
|
begin
|
|
end
|
|
RX_ADRESS_4:
|
|
begin
|
|
end
|
|
RX_ADRESS_5:
|
|
begin
|
|
end
|
|
RX_ADRESS_6:
|
|
begin
|
|
end
|
|
RX_ADRESS_7:
|
|
begin
|
|
end
|
|
RX_ADRESS_8:
|
|
begin
|
|
end
|
|
RX_RESPONSE_ADRESS:
|
|
begin
|
|
|
|
end
|
|
RX_DATA0_1:
|
|
begin
|
|
|
|
end
|
|
RX_DATA0_2:
|
|
begin
|
|
|
|
end
|
|
RX_DATA0_3:
|
|
begin
|
|
|
|
end
|
|
RX_DATA0_4:
|
|
begin
|
|
|
|
end
|
|
RX_DATA0_5:
|
|
begin
|
|
|
|
end
|
|
RX_DATA0_6:
|
|
begin
|
|
|
|
end
|
|
RX_DATA0_7:
|
|
begin
|
|
|
|
end
|
|
RX_DATA0_8:
|
|
begin
|
|
|
|
end
|
|
RX_RESPONSE_DATA0_1:
|
|
begin
|
|
end
|
|
|
|
RX_DATA1_1:
|
|
begin
|
|
|
|
end
|
|
RX_DATA1_2:
|
|
begin
|
|
|
|
end
|
|
RX_DATA1_3:
|
|
begin
|
|
|
|
end
|
|
RX_DATA1_4:
|
|
begin
|
|
|
|
end
|
|
RX_DATA1_5:
|
|
begin
|
|
|
|
end
|
|
RX_DATA1_6:
|
|
begin
|
|
|
|
end
|
|
RX_DATA1_7:
|
|
begin
|
|
|
|
end
|
|
RX_DATA1_8:
|
|
begin
|
|
|
|
end
|
|
RX_RESPONSE_DATA1_1:
|
|
begin
|
|
end
|
|
RX_DELAY_BYTES:
|
|
begin
|
|
|
|
end
|
|
RX_NACK:
|
|
begin
|
|
|
|
|
|
end
|
|
RX_STOP:
|
|
begin
|
|
|
|
|
|
end
|
|
default:
|
|
begin
|
|
count_receive_data <= 12'd4095;
|
|
fifo_rx_wr_en <= 1'b0;
|
|
count_rx <= 2'd3;
|
|
end
|
|
endcase
|
|
end
|
|
end
|
|
|
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
|
|
No newline at end of file
|
No newline at end of file
|
