| Line 194... |
Line 194... |
//STATE CONTROL
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//STATE CONTROL
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reg [5:0] state_tx;
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reg [5:0] state_tx;
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reg [5:0] next_state_tx;
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reg [5:0] next_state_tx;
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//ASSIGN REGISTERS TO BIDIRETIONAL PORTS
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//ASSIGN REGISTERS TO BIDIRETIONAL PORTS
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assign SDA = (DATA_CONFIG_REG[0] == 1'b1 & DATA_CONFIG_REG[1] == 1'b0)?SDA_OUT:1'bz;
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assign SDA =(DATA_CONFIG_REG[0] == 1'b1 & DATA_CONFIG_REG[1] == 1'b0 & state_tx != RESPONSE_CIN & state_tx != RESPONSE_ADDRESS & state_tx != RESPONSE_DATA0_1 & state_tx != RESPONSE_DATA1_1)?SDA_OUT:SDA_OUT_RX;
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assign SCL = (DATA_CONFIG_REG[0] == 1'b1 & DATA_CONFIG_REG[1] == 1'b0)?BR_CLK_O:1'bz;
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assign SCL = (DATA_CONFIG_REG[0] == 1'b1 & DATA_CONFIG_REG[1] == 1'b0)?BR_CLK_O:BR_CLK_O_RX;
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//STANDARD ERROR
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//STANDARD ERROR
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assign ERROR = (DATA_CONFIG_REG[0] == 1'b1 & DATA_CONFIG_REG[1] == 1'b1)?1'b1:1'b0;
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assign ERROR = (DATA_CONFIG_REG[0] == 1'b1 & DATA_CONFIG_REG[1] == 1'b1)?1'b1:1'b0;
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| Line 916... |
Line 918... |
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end
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end
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CONTROLIN_4:
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CONTROLIN_4:
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begin
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begin
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if(count_send_data < DATA_CONFIG_REG[13:2])
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if(count_send_data < DATA_CONFIG_REG[13:2])
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begin
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begin
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count_send_data <= count_send_data + 12'd1;
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count_send_data <= count_send_data + 12'd1;
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SDA_OUT<=fifo_tx_data_out[3:3];
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SDA_OUT<=fifo_tx_data_out[3:3];
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if(count_receive_data < DATA_CONFIG_REG[13:2]/12'd4)
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if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
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begin
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begin
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BR_CLK_O <= 1'b0;
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BR_CLK_O <= 1'b0;
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end
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end
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else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
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else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
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begin
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begin
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| Line 954... |
Line 954... |
if(count_send_data < DATA_CONFIG_REG[13:2])
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if(count_send_data < DATA_CONFIG_REG[13:2])
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begin
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begin
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count_send_data <= count_send_data + 12'd1;
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count_send_data <= count_send_data + 12'd1;
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SDA_OUT<=fifo_tx_data_out[4:4];
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SDA_OUT<=fifo_tx_data_out[4:4];
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if(count_receive_data < DATA_CONFIG_REG[13:2]/12'd4)
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if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
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begin
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begin
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BR_CLK_O <= 1'b0;
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BR_CLK_O <= 1'b0;
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end
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end
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else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
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else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
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begin
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begin
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| Line 974... |
Line 974... |
count_send_data <= 12'd0;
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count_send_data <= 12'd0;
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SDA_OUT<=fifo_tx_data_out[5:5];
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SDA_OUT<=fifo_tx_data_out[5:5];
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end
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end
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end
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end
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CONTROLIN_6:
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CONTROLIN_6:
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begin
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begin
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if(count_send_data < DATA_CONFIG_REG[13:2])
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if(count_send_data < DATA_CONFIG_REG[13:2])
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begin
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begin
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| Line 1074... |
Line 1072... |
count_send_data <= count_send_data + 12'd1;
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count_send_data <= count_send_data + 12'd1;
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//LETS TRY USE THIS BUT I DONT THINK IF WORKS
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//LETS TRY USE THIS BUT I DONT THINK IF WORKS
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RESPONSE<= SDA;
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RESPONSE<= SDA;
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if(count_receive_data < DATA_CONFIG_REG[13:2]/12'd4)
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if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
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begin
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begin
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BR_CLK_O <= 1'b0;
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BR_CLK_O <= 1'b0;
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end
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end
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else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
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else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
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begin
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begin
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| Line 1210... |
Line 1208... |
ADDRESS_5:
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ADDRESS_5:
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begin
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begin
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if(count_send_data < DATA_CONFIG_REG[13:2])
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if(count_send_data < DATA_CONFIG_REG[13:2])
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begin
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begin
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count_send_data <= count_receive_data + 12'd1;
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count_send_data <= count_send_data + 12'd1;
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SDA_OUT<=fifo_tx_data_out[12:12];
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SDA_OUT<=fifo_tx_data_out[12:12];
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if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
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if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
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begin
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begin
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BR_CLK_O <= 1'b0;
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BR_CLK_O <= 1'b0;
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| Line 1381... |
Line 1379... |
DATA0_2:
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DATA0_2:
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begin
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begin
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if(count_send_data < DATA_CONFIG_REG[13:2])
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if(count_send_data < DATA_CONFIG_REG[13:2])
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begin
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begin
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count_send_data <= count_receive_data + 12'd1;
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count_send_data <= count_send_data + 12'd1;
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SDA_OUT<=fifo_tx_data_out[17:17];
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SDA_OUT<=fifo_tx_data_out[17:17];
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if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
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if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
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begin
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begin
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BR_CLK_O <= 1'b0;
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BR_CLK_O <= 1'b0;
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| Line 1979... |
Line 1977... |
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BR_CLK_O <= 1'b1;
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BR_CLK_O <= 1'b1;
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if(count_send_data < DATA_CONFIG_REG[13:2])
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if(count_send_data < DATA_CONFIG_REG[13:2])
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begin
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begin
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count_send_data <= count_receive_data + 12'd1;
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count_send_data <= count_send_data + 12'd1;
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if(count_send_data < DATA_CONFIG_REG[13:2]/12'd2-12'd2)
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if(count_send_data < DATA_CONFIG_REG[13:2]/12'd2-12'd2)
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begin
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begin
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SDA_OUT<=1'b0;
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SDA_OUT<=1'b0;
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end
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end
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| Line 2180... |
Line 2178... |
|
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if( count_receive_data != DATA_CONFIG_REG[13:2])
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if( count_receive_data != DATA_CONFIG_REG[13:2])
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begin
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begin
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next_state_rx = RESPONSE_CIN;
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next_state_rx = RESPONSE_CIN;
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end
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end
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else
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else if(RESPONSE == 1'b0)//ACK
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begin
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begin
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next_state_rx = ADDRESS_1;
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next_state_rx = DELAY_BYTES;
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end
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else if(RESPONSE == 1'b1)//NACK
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begin
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next_state_rx = NACK;
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end
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end
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end
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end
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//NOW SENDING ADDRESS
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//NOW SENDING ADDRESS
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ADDRESS_1:
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ADDRESS_1:
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| Line 2281... |
Line 2283... |
begin
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begin
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if( count_receive_data != DATA_CONFIG_REG[13:2])
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if( count_receive_data != DATA_CONFIG_REG[13:2])
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begin
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begin
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next_state_rx = RESPONSE_ADDRESS;
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next_state_rx = RESPONSE_ADDRESS;
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end
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end
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else
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else if(RESPONSE == 1'b0)//ACK
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begin
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begin
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next_state_rx = DATA0_1;
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next_state_rx = DELAY_BYTES;
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end
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else if(RESPONSE == 1'b1)//NACK
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begin
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next_state_rx = NACK;
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end
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end
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end
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end
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//data in
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//data in
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DATA0_1:
|
DATA0_1:
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begin
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begin
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| Line 2377... |
Line 2383... |
next_state_rx = RESPONSE_DATA0_1;
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next_state_rx = RESPONSE_DATA0_1;
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end
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end
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end
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end
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RESPONSE_DATA0_1:
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RESPONSE_DATA0_1:
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begin
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begin
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|
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if( count_receive_data != DATA_CONFIG_REG[13:2])
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if( count_receive_data != DATA_CONFIG_REG[13:2])
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begin
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begin
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next_state_rx = RESPONSE_DATA0_1;
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next_state_rx = RESPONSE_DATA0_1;
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end
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end
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else
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else if(RESPONSE == 1'b0)//ACK
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begin
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begin
|
next_state_rx = DATA1_1;
|
next_state_rx = DELAY_BYTES;
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end
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else if(RESPONSE == 1'b1)//NACK
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begin
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next_state_rx = NACK;
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end
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end
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end
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end
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//second byte
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//second byte
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DATA1_1:
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DATA1_1:
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begin
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begin
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if( count_receive_data != DATA_CONFIG_REG[13:2])
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if( count_receive_data != DATA_CONFIG_REG[13:2])
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begin
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begin
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| Line 2480... |
Line 2490... |
end
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end
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RESPONSE_DATA1_1:
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RESPONSE_DATA1_1:
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begin
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begin
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if( count_receive_data != DATA_CONFIG_REG[13:2])
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if( count_receive_data != DATA_CONFIG_REG[13:2])
|
begin
|
begin
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next_state_rx = RESPONSE_DATA1_1;
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next_state_rx = RESPONSE_DATA0_1;
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end
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end
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else
|
else if(RESPONSE == 1'b0)//ACK
|
begin
|
begin
|
next_state_rx = DELAY_BYTES;
|
next_state_rx = DELAY_BYTES;
|
end
|
end
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else if(RESPONSE == 1'b1)//NACK
|
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begin
|
|
next_state_rx = NACK;
|
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end
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end
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end
|
DELAY_BYTES://THIS FORM WORKS
|
DELAY_BYTES://THIS FORM WORKS
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begin
|
begin
|
|
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| Line 3282... |
Line 3296... |
begin
|
begin
|
count_receive_data <= count_receive_data + 12'd1;
|
count_receive_data <= count_receive_data + 12'd1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
|
|
|
|
|
if(count_rx == 2'd0)
|
|
begin
|
|
count_rx <= count_rx + 2'd1;
|
|
//SDA_OUT<=fifo_tx_data_out[8:8];
|
|
end
|
|
else if(count_rx == 2'd1)
|
|
begin
|
|
count_rx <= count_tx + 2'd1;
|
|
//SDA_OUT<=fifo_tx_data_out[16:16];
|
|
end
|
|
else if(count_rx == 2'd2)
|
|
begin
|
|
count_rx <= count_rx + 2'd1;
|
|
//SDA_OUT<=fifo_tx_data_out[24:24];
|
|
end
|
|
else if(count_rx == 2'd3)
|
|
begin
|
|
count_rx <= 2'd0;
|
|
end
|
|
|
count_receive_data <= 12'd0;
|
count_receive_data <= 12'd0;
|
fifo_rx_wr_en <= 1'b1;
|
|
end
|
end
|
|
|
|
|
end
|
end
|
STOP:
|
STOP:
|
