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https://opencores.org/ocsvn/apbi2c/apbi2c/trunk
[/] [apbi2c/] [trunk/] [rtl/] [module_i2c.v] - Diff between revs 22 and 23
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| Rev 22 |
Rev 23 |
| Line 223... |
Line 223... |
end
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end
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else if(DATA_CONFIG_REG[0] == 1'b1 && (fifo_tx_f_full == 1'b1 || fifo_tx_f_empty == 1'b0) && DATA_CONFIG_REG[1] == 1'b1)
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else if(DATA_CONFIG_REG[0] == 1'b1 && (fifo_tx_f_full == 1'b1 || fifo_tx_f_empty == 1'b0) && DATA_CONFIG_REG[1] == 1'b1)
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begin
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begin
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next_state_tx = IDLE;
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next_state_tx = IDLE;
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end
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end
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else if(DATA_CONFIG_REG[0] == 1'b1 && (fifo_tx_f_full == 1'b1 || fifo_tx_f_empty == 1'b0) && DATA_CONFIG_REG[1] == 1'b0 && count_timeout < TIMEOUT_TX)
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else if(DATA_CONFIG_REG[0] == 1'b1 && ((fifo_tx_f_full == 1'b0 && fifo_tx_f_empty == 1'b0) || fifo_tx_f_full == 1'b1) && DATA_CONFIG_REG[1] == 1'b0 && count_timeout < TIMEOUT_TX)
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begin
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begin
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next_state_tx = START;
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next_state_tx = START;
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end
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end
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| Line 785... |
Line 785... |
begin
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begin
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count_send_data <= 12'd0;
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count_send_data <= 12'd0;
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SDA_OUT<= 1'b1;
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SDA_OUT<= 1'b1;
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BR_CLK_O <= 1'b1;
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BR_CLK_O <= 1'b1;
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end
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end
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else if(DATA_CONFIG_REG[0] == 1'b1 && (fifo_tx_f_full == 1'b1 ||fifo_tx_f_empty == 1'b0) && DATA_CONFIG_REG[1] == 1'b0)
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else if(DATA_CONFIG_REG[0] == 1'b1 && ((fifo_tx_f_empty == 1'b0 && fifo_tx_f_full == 1'b0 )|| fifo_tx_f_full == 1'b1 ) && DATA_CONFIG_REG[1] == 1'b0)
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begin
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begin
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count_send_data <= count_send_data + 12'd1;
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count_send_data <= count_send_data + 12'd1;
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SDA_OUT<=1'b0;
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SDA_OUT<=1'b0;
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end
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end
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else if(DATA_CONFIG_REG[0] == 1'b1 && (fifo_tx_f_full == 1'b1 ||fifo_tx_f_empty == 1'b0) && DATA_CONFIG_REG[1] == 1'b1)
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else if(DATA_CONFIG_REG[0] == 1'b1 && (fifo_tx_f_full == 1'b1 ||fifo_tx_f_empty == 1'b0) && DATA_CONFIG_REG[1] == 1'b1)
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| Line 2580... |
Line 2580... |
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case(state_rx)
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case(state_rx)
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IDLE:
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IDLE:
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begin
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begin
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SDA_OUT_RX<= SDA;
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BR_CLK_O_RX<=SCL;
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if(((fifo_rx_f_full == 1'b0 && fifo_rx_f_empty == 1'b0) || (fifo_rx_f_full == 1'b0 && fifo_rx_f_empty == 1'b1)) && DATA_CONFIG_REG[1] == 1'b1)
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if(((fifo_rx_f_full == 1'b0 && fifo_rx_f_empty == 1'b0) || (fifo_rx_f_full == 1'b0 && fifo_rx_f_empty == 1'b1)) && DATA_CONFIG_REG[1] == 1'b1)
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begin
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begin
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SDA_OUT_RX<= SDA;
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BR_CLK_O_RX<=SCL;
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count_receive_data <= count_receive_data + 12'd1;
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count_receive_data <= count_receive_data + 12'd1;
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end
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end
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else
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else
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begin
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begin
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SDA_OUT_RX<= SDA_OUT_RX;
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BR_CLK_O_RX<=BR_CLK_O_RX;
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count_receive_data <= count_receive_data;
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count_receive_data <= count_receive_data;
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end
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end
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end
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end
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START:
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START:
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| Line 3359... |
Line 3362... |
begin
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begin
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count_timeout <= 12'd0;
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count_timeout <= 12'd0;
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end
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end
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else
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else
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begin
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begin
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if(count_timeout <= TIMEOUT_TX)
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if(count_timeout <= TIMEOUT_TX && state_tx == IDLE)
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begin
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begin
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if(SDA == 1'b0 && SCL == 1'b0)
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if(SDA == 1'b0 && SCL == 1'b0)
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count_timeout <= count_timeout + 12'd1;
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count_timeout <= count_timeout + 12'd1;
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end
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end
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else
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else
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