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https://opencores.org/ocsvn/apbi2c/apbi2c/trunk
[/] [apbi2c/] [trunk/] [rtl/] [module_i2c.v] - Diff between revs 2 and 4
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//// Author(s): - Felipe Fernandes Da Costa, fefe2560@gmail.com
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//// Author(s): - Felipe Fernandes Da Costa, fefe2560@gmail.com
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//// Ronal Dario Celaya
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//// Ronal Dario Celaya ,rcelaya.dario@gmail.com
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/////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////
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//// Copyright (C) 2009 Authors and OPENCORES.ORG
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//// Copyright (C) 2009 Authors and OPENCORES.ORG
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*/
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*/
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assign SDA = SDA_OUT;
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assign SDA = SDA_OUT;
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assign SCL = BR_CLK_O;
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assign SCL = BR_CLK_O;
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//STANDARD ERROR
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assign ERROR = (DATA_CONFIG_REG[0] == 1'b1 & DATA_CONFIG_REG[1] == 1'b1)?1'b1:1'b0;
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//COMBINATIONAL BLOCK TO TX
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//COMBINATIONAL BLOCK TO TX
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always@(*)
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always@(*)
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begin
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begin
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//OBEYING SPEC
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//OBEYING SPEC
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if(DATA_CONFIG_REG[0] == 1'b0 && fifo_tx_f_full == 1'b0 && DATA_CONFIG_REG[1] == 1'b0)
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if(DATA_CONFIG_REG[0] == 1'b0 && fifo_tx_f_full == 1'b0 && DATA_CONFIG_REG[1] == 1'b0)
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begin
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begin
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next_state_tx = TX_IDLE;
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next_state_tx = TX_IDLE;
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end
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end
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else
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else if(DATA_CONFIG_REG[0] == 1'b1 && fifo_tx_f_full == 1'b1 && DATA_CONFIG_REG[1] == 1'b1)
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begin
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next_state_tx = TX_IDLE;
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end
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else if(DATA_CONFIG_REG[0] == 1'b1 && fifo_tx_f_full == 1'b1 && DATA_CONFIG_REG[1] == 1'b0)
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begin
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begin
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next_state_tx = TX_START;
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next_state_tx = TX_START;
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end
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end
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begin
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begin
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fifo_tx_rd_en <= 1'b0;
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fifo_tx_rd_en <= 1'b0;
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if(DATA_CONFIG_REG[0] == 1'b0 && fifo_tx_f_full == 1'b0)
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if(DATA_CONFIG_REG[0] == 1'b0 && fifo_tx_f_full == 1'b0 && DATA_CONFIG_REG[1] == 1'b0)
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begin
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begin
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count_send_data <= 12'd0;
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count_send_data <= 12'd0;
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SDA_OUT<= 1'b1;
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SDA_OUT<= 1'b1;
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BR_CLK_O <= 1'b1;
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BR_CLK_O <= 1'b1;
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end
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end
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else
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else if(DATA_CONFIG_REG[0] == 1'b1 && fifo_tx_f_full == 1'b1 && DATA_CONFIG_REG[1] == 1'b0)
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begin
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begin
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count_send_data <= count_send_data + 12'd1;
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count_send_data <= count_send_data + 12'd1;
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SDA_OUT<=1'b0;
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SDA_OUT<=1'b0;
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end
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end
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else if(DATA_CONFIG_REG[0] == 1'b1 && fifo_tx_f_full == 1'b1 && DATA_CONFIG_REG[1] == 1'b1)
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begin
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count_send_data <= 12'd0;
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SDA_OUT<= 1'b1;
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BR_CLK_O <= 1'b1;
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end
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end
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end
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TX_START:
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TX_START:
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begin
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begin
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